From 0d6faf2bd0d12642e8b2c428d62c285f4ee28b9d Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 7 Dec 2015 16:58:54 +0800 Subject: [PATCH] armv8/ls1043a: Implement workaround for PEX erratum A009929 Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 16 ++++++++++++++++ .../arm/include/asm/arch-fsl-layerscape/config.h | 1 + .../asm/arch-fsl-layerscape/immap_lsch2.h | 1 + 3 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 984eaf903e..23d6b73e3d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -197,6 +197,19 @@ int sata_init(void) } #endif +static void erratum_a009929(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009929 + struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; + u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); + + rstrqmr1 |= 0x00000400; + gur_out32(&gur->rstrqmr1, rstrqmr1); + writel(0x01000000, dcsr_cop_ccp); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -216,6 +229,9 @@ void fsl_lsch2_early_init_f(void) */ out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + /* Erratum */ + erratum_a009929(); } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6e5224ea1c..49b113dc59 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -166,6 +166,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009929 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 65a785cd28..21b803ff0f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -12,6 +12,7 @@ #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) -- 2.25.1