From 07e1c0ae83faff57477392be87734128db5e1b14 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 11 Aug 2016 14:02:51 +0800 Subject: [PATCH] imx: iomux: fix snvs usage for i.MX6ULL MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: "Benoît Thébaudeau" --- arch/arm/imx-common/iomux-v3.c | 11 ++++++++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + arch/arm/include/asm/imx-common/iomux-v3.h | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 2612e09f13..392f4bcb99 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -42,6 +42,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #ifdef CONFIG_IOMUX_LPSR u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT; +#ifdef CONFIG_MX7 if (lpsr == IOMUX_CONFIG_LPSR) { base = (void *)IOMUXC_LPSR_BASE_ADDR; mux_mode &= ~IOMUX_CONFIG_LPSR; @@ -49,9 +50,17 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; } +#else + if (is_mx6ull()) { + if (lpsr == IOMUX_CONFIG_LPSR) { + base = (void *)IOMUXC_SNVS_BASE_ADDR; + mux_mode &= ~IOMUX_CONFIG_LPSR; + } + } +#endif #endif - if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs) + if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); if (sel_input_ofs) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3bcb1a81a3..8bb36eb9de 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -182,6 +182,7 @@ #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) +#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 2e499681cf..e0f83505ce 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -85,12 +85,12 @@ typedef u64 iomux_v3_cfg_t; #define NO_PAD_CTRL (1 << 17) -#ifdef CONFIG_MX7 - -#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 #define IOMUX_CONFIG_LPSR 0x8 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) +#ifdef CONFIG_MX7 + +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 #define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) #define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) -- 2.25.1