EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0

This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0.
It also corrects the gpio offset calculations.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

EXYNOS5: CLOCK: Add BPLL support

This patch adds support for BPLL clock.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0

The patch adds the memory initialization sequence of DDR3.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0

Add new clock values for Exynos5250 Rev 1.0

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0

Define additional registers for clock control in Exynos5250 Rev 1.0

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

SMDK5250: Add smdk5250-uboot-spl.lds

Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.

Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

SMDK5250: SPL: Define parametric board initializer

Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

ARCH: SPL: Add parametric board initializer

Add a structure for table-driven configuration mechanism such that no recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

ARM: Remove unused stack and irq config defines

CONFIG_STACKSIZE is not referenced anywhere except on AVR32, but present
in most ARM board config files.

IRQs are only enabled for 1 config, so remove the unused config options
for IRQ and FIQ stack size as well.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>

arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0

save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
This patch removes save_boot_params_default() and put the equivalent in start.S

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>

tegra20: Remove armv4t build flags

These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9.  Now that the ARM7TDMI support
is split into a separate SPL, this is no longer necessary.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

spl: fix SPL build of private libgcc

This fixes the SPL build to link with the SPL version of libgcc if
USE_PRIVATE_LIBGCC is set to "yes".  Previously it was linking with
the libgcc from the normal u-boot build because it gets set in
PLATFORM_LIBS and passed down the to the SPL build.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

arm: enable libgcc build for SPL

Enable the building of private libgcc for SPL

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: enable SPL for tegra20 boards

Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards.  Also remove redundant code from u-boot that is not
contained in SPL.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: move SDRAM param save to later in boot

Move warmboot_save_sdram_params() to later in the boot sequence.  This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: add u-boot-*-tegra.bin targets

Add target for tegra20 u-boot image.  This is a concatenation of tegra
spl and normal u-boot binaries.  For non-devicetree builds this is
named "u-boot-nodtb-tegra.bin" for devicetree builds is named
"u-boot-dtb-tegra.bin".

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

ARM: add tegra20 support to arm720t

Add support for tegra20 arm7 boot processor.  This processor is used
to power on the Cortex A9 and transfer control to it.  In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical except for cache and MMU.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: remove timer_init from SPL build

Don't use timer_init from tegra board.c.  This comes out of arm720t
for the SPL build.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

ARM: Fix arm720t SPL build

Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

MAKEALL: update to work with new boards.cfg syntax

Update MAKEALL to handle the optional SPL CPU field that was added to
boards.cfg.  This impacts the cases in MAKEALL that have to match
against CPU type (field 3).  In these cases use ':' as a field
separator to split the u-boot CPU from the SPL CPU.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

mkconfig: remove bashisms and cleanup config.mk generation

This adds some cleanup to mkconfig related to SPL support.  Bash
specific script has been replaced with awk for better shell
compatibility.  config.mk generation is done through a subshell and
single redirect to improve readability.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: make board mkdir commands unconditional

Change the mkdir commands for the object directories to be
unconditional.  This fixes an issue when building for SPL where
SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: tec: add tegra20-common-post.h

Add tegra20-common-post.h to be consistent with other tegra20 boards.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: rename CONFIG_MACH_TEGRA_GENERIC

Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA.
The meaning of the config options is now:

CONFIG_TEGRA - Any tegra chip
CONFIG_TEGRA20 - A tegra20 family chip
CONFIG_TEGRA30 - A tegra30 family chip (not added yet)

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common

In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common.  This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

tegra20: rename tegra2 -> tegra20

This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>

ARM: add Raspberry Pi model B board, using BCM2835 SoC

The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM,
contains an SMSC 9512 USB LAN/Hub chip, and various IO connectors.
For more details, see http://www.raspberrypi.org/.

Various portions (cache enable, MACH_TYPE setup, RAM size limit, stack
relocation to top of RAM) extracted from work by:
Oleksandr Tymoshenko <gonzo@bluezbox.com>.

GPIO driver enablement by Vikram Narayanan <vikram186@gmail.com>.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Tom Rini <trini@ti.com>

ARM: add basic support for the Broadcom BCM2835 SoC

This SoC is used in the Raspberry Pi, for example.

For more details, see:
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf.

Initial support is enough to boot to a serial console, execute a minimal
set of U-Boot commands, download data over a serial port, and boot a
Linux kernel. No storage or network drivers are implemented.

GPIO driver originally by Vikram Narayanan <vikram186@gmail.com>
with many fixes from myself.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

ARM: arm1176: enable instruction cache in arch_cpu_init()

Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107x.

Cc: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

README: fix references to config_cmd_default.h

All usage of config_cmd_default.h uses <> for the include statement.
Update the README to do the same, rather than using "".

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

snowball: Adding board specific cache cleanup routine

Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

armv7: Adding cpu specific cache managmenent

Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

u8500: Separating mmc config parameters from driver

Configuration in vexpress and u8500.v1 is different from what
is needed in u8500.v2.  As such, card configuration specifics need
to reside in the board file rather than the driver.

Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>

u8500: Enabling power to MMC device on AB8500 V2

Register mapping has changed on power control chip between
the first and second revision.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>

u8500: Moving processor-specific functions to cpu area.

Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>

snowball: applying power to LAN and GBF controllers

LAN and GBF need to be powered explicitely, doing so with
interface to AB8500 companion chip.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

snowball: Moving to ux500.v2 addess scheme for PRCMU access

Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

snowball: Adding CPU clock initialisation

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

snowball: Adding architecture dependent initialisation

Enabling timers and clocks in PRCMU and cleaning up mailbox.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

u8500: Moving prcmu to cpu directory

This is to allow the prcmu functions to be used by multiple
u8500-based processors.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>

snowball: Add support for ux500 based snowball board

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Conflicts:

drivers/gpio/Makefile

davinci, c6x: Always use C version of reset code

We can safely use the same reset code written in C for both Davinci and
C6X platforms.  In addition the C version of the code is marginally
smaller on Davinci.

Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>

arm: omap: Fix switching back to nandecc sw.

Orjan Friberg wrote at [1]:

"For the beagleboard, ecc.size is not explicitly set when doing 'nandecc
sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's
set to 256 bytes.

When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when
changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly
the format has changed."

No patch has been submitted and the issue was still present. This patch
adds the mentioned solution. Tested on a tam3517 board.

[1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html

cc: Orjan Friberg <of@flatfrog.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>

davinci: enbw_cmc: change switch init behaviour

change the behaviour of switch initialization:

- rename "pwl" to "lan" in hwconfig parameter
  "lan" = port 1 with phy addr 2
  "lmn" = port 2 with phy addr 3

- if we have a valid switch config file in flash, do not
  evaluate the settings in the hwconfig "lan" or "lmn"
  subcommand.

- if we have no valid switch config file in flash, start
  the switch with default values, if we have a "lan" or
  a "lmn" hwconfig subcommand. If no "lan" or "lmn" is
  found in hwconfig, do nothing with the switch.

Signed-off-by: Heiko Schocher <hs@denx.de>

am33xx evm: Update secure_emif_sdram_config during ddr init

This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.

During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.

Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.

Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>

da8xx/hawkboard: Add support for ohci host controller

Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.

Move the usb header for da8xx platforms under arch-davinci.

Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>

armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stack

Make sure that when we setup the stack before calling s_init() we have
the stack have 8-byte alignment for ABI compliance.

Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>

omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms

Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms.  As part of this we change some of the macros that are used
to be more clear.  Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END.  On am335x evm we
should have been doing this initially and do now.

Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>

am335x evm: Enable support for spi0

Signed-off-by: Tom Rini <trini@ti.com>

am33xx: Add support, update omap3 McSPI driver

Signed-off-by: Tom Rini <trini@ti.com>

am335x evm: Enable MMC1 pinmux

MMC1 is available in profile 2 on the GP EVM and is exposed on the
expansion header on beaglebone.

Signed-off-by: Tom Rini <trini@ti.com>

am33xx: Correct MMC1, remove MMC2 support

- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value

Signed-off-by: Tom Rini <trini@ti.com>

am335x evm: Initial support for AM335x GP EVM Profiles

The AM335x GP EVM can have one of 8 different profiles selected.  Each
profile has a different set of peripherals and requires different pinmux
configurations that conflict with other profiles.  i2c1 is an example of
a conflicted mux currently.

Signed-off-by: Tom Rini <trini@ti.com>

sc_sps_1: Adjust board config to use 'mxs' SoC code

Fix build failure due the move of mx28 code to 'mxs' SoC.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>

rtc: imxdi: Initial support

Add support for Freescale's i.MX DryIce RTC, present on i.MX25.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

MX28: Add SchulerControl SC_SPS_1 platform

This i.MX28 platform supports the following:
* 2x FEC ethernet
* USB on USBH0
* I2C EEPROM
* SPI NVRAM
* LEDs

Signed-off-by: Marek Vasut <marex@denx.de>

i.MX28: bug fixes in PMU configuration code

Signed-off-by: Stathis Voukelatos <stathis.voukelatos@linn.co.uk>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>

MX28: Move the u-boot.bd info CPUDIR/SOCDIR

This gets us rid of duplication of the same file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

vision2: do not overwrite the console

On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

mx51evk: do not overwrite the console

On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

MX5: mx53loco: do not overwrite the console

On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>

MX28: Fix MXS MMC DMA issues

The DMA didn't work properly because the DMA descriptor wasn't
properly cleaned after it was used once. Also, the DMA_ENABLE bit
was enabled/disabled too late.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

MX28: Transfer small blocks via PIO in MXS MMC

Large blocks (> 512b) shall be transfered via DMA to make
things a bit faster.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

MX28: Split out the PIO and DMA transfer functions

Move DMA and PIO data transfer parts into separate functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

MX28: Fix up the MMC driver DMA mode

The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1.
Also, it was using SSP0 DMA channel for all SSP devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCs

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

mxs: Clarify why we poweroff in case of brownout in 5v conflict

If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable
but this wasn't clear on code so a comment has been added to clarify
it.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

mxs: Reowork SPL to use 'mxs' prefix for methods

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

mxs: prefix register structs with 'mxs' prefix

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

mxs: prefix register acessor macros with 'mxs' prefix

As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

mxs: reorganize source directory for easy sharing of code in i.MXS SoCs

Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>

mx28evk: Turn on caches

Turn on data and instruction caches.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

MX28: use a clear name for DDR2 initialization

The mx28 prefix has been added to the initialization data and function
so it is clear by which SoC it is used as i.MX233 will have a specific
one. While on that, we also change it to static.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>

Add support for Bluegiga APX4 Development Kit

This adds support for Bluegiga APX4 Development Kit. It is built around
Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC,
RTC and USB. APX4 has only one ethernet port.

Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>

MX28: extend print_cpuinfo() to use chip information

The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

MX28: SPI: Add DMA transfer support

The DMA transfers happen only if the transfered data are larger
than 512 bytes. Otherwise PIO is used. This is a small speed
optimization.

The DMA transfer doesn't work if unaligned transfer is requested
due to the limitation of the DMA controller. This has to be fixed
by introducing generic bounce buffer. Therefore the DMA feature
is now disabled by default.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

MX28: SPI: Pull out the PIO transfer function

Pull out all the PIO transfer logic into separate function,
so DMA can be added.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

MX28: SPI: Refactor spi_xfer a bit

This makes it easier to adapt for addition of DMA support.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>

imx: Use a clear identification of an unidentified CPU type

In case an unidentified CPU type is detected it now returns
i.MX??, in a const char.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

at91: Add support for taskit AT91SAM9G20 boards.

This adds support for the AT91SAM9G20 boards by taskit GmbH.
Both boards, Stamp9G20 and PortuxG20, are integrated in one
file. PortuxG20 is basically a SBC built around the Stamp9G20.

Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.deve@googlemail.com>

Enable the EMAC clock in at91_macb_hw_init().

Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

MAINTAINERS: fix Andreas Bießmann AVR32 entry

The grasshopper board is a avr32 based device and belongs therefore to the avr32
section.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

MAINTAINERS: fix entry of Ilko Iliev

These boards have ARM cores, move to the ARM section.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

arm : Atmel : add at91sam9x5ek board support

Add at91sam9x5ek board support, this board support the following SoCs
  AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

doc/git-mailrc: update at91 and avr32

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

am335x_evm: enable SMSC PHY driver

Beaglebone uses SMSC PHY which works incorrectly with generic PHY
driver so enable SMSC PHY driver to fix networking problems on
Beaglebone.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>

OMAP3: fix DRAM size for IGEP-based boards.

The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the
LPDDR memory consist on two dies of 256MiB.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>

DaVinci DA8xx: fix set_cpu_clk_info()

For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:

  [...snip...]
  ARM frequency = 300 MHz
  DSP frequency = -536870913 MHz
  DDR frequency = 300 MHz

This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Hadli, Manjunath <manjunath.hadli@ti.com>
Cc: Heiko Schocher <hs@denx.de>

DaVinci DA8xx: replace magic number for DDR speed

Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>

DaVinci DA850: UART2 clock ID comes from ASYNC3

On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>

DaVinci DA8xx: tidy up clock ID definition

Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>

doc/git-mailrc: Update 'ti' alias

Remove Sandeep, thanks for all the hard work!

Signed-off-by: Tom Rini <trini@ti.com>

dm: Move OMAP GPIO driver to drivers/gpio/

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>

dm: Select CONFIG_SPL_GPIO_SUPPORT on OMAP

This fixes the breakage with SPL on most OMAP boards after the GPIO
driver was moved.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>

am33xx: Rework pinmux functions

- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
  - Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.

Signed-off-by: Tom Rini <trini@ti.com>

am33xx evm: Add CONFIG_CMD_EEPROM and related

am33xx boards have at least one eeprom and in the case of beaglebones
with capes, more.

Signed-off-by: Tom Rini <trini@ti.com>

am33xx: Add support for TI AM335x StarterKit EVM

- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
  config_ddr with.
- Both of the above require filling in the header structure early, move
  it into the data section.

Signed-off-by: Tom Rini <trini@ti.com>

am33xx: Remove board/ti/am335x/evm.c

The intention has always been (and boards are to support) an i2c EEPROM
that will identify what hardware they are, allowing a single binary to
support multiple boards.  As such, remove the 'evm.c' file as there is
nothing EVM centric in it currently, only SoC peripheral configuration.

Signed-off-by: Tom Rini <trini@ti.com>

am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support

Signed-off-by: Tom Rini <trini@ti.com>