cros: exynos: enable cros-ec for smdk5250

This patch initiates cros-ec in board_init() to enable it for smdk5250.

This patch depends on the patch in the MMC series that brings in exynos5-dt.c.
Refer to http://patchwork.ozlabs.org/patch/240084.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

cros: exynos: add cros-ec device nodes to exynos5250-snow.dts

This patch adds cros-ec related device nodes to exynos5250-snow.dts.
It also adds a gpio node to exynos5250.dtsi.

Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

cros: adds cros_ec keyboard driver

This patch adds the driver for keyboard that's controlled by ChromeOS EC.

Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

cros: add LPC support for cros_ec

This patch adds LPC support for carrying out the cros_ec protocol.

Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

cros: exynos: add SPI support for cros_ec

This patch adds SPI support for carrying out the cros_ec protocol.

Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

cros: add I2C support for cros_ec

This patch adds I2C support for carrying out the cros_ec protocol.

Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

cros: add cros_ec driver

This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.

Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

Merge branch 'master' of git://git.denx.de/u-boot-net

phylib: add atheros ar803x phy

add atheros ar803x phy, used on the upcoming siemens boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

phylib: add natsemi dp83630 phy

add natsemi dp83630 phy, used on the upcoming siemens boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

net: update FTGMAC100 for MMU/D-cache support

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Tom Rini <trini@ti.com>

net: add Faraday FTMAC110 10/100Mbps ethernet support

Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:

(1) Tx DMA Buffer Address:
    1 bytes aligned: Invalid
    2 bytes aligned: O.K
    4 bytes aligned: O.K

(2) Rx DMA Buffer Address:
    1 bytes aligned: Invalid
    2 bytes aligned: O.K
    4 bytes aligned: Invalid!!!

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>

net: phy: supplement support for Micrel's KSZ9031

Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read

Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>

net: macb: add support for gigabit MAC

Add gigabit MAC support in macb driver
  - using IP version to distinguish whether MAC is GMAC

Signed-off-by: Bo Shen <voice.shen@atmel.com>

net: macb: using phylib to configure phy device

using phylib to configure phy device in macb driver

Signed-off-by: Bo Shen <voice.shen@atmel.com>

net: macb: using AT91FAMILY replace #ifdeferry

Using CONFIG_AT91FAMILY replace #ifdeferry for atmel SoC

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>

ARM: at91sam9n12: add network support with ksz8851_16mll

add network support with ksz8851_16mll on at91sam9n12ek board

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>

net: ks8851_mll: add ethernet support

The device interface is 16 bits wide.
All the available packets are read from the incoming fifo.

Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it>
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
[voice.shen@atmel.com: address comments from review results]
[voice.shen@atmel.com: clean up for submit]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>

phylib: Add Atheros AR8035 GETH PHY support

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>

add support for Xilinx 1000BASE-X phy (GTX)

commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell <coldwell@ll.mit.edu>
Date:   Tue Feb 19 08:27:33 2013 -0500

    Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)

Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>

net: Correct check for link-local target IP conflict

Make the link-local code conform more completely with the RFC.

This will prevent ARP queries for the target (such as while it is
rebooting) from causing the device to choose a different link-local
address, thinking that its address is in use by another machine.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

PHY: micrel.c: add support for KSZ9031

Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid
code duplication

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Joe Herschberger <joe.hershberger@gmail.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>

net/tftp: sparse fixes

tftp.c:464:17: warning: cast to restricted __be16
tftp.c:552:29: warning: cast to restricted __be16
tftp.c:640:33: warning: cast to restricted __be16
tftp.c:642:25: warning: cast to restricted __be16

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

net: make IPaddr type big endian

for use with sparse.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

net: Fix build regression in macb.c

The added weak symbol must not be static.

This was introduced in 416ce623fbad51af57660346ebb6f7befb88b3c9

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

net/macb: Add arch specific routine to get mdio control

SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently there is a fixed configuration in which only a
particular MAC can use the MDIO lines.

Call an arch specific function to take control of specific mdio lines at
runtime.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>

net/designware: Do not select MIIPORT for RGMII interface

Do not select MIIPORT for RGMII interface

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>

net: nfs: add dynamic wait period

This patch tackles the time out problem which leads to break the
boot process, when loading file over nfs. The patch does two things.

First of all, we just ignore messages that arrive with a rpc_id smaller
then the client id. We just interpret this messages as answers to
formaly timed out messages.

Second, when a time out occurs we double the time to wait, so that we
do not stress the server resending the last message.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>

NET: mvgbe: add support for Dove

Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

NET: mvgbe: add phylib support

This add phylib support to the Marvell GBE driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

NET: phy: add 88E1310 PHY initialization

This adds PHY initialization for Marvell Alaska 88E1310 PHY.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

pxe: add ipappend support

Add ipappend support to pass network device information to the kernel.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

net: Fix build regression in cmd_pxe.c

Not all boards define an SOC.  As a result, we can't depend on that.

This was introduced in 39f985536d3f0df5dba32c15b64ba2b5d32dd296

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

pxe: add support for per arch and SoC default paths

A pxelinux server setup for "default" menu is typically an x86 binary.
This does not work well with a mixed architecture setup. Extend the default
search to look for default-<arch>-<soc> and then default-<arch> before
falling back to just "default".

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

pxe: add support for ontimeout token

ontimeout is similar to default, but is the selection on menu timeout.
This is how cobbler sets a default. The label default is supposed to be
the default selection when <enter> is pressed. If both default and
ontimeout are set, last one parsed wins.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

pxe: simplify menu display and selection

Menus with lots of entries and long append lines are hard to read.
Just show a numbered list using the label or name and make the choice
by entering the number.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

pxe: always display a menu when present

The prompt flag is for displaying a "boot:" prompt in pxelinux. This
doesn't make sense for u-boot as we don't support the pxelinux command
interface. So we should just ignore prompt statements and always show the
menu if a menu is present.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

pxe: try bootz if bootm fails to find a valid image

Standard pxelinux servers will typically use a zImage rather than u-boot
image format, so fallback to bootz if bootm fails.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

bootz: un-staticize do_bootz

Make do_bootz available for other functions like do_bootm is.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

pxe: fix handling of different localboot values

Add support for value of -1 For localboot. A value of -1 means return to
u-boot prompt.

The localboot value is often 0, so we need to distinguish the value from
localboot being selected. A value of greater than or equal to 0 means
attempt local boot command.

If localboot is selected, we don't want to try other entries.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

pxe: make string parameters const

Convert a bunch of string parameters to be const.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

pxe: Use ethact setting for pxe

Get the MAC address using eth_getenv_enetaddr_by_index so that the MAC
address of ethact is used. This enables using the a NIC other than the
first one for PXE boot.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

net: add ICPlus PHY driver

The driver code was taken from Linux kernel source:
drivers/net/phy/icplus.c

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>

phy: export genphy_parse_link()

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>

net: Add sunxi (Allwinner) wemac driver

This patch adds support for the WEMAC, the ethernet controller included
in the Allwinner A10 SoC. It will get used in the upcoming A10 board
support.

From: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>

checkpatch: add ignore for network block comment style checking

When use checkpatch.pl to check network related patch, it will report
--->8---
WARNING: networking block comments don't use an empty /* line,
use /* Comment...
---<8---

So, add --ignore NETWORKING_BLOCK_COMMENT_STYLE into .checkpatch.conf
This will help to keep all driver include network related driver use
the same comment style

Signed-off-by: Bo Shen <voice.shen@atmel.com>

Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx

Merge branch 'master' of git://git.denx.de/u-boot-spi

ac14xx: rephrase network boot config for development

- remove the builtin 'rootpath' spec (according to U-Boot project
  policy) and require user provided environments to contain these
- rephrase the evaluation of the 'muster_nr' approach which allows to
  quickly switch among several network boot setups (make the setting
  transparent when empty, resulting in default DULG behaviour)
- reduce the ARP timeout for faster network boot

Signed-off-by: Gerhard Sittig <gsi@denx.de>

ac14xx: use the official product name everywhere

remove remaining "k6" code names, switch to the official 'ac14xx' name

Signed-off-by: Gerhard Sittig <gsi@denx.de>

ac14xx: remove obsolete board config items

- use the default baudrate table for serial communication
- remove hostname/boofile/rootpath defines which were not referenced elsewhere

Signed-off-by: Gerhard Sittig <gsi@denx.de>

ac14xx: re-order the recovery condition checks

re-order the conditions which make the recovery system startup: combine
those conditions which were explicitly initiated (key press, software
request) and those which post-process error conditions (installer issues)

Signed-off-by: Gerhard Sittig <gsi@denx.de>

ac14xx: minor improvement in diagnostics

- minor rewording of diagnostics output
- make diagnostics optional and off by default

Signed-off-by: Gerhard Sittig <gsi@denx.de>

ac14xx: cleanup comments in the board support

fix typos, minor rephrasing, remove obsolete notes and TODO items

Signed-off-by: Gerhard Sittig <gsi@denx.de>

ac14xx: fix a potential NULL deref in diagnostics

getenv() immediately after setenv() may perfectly legally return NULL, so
make sure to not deference an invalid pointer when creating diagnostic output

Signed-off-by: Gerhard Sittig <gsi@denx.de>

sf: Warn to use BAR for > 16MiB flashes

Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: Add debug messages on spi_flash_read_common

- Added debug's on spi_flash_read_common()
- Added space

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: Place the sf calls in proper order

Placed the sf calls in proper order - erase/write/read

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: Unify spi_flash write code

Move common flash write code into spi_flash_write_common().

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>

sf: Add flag status register polling support

Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.

Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

sf: Remove spi_flash_cmd_poll_bit()

There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

sf: spansion: Add support for S25FL512S_64K

Add support for Spansion S25FL512S_64K SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: stmicro: Add support for N25Q1024A

Add support for Numonyx N25Q1024A SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: stmicro: Add support for N25Q1024

Add support for Numonyx N25Q1024 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: stmicro: Add support for N25Q512A

Add support for Numonyx N25Q512A SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: stmicro: Add support for N25Q512

Add support for Numonyx N25Q512 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: Use spi_flash_addr() in write call

Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

sf: Add bank addr code in CONFIG_SPI_FLASH_BAR

Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.

It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

sf: Update sf read to support all sizes of flashes

This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.

The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)

With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

sf: Update sf to support all sizes of flashes

Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility

The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.

As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

sf: Read flash bank addr register at probe time

Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.

bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.

Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

sf: Discover the bank addr commands

Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.

Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: Add bank address register writing support

This patch provides support to program a flash bank address
register.

extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.

reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

spi: mxc_spi: Use DIV_ROUND_UP at appropriate places

This change slightly improves readability.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

spi: cf_qspi: Use DIV_ROUND_UP at appropriate place

This change slightly improves readability.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

sf: winbond: Add support for W25QXXXFV

Add support for Winbond W25QXXXFV SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: winbond: Add support for W25Q16DW

Add support for Winbond W25Q16DW SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: winbond: Add support for W25Q128FW

Add support for Winbond W25Q128FW SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: winbond: Update the names for W25Q 0x40XX ID's flash parts

Use the exact names for W25Q 0x40XX ID's flash parts, as the same
sizes of flashes comes with different ID's. so-that the distinguishes
becomes easy with this change.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

sf: spansion: Correct name of S25FL128S 64K Sector part

Corrected the name of S25FL128S 64K sector part SPI flash,
S25FL128S supported has been added in below commit
"sf: spansion: Add support for S25FL128S"
(sha1: 1bfb9f156aa66cca6bb9c773867a1f02a84b14be)

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Merge branch 'master' of git://git.denx.de/u-boot-arm

arm: optimize relocate_code routine

Use section symbols directly
Drop support for R_ARM_ABS32 record types
Eliminate unneeded intermediate registers
Optimize relocation table iteration

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

arm: make __rel_dyn_{start, end} compiler-generated

This change is only done where needed: some linker
scripts may contain relocation symbols yet remain
unchanged.

__rel_dyn_start and __rel_dyn_end each requires
its own output section; putting them in relocation
sections changes their flags and breaks relocation.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

arm: make __image_copy_{start, end} compiler-generated

This change is only done where needed: some linker
scripts may contain __image_copy_{start,end} yet
remain unchanged.

Also, __image_copy_end needs its own section; putting
it in relocation sections changes their flags and makes
relocation break.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

arm: generalize lib/bss.c into lib/sections.c

File arch/arm/lib/bss.c was initially defined for BSS only,
but is now going to also contain definitions for other
section-boundary-related symbols, so rename it for better
accuracy.

Also, remove useless 'used' attributes.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

remove all references to .dynsym

Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase

Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

arm: ensure u-boot only uses relative relocations

Add a Makefile target ('checkarmreloc') which
fails if the ELF binary contains relocation records
of types other than R_ARM_RELATIVE.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

powerpc/85xx: Add P1023RDB board support

P1023RDB Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (Fixed DDR on board)
   64MB NOR flash
   128MB NAND flash

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC2: Connected to Atheros AR8035 GETH PHY

PCIe:
   Three mini-PCIe slots

USB:
   Two USB2.0 Type A ports

I2C:
   AT24C08 8K Board EEPROM (8 bit address)

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs

init_tlbs() initialize all the TLB entries required for the system.

So disable DEBUG TLB entry before TLB entries initialization.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc/pixis: Fix pixis help message

"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc/CoreNet: Allow pbl images to take u-boot images != 512K

Instead of assuming that SYS_TEXT_BASE is 0xFFF80000 calculate the initial
pbl command offset by subtracting the image size from the top of the
24-bit address range. Also increase the size of the memory buffer to
accommodate a larger output image.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE

If a variable is used as array subscript, it's valid value range is
0 ... ARRAY_SIZE -1.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Makefile: move the common makefile line to public area

Move the common makefile line shared by the SPL and non-SPL to the public area,
so that we can avoid excessive SPL symbols. Some of them will be used by the
SPL later.

This patch is on top of the patch "common/Makefile: Add new symbol
CONFIG_SPL_ENV_SUPPORT for environment in SPL".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL

There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).

Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS

There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.

1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.

This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc/mpc85xx: support application without resetvec segment in the linker script

For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define

PCIe TLB should be created with CONFIG_PCI defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

board/b4860qds: Relax NOR flash teadc timing parameter

Relax parameters to give address latching more time to setup.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

powerpc/mpc85xx: work around erratum A-006593

Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".

The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1.  This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

fsl_ifc: add support for different IFC bank count

Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
   error on some devices that does not have IFC controller.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>