oweals/u-boot.git
11 years agospi: exynos: Support SPI_PREAMBLE mode
Rajeshwari Shinde [Tue, 28 May 2013 20:10:38 +0000 (20:10 +0000)]
spi: exynos: Support SPI_PREAMBLE mode

Support interfaces with a preamble before each received message.

We handle this when the client has requested a SPI_XFER_END, meaning
that we must close of the transaction. In this case we read until we
see the preamble (or a timeout occurs), skipping all data before and
including the preamble. The client will receive only data bytes after
the preamble.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agospi: Add support for preamble bytes
Rajeshwari Shinde [Tue, 28 May 2013 20:10:37 +0000 (20:10 +0000)]
spi: Add support for preamble bytes

A SPI slave may take time to react to a request. For SPI flash devices
this time is defined as one bit time, or a whole byte for 'fast read'
mode.

If the SPI slave is another CPU, then the time it takes to react may
vary. It is convenient to allow the slave device to tag the start of
the actual reply so that the host can determine when this 'preamble'
finishes and the actual message starts.

Add a preamble flag to the available SPI flags. If supported by the
driver then it will ignore any received bytes before the preamble
on each transaction. This ensures that reliable communication with
the slave is possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agosf: winbond: Add support for W25PXX SPI flash
Kuo-Jung Su [Thu, 23 May 2013 15:09:49 +0000 (15:09 +0000)]
sf: winbond: Add support for W25PXX SPI flash

Add support for Winbond's W25PXX SPI flash.
These devices is used on Faraday A369 evaluation board.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
CC: Tom Rini <trini@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agosf: winbond: Add support for W25Q256
Jagannadha Sutradharudu Teki [Sat, 23 Feb 2013 01:39:01 +0000 (01:39 +0000)]
sf: winbond: Add support for W25Q256

Add support for Winbond W25Q256 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agosf: spansion: Add Spansion S25FL064P IDs
Marek Vasut [Tue, 28 Aug 2012 15:13:37 +0000 (15:13 +0000)]
sf: spansion: Add Spansion S25FL064P IDs

This is a S25FL064A successor. It supports up to 104MHz bus
speed.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agopowerpc/esdhc: Correct judgement for DATA PIO mode
Haijun.Zhang [Tue, 7 May 2013 15:50:58 +0000 (15:50 +0000)]
powerpc/esdhc: Correct judgement for DATA PIO mode

The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:

Commit 7b43db92110ec2f15c5f7187a165f2928464966b
drivers/mmc/fsl_esdhc.c: fix compiler warnings

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Sun Yusong-R58495 <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agommc: update Faraday FTSDC010 for rw performance
Kuo-Jung Su [Mon, 6 May 2013 20:32:51 +0000 (20:32 +0000)]
mmc: update Faraday FTSDC010 for rw performance

Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.

It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Tom Rini [Tue, 14 May 2013 22:47:43 +0000 (18:47 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-mpc85xx

11 years agoPower: remove support for Freescale MPC8220
Wolfgang Denk [Sat, 11 May 2013 03:00:50 +0000 (03:00 +0000)]
Power: remove support for Freescale MPC8220

The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.

Remove the code to avoid wasting maitaining efforts on dead stuff.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
11 years agodoc/README.scrapyard: add missing commit IDs
Wolfgang Denk [Sat, 11 May 2013 03:00:49 +0000 (03:00 +0000)]
doc/README.scrapyard: add missing commit IDs

Signed-off-by: Wolfgang Denk <wd@denx.de>
11 years agodrivers/mmc: move spl_mmc.c to common/spl
Ying Zhang [Thu, 9 May 2013 23:00:36 +0000 (23:00 +0000)]
drivers/mmc: move spl_mmc.c to common/spl

The mpc85xx repuires a special layout on the memory device that is
connected to the eSDHC controller interface. But the file spl_mmc.c
didn't handle this specfic case, there needs a special treatmen, in
the powerpc drictory. So, there is no longer to keep spl_mmc.c on
mpc85xx, CONFIG_SPL_FRAMEWORK is not set.

When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not
set, there was an error in drivers/mmc/spl_mmc.c:

drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'.

Now, the solution is to move the file "spl_mmc.c" to directory "common/spl".

Signed-off-by: Ying Zhang <b40530@freescale.com>
11 years agosmc911x: fix the timeout detection
Masahiro Yamada [Wed, 8 May 2013 21:42:44 +0000 (21:42 +0000)]
smc911x: fix the timeout detection

If timeout is occurred at the while loop above,
the value of 'timeout' is -1, not 0.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
11 years agodoc/README.ubi: Add description of accessing ubi filesystems
Paul B. Henson [Wed, 8 May 2013 17:08:10 +0000 (17:08 +0000)]
doc/README.ubi: Add description of accessing ubi filesystems

Signed-off-by: "Paul B. Henson" <henson@acm.org>
11 years agoT4240/eth: fix SGMII card PHY address
Shaohui Xie [Mon, 25 Mar 2013 07:39:38 +0000 (07:39 +0000)]
T4240/eth: fix SGMII card PHY address

QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot, then
the slot must have a SGMII card pluged, we mark all ports on that slot,
and fix dts to use the SGMII card PHY address when doing dts fixup
for the marked ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: Fix disabling remote I2C connection
Ed Swarthout [Mon, 25 Mar 2013 07:39:37 +0000 (07:39 +0000)]
powerpc/t4qds: Fix disabling remote I2C connection

Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860qds: Assign DDR address in board file
York Sun [Mon, 25 Mar 2013 07:39:36 +0000 (07:39 +0000)]
powerpc/b4860qds: Assign DDR address in board file

B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Allow board file to override DDR address assignment
York Sun [Mon, 25 Mar 2013 07:39:35 +0000 (07:39 +0000)]
powerpc/mpc8xxx: Allow board file to override DDR address assignment

This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Update workaround for DDR erratum A-004934
York Sun [Mon, 25 Mar 2013 07:39:34 +0000 (07:39 +0000)]
powerpc/mpc85xx: Update workaround for DDR erratum A-004934

The workaround has been updated to use a slightly different magic number.
Change from 0x00003000 to 0x30003000.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c
Roy Zang [Mon, 25 Mar 2013 07:39:33 +0000 (07:39 +0000)]
T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c

This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without  “usb start” command.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4240/net: use QSGMII card PHY address by default
Shaohui Xie [Mon, 25 Mar 2013 07:39:32 +0000 (07:39 +0000)]
T4240/net: use QSGMII card PHY address by default

Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agonet/phy: add VSC8574 support
Shaohui Xie [Mon, 25 Mar 2013 07:39:31 +0000 (07:39 +0000)]
net/phy: add VSC8574 support

The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/85xx: fix build error introduced by serdes_get_prtcl
Shengzhou Liu [Mon, 25 Mar 2013 07:39:30 +0000 (07:39 +0000)]
powerpc/85xx: fix build error introduced by serdes_get_prtcl

Removed unused declare serdes_get_prtcl() which was no longer needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agonet/fm: fixup ethernet for mEMAC
Shengzhou Liu [Mon, 25 Mar 2013 07:39:29 +0000 (07:39 +0000)]
net/fm: fixup ethernet for mEMAC

- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
  MAC node disabled incorrectly.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agot4240qds/eth: fixup ethernet for t4240qds
Shengzhou Liu [Mon, 25 Mar 2013 07:39:28 +0000 (07:39 +0000)]
t4240qds/eth: fixup ethernet for t4240qds

1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
   slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/85xx: add missing QMAN frequency calculation
Shaohui Xie [Mon, 25 Mar 2013 07:33:25 +0000 (07:33 +0000)]
powerpc/85xx: add missing QMAN frequency calculation

When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc: Add T4160QDS
York Sun [Mon, 25 Mar 2013 07:33:31 +0000 (07:33 +0000)]
powerpc: Add T4160QDS

T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Move SoC define into boards.cfg
York Sun [Mon, 25 Mar 2013 07:33:30 +0000 (07:33 +0000)]
powerpc/t4240qds: Move SoC define into boards.cfg

Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC
variants supported on the same board.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Add T4160 SoC
York Sun [Mon, 25 Mar 2013 07:33:29 +0000 (07:33 +0000)]
powerpc/mpc85xx: Add T4160 SoC

T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240: Fix SerDes protocol arrays with const prefix
York Sun [Mon, 25 Mar 2013 07:33:28 +0000 (07:33 +0000)]
powerpc/t4240: Fix SerDes protocol arrays with const prefix

Protocols are constants. Fix arrays with const prefix.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Fix PIR parsing for chassis2
York Sun [Mon, 25 Mar 2013 07:33:27 +0000 (07:33 +0000)]
powerpc/mpc85xx: Fix PIR parsing for chassis2

The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/corenet2: Print SerDes protocol in decimal
York Sun [Mon, 25 Mar 2013 07:33:26 +0000 (07:33 +0000)]
powerpc/corenet2: Print SerDes protocol in decimal

Use decimal and hexadecimal for protocol numbers. It helps to match with
SoC user manual.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/USB: Add USB 2.0 UTMI dual phy support
Roy Zang [Mon, 25 Mar 2013 07:33:23 +0000 (07:33 +0000)]
T4/USB: Add USB 2.0 UTMI dual phy support

T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Add voltage ID support
York Sun [Mon, 25 Mar 2013 07:33:22 +0000 (07:33 +0000)]
powerpc/t4240qds: Add voltage ID support

T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Fix portal setup
York Sun [Mon, 25 Mar 2013 07:33:21 +0000 (07:33 +0000)]
powerpc/mpc85xx: Fix portal setup

Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Fix DDR 3-way interleaving
York Sun [Mon, 25 Mar 2013 07:33:20 +0000 (07:33 +0000)]
powerpc/mpc8xxx: Fix DDR 3-way interleaving

Should check if interleaving is enabled before using interleaving mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Update DDR timing table
York Sun [Mon, 25 Mar 2013 07:33:19 +0000 (07:33 +0000)]
powerpc/t4240qds: Update DDR timing table

Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/SerDes: correct the SATA index
Roy Zang [Mon, 25 Mar 2013 07:33:18 +0000 (07:33 +0000)]
T4/SerDes: correct the SATA index

Lane H on SerDes4 should be SATA2 instead of SATA1

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoFman/t4240: some fix for 10G XAUI
Shaohui Xie [Mon, 25 Mar 2013 07:33:17 +0000 (07:33 +0000)]
Fman/t4240: some fix for 10G XAUI

1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: fix XAUI card PHY address
Shaohui Xie [Mon, 25 Mar 2013 07:33:16 +0000 (07:33 +0000)]
powerpc/t4240qds: fix XAUI card PHY address

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/serdes: fix the serdes clock frequency
Roy Zang [Mon, 25 Mar 2013 07:33:15 +0000 (07:33 +0000)]
T4/serdes: fix the serdes clock frequency

Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0]  S3RATE[1:0]  S4RATE[1:0]

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoe6500: Move L1 enablement after L2 enablement
Andy Fleming [Mon, 25 Mar 2013 07:33:14 +0000 (07:33 +0000)]
e6500: Move L1 enablement after L2 enablement

The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.

Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Fix SPI flash type
Shaohui Xie [Mon, 25 Mar 2013 07:33:13 +0000 (07:33 +0000)]
powerpc/t4240qds: Fix SPI flash type

T4240QDS uses a SST instead of SPANSION SPI flash.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Update corenet global utility block registers
York Sun [Mon, 25 Mar 2013 07:33:12 +0000 (07:33 +0000)]
powerpc/mpc85xx: Update corenet global utility block registers

Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse
status register.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Add definitions for HDBCR registers
Andy Fleming [Mon, 25 Mar 2013 07:33:10 +0000 (07:33 +0000)]
powerpc/mpc85xx: Add definitions for HDBCR registers

Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1  to actually
use those definitions.

Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/B4860: Corrected FMAN1 operating frequency print at u-boot
Sandeep Singh [Mon, 25 Mar 2013 07:33:09 +0000 (07:33 +0000)]
powerpc/B4860: Corrected FMAN1 operating frequency print at u-boot

The bit positions for FMAN1 freq in RCW is different for B4860.
Also addded a case when FMAN1 frewuency is equal to systembus.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoOMAP5: Enable USB Ethernet support with LAN9730
Lubomir Popov [Mon, 1 Apr 2013 04:50:55 +0000 (04:50 +0000)]
OMAP5: Enable USB Ethernet support with LAN9730

Added the LAN9730 to list of supported devices. This chip is used
in the sEVM, uEVM and som5_evb. Tested on the som5_evb with dhcp
and ping.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
11 years agobuildman: Produce a sensible error message when branch is missing
Simon Glass [Wed, 8 May 2013 08:06:08 +0000 (08:06 +0000)]
buildman: Produce a sensible error message when branch is missing

Rather than a backtrace, produce a nice error message when an invalid
branch is provided to buildman.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agosparc: Use image_setup_linux() instead of local code
Simon Glass [Wed, 8 May 2013 08:06:06 +0000 (08:06 +0000)]
sparc: Use image_setup_linux() instead of local code

Sparc only really sets up the ramdisk, but we should still use
image_setup_linux() so that setup is common across all architectures
that use the FDT.

Cover-letter
Introduce a common image_setup_linux() function
This series continues the work to tidy up the image code. Each
architecture has its own code for setting up ready for booting linux.
An attempt is made here to unify these in a single image_setup_linux()
function.

The part of the image code that deals with FDT is split into image-fdt.c
and a few tweaks are added to make FIT images more viable in SPL.
END
Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agom68k: Use image_setup_linux() instead of local code
Simon Glass [Wed, 8 May 2013 08:06:05 +0000 (08:06 +0000)]
m68k: Use image_setup_linux() instead of local code

Rather than having similar code in m68k, use image_setup_linux() which
should be common across all architectures that use the FDT.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agopowerpc: Use image_setup_linux() instead of local code
Simon Glass [Wed, 8 May 2013 08:06:04 +0000 (08:06 +0000)]
powerpc: Use image_setup_linux() instead of local code

Rather than having similar code in powerpc, use image_setup_linux() which
should be common across all architectures that use the FDT.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoarm: Use image_setup_linux() instead of local code
Simon Glass [Wed, 8 May 2013 08:06:03 +0000 (08:06 +0000)]
arm: Use image_setup_linux() instead of local code

Use the common FDT setup function that is now available in image. Move
the FDT-specific code to a new bootm-fdt.c and remove unused headers
from bootm.c.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoarm: Refactor bootm to reduce #ifdefs
Simon Glass [Wed, 8 May 2013 08:06:02 +0000 (08:06 +0000)]
arm: Refactor bootm to reduce #ifdefs

With fewer #ifdefs the code is more readable and more of the code is
compiled for all boards. Add defines in the header file to control
what features are enabled, and then use if() instead of #ifdef.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoimage: Add device tree setup to image library
Simon Glass [Wed, 8 May 2013 08:06:01 +0000 (08:06 +0000)]
image: Add device tree setup to image library

This seems to be a common function for several architectures, so create
a common function rather than duplicating the code in each arch.

Also make an attempt to avoid introducing #ifdefs in the new code, partly
by removing useless #ifdefs around function declarations in the image.h
header.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoimage: Split libfdt code into image-fdt.c
Simon Glass [Wed, 8 May 2013 08:06:00 +0000 (08:06 +0000)]
image: Split libfdt code into image-fdt.c

The image file is still very large, and some of the code is only used when
libfdt is in use. Move this code into a new file.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoimage: Add CONFIG_FIT_SPL_PRINT to control FIT image printing in SPL
Simon Glass [Wed, 8 May 2013 08:05:59 +0000 (08:05 +0000)]
image: Add CONFIG_FIT_SPL_PRINT to control FIT image printing in SPL

This code is very large, and in SPL it isn't always useful to print
out image information (in fact there might not even be a console
active). So disable this feature unless this option is set.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoimage: Remove remaining #ifdefs in image-fit.c
Simon Glass [Wed, 8 May 2013 08:05:58 +0000 (08:05 +0000)]
image: Remove remaining #ifdefs in image-fit.c

There are only two left. One is unnecessary and the other can be moved
to the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agomkimage: Put FIT loading in function and tidy error handling
Simon Glass [Wed, 8 May 2013 08:05:57 +0000 (08:05 +0000)]
mkimage: Put FIT loading in function and tidy error handling

The fit_handle_file() function is quite long - split out the part that
loads and checks a FIT into its own function. We will use this
function for storing public keys into a destination FDT file.

The error handling is currently a bit repetitive - tidy it.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agosandbox: image: Add support for booting images in sandbox
Simon Glass [Tue, 7 May 2013 06:12:03 +0000 (06:12 +0000)]
sandbox: image: Add support for booting images in sandbox

Much of the image code uses addresses as ulongs and pointers interchangeably,
casting between the two forms as needed.

This doesn't work with sandbox, which has a U-Boot RAM buffer which is
separate from the host machine's memory.

Adjust the cost so that translating from a U-Boot address to a pointer uses
map_sysmem(). This allows bootm to work correctly on sandbox.

Note that there are no exhaustive tests for this code on sandbox, so it is
possible that some dark corners remain.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de> (v1)
11 years agoimage: Rename hash printing to fit_image_print_verification_data()
Simon Glass [Tue, 7 May 2013 06:12:02 +0000 (06:12 +0000)]
image: Rename hash printing to fit_image_print_verification_data()

This function will be used to print signatures as well as hashes, so rename
it. Also make it static since it is not used outside this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Rename fit_add_hashes() to fit_add_verification_data()
Simon Glass [Tue, 7 May 2013 06:12:01 +0000 (06:12 +0000)]
image: Rename fit_add_hashes() to fit_add_verification_data()

We intend to add signatures to FITs also, so rename this function so that
it is not specific to hashing. Also rename fit_image_set_hashes() and
make it static since it is not used outside this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Export fit_conf_get_prop_node()
Simon Glass [Tue, 7 May 2013 06:12:00 +0000 (06:12 +0000)]
image: Export fit_conf_get_prop_node()

This function will be needed by signature checking code, so export it,
and also add docs.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoimage: Move error! string to common place
Simon Glass [Tue, 7 May 2013 06:11:59 +0000 (06:11 +0000)]
image: Move error! string to common place

The string " error\n" appears in each error string. Move it out to a
common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Move hash checking into its own function
Simon Glass [Tue, 7 May 2013 06:11:58 +0000 (06:11 +0000)]
image: Move hash checking into its own function

The existing function is long and most of the code is indented a long
way. Before adding yet more code, split this out into its own function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de> (v1)
11 years agoimage: Rename fit_image_check_hashes() to fit_image_verify()
Simon Glass [Tue, 7 May 2013 06:11:57 +0000 (06:11 +0000)]
image: Rename fit_image_check_hashes() to fit_image_verify()

This is the main entry point to the FIT image verification code. We will
be using it to handle image verification with signatures, so rename the
function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Convert fit_image_hash_set_value() to static, and rename
Simon Glass [Tue, 7 May 2013 06:11:56 +0000 (06:11 +0000)]
image: Convert fit_image_hash_set_value() to static, and rename

This function doesn't need to be exported, and with verification
we want to use it for setting the 'value' property in any node,
so rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Split hash node processing into its own function
Simon Glass [Tue, 7 May 2013 06:11:55 +0000 (06:11 +0000)]
image: Split hash node processing into its own function

This function has become quite long and much of the body is indented quite
a bit. Move it into a separate function to make it easier to work with.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
11 years agoimage: Move HOSTCC image code to tools/
Simon Glass [Tue, 7 May 2013 06:11:54 +0000 (06:11 +0000)]
image: Move HOSTCC image code to tools/

This code is never compiled into U-Boot, so move it into a separate
file in tools/ to avoid the large #ifdef.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Split FIT code into new image-fit.c
Simon Glass [Tue, 7 May 2013 06:11:53 +0000 (06:11 +0000)]
image: Split FIT code into new image-fit.c

The FIT code is about half the size of the >3000-line image.c. Split this
code into its own file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Export fit_check_ramdisk()
Simon Glass [Tue, 7 May 2013 06:11:52 +0000 (06:11 +0000)]
image: Export fit_check_ramdisk()

One we split out the FIT code from image.c we will need this function.
Export it in the header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
11 years agoimage: Move timestamp #ifdefs to header file
Simon Glass [Tue, 7 May 2013 06:11:51 +0000 (06:11 +0000)]
image: Move timestamp #ifdefs to header file

Rather than repeat the line
 #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
defined(USE_HOSTCC)

everywhere, put this in a header file and #define IMAGE_ENABLE_TIMESTAMP
to either 1 or 0. Then we can use a plain if() in most code and avoid
the #ifdefs.

The compiler's dead code elimination ensures that the result is the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
11 years agolibfdt: Add fdt_next_subnode() to permit easy subnode iteration
Simon Glass [Tue, 7 May 2013 06:11:50 +0000 (06:11 +0000)]
libfdt: Add fdt_next_subnode() to permit easy subnode iteration

Iterating through subnodes with libfdt is a little painful to write as we
need something like this:

for (depth = 0, count = 0,
offset = fdt_next_node(fdt, parent_offset, &depth);
     (offset >= 0) && (depth > 0);
     offset = fdt_next_node(fdt, offset, &depth)) {
if (depth == 1) {
/* code body */
}
}

Using fdt_next_subnode() we can instead write this, which is shorter and
easier to get right:

for (offset = fdt_first_subnode(fdt, parent_offset);
     offset >= 0;
     offset = fdt_next_subnode(fdt, offset)) {
/* code body */
}

Also, it doesn't require two levels of indentation for the loop body.

Signed-off-by: Simon Glass <sjg@chromium.org>
(Cherry-picked from dtc commit 4e76ec79)
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
11 years agomkimage: Move ARRAY_SIZE to header file
Simon Glass [Tue, 7 May 2013 06:11:49 +0000 (06:11 +0000)]
mkimage: Move ARRAY_SIZE to header file

Move this definition from aisimage.c to mkimage.h so that it is available
more widely.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
11 years agobootstage: Don't build for HOSTCC
Simon Glass [Tue, 7 May 2013 06:11:48 +0000 (06:11 +0000)]
bootstage: Don't build for HOSTCC

We don't measure boot timing on the host, or with SPL, so use both
conditions in the bootstage header. This allows us to avoid using
conditional compilation around bootstage_...() calls. (#ifdef)

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agohash: Add a way to calculate a hash for any algortihm
Simon Glass [Tue, 7 May 2013 06:11:47 +0000 (06:11 +0000)]
hash: Add a way to calculate a hash for any algortihm

Rather than needing to call one of many hashing algorithms in U-Boot,
provide a function hash_block() which handles this, and can support all
available hash algorithms.

Once we have md5 supported within hashing, we can use this function in
the FIT image code.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoAdd minor updates to README.fdt-control
Simon Glass [Tue, 7 May 2013 06:11:46 +0000 (06:11 +0000)]
Add minor updates to README.fdt-control

A few things have changed since this doc was written, so update it to
match the current state of things.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoenv: Fix minor comment typos in cmd_nvedit
Simon Glass [Tue, 7 May 2013 06:11:45 +0000 (06:11 +0000)]
env: Fix minor comment typos in cmd_nvedit

This should say 'environmnent'.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoMerge branch 'master' of git://git.denx.de/u-boot-blackfin into powerpc-eldk53-warnin...
Tom Rini [Tue, 14 May 2013 15:45:41 +0000 (11:45 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-blackfin into powerpc-eldk53-warning-fixes

11 years agoMerge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Mon, 13 May 2013 22:17:39 +0000 (18:17 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-x86

11 years agox86: Add coreboot timestamps
Simon Glass [Wed, 17 Apr 2013 16:13:48 +0000 (16:13 +0000)]
x86: Add coreboot timestamps

Add selected coreboot timestamps into bootstage to get a unified view of
the boot timings.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agox86: Support adding coreboot timestanps to bootstage
Simon Glass [Wed, 17 Apr 2013 16:13:47 +0000 (16:13 +0000)]
x86: Support adding coreboot timestanps to bootstage

Coreboot provides a lot of useful timing information. Provide a facility
to add this to bootstage on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agox86: config: Enable LZO for coreboot, remove zlib, gzip
Simon Glass [Wed, 17 Apr 2013 16:13:46 +0000 (16:13 +0000)]
x86: config: Enable LZO for coreboot, remove zlib, gzip

We don't use zlib and gzip but do use lzo, so enable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agox86: Fix warning in cmd_ximg.c when CONFIG_GZIP is not defined
Simon Glass [Wed, 17 Apr 2013 16:13:45 +0000 (16:13 +0000)]
x86: Fix warning in cmd_ximg.c when CONFIG_GZIP is not defined

This local variable is not used unless CONFIG_GZIP is defined. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agobootstage: Allow marking a particular line of code
Simon Glass [Wed, 17 Apr 2013 16:13:44 +0000 (16:13 +0000)]
bootstage: Allow marking a particular line of code

Add a function which allows a (file, function, line number) to be marked
in bootstage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
11 years agox86: Enable bootstage for coreboot
Simon Glass [Wed, 17 Apr 2013 16:13:43 +0000 (16:13 +0000)]
x86: Enable bootstage for coreboot

This is a convenient way of finding out where boottime is going. Enable
it for coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoCall bootstage_relocate() after malloc is initted
Doug Anderson [Wed, 17 Apr 2013 16:13:42 +0000 (16:13 +0000)]
Call bootstage_relocate() after malloc is initted

In a previous CL we added the bootstage_relocate(), which should be
called after malloc is initted.  Now we call it on generic board.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
11 years agobootstage: Copy bootstage strings post-relocation
Doug Anderson [Wed, 17 Apr 2013 16:13:41 +0000 (16:13 +0000)]
bootstage: Copy bootstage strings post-relocation

Any pointers to name strings that were passed to bootstage_mark_name()
pre-relocation should be copied post-relocation so that they don't get
trashed as the original location of U-Boot is re-used for other
purposes.

This change introduces a new API call that should be called from
board_init_r() after malloc has been initted on any board that uses
bootstage.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
11 years agobootstage: Add stubs for new bootstage functions
Simon Glass [Wed, 17 Apr 2013 16:13:40 +0000 (16:13 +0000)]
bootstage: Add stubs for new bootstage functions

Some functions don't have a stub for when CONFIG_BOOTSTAGE is not defined.
Add one to avoid #ifdefs in the code when this is used in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
11 years agox86: Re-enable PCAT timer 2 for beeping
Simon Glass [Wed, 17 Apr 2013 16:13:39 +0000 (16:13 +0000)]
x86: Re-enable PCAT timer 2 for beeping

While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agox86: Remove ISR timer
Simon Glass [Wed, 17 Apr 2013 16:13:38 +0000 (16:13 +0000)]
x86: Remove ISR timer

This is no longer used since we prefer the more accurate TSC timer, so
remove the dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
11 years agox86: Remove old broken timer implementation
Simon Glass [Wed, 17 Apr 2013 16:13:37 +0000 (16:13 +0000)]
x86: Remove old broken timer implementation

Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
11 years agox86: Add TSC timer
Simon Glass [Wed, 17 Apr 2013 16:13:36 +0000 (16:13 +0000)]
x86: Add TSC timer

This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agox86: Rationalise kernel booting logic and bootstage
Simon Glass [Wed, 17 Apr 2013 16:13:35 +0000 (16:13 +0000)]
x86: Rationalise kernel booting logic and bootstage

The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
11 years agox86: Implement panic output for coreboot
Simon Glass [Wed, 17 Apr 2013 16:13:34 +0000 (16:13 +0000)]
x86: Implement panic output for coreboot

panic_puts() can be called in early boot to display a message. It might
help with early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
11 years agox86: Declare global_data pointer when it is used
Simon Glass [Wed, 17 Apr 2013 16:13:33 +0000 (16:13 +0000)]
x86: Declare global_data pointer when it is used

Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agox86: Remove legacy board init code
Simon Glass [Wed, 17 Apr 2013 16:13:32 +0000 (16:13 +0000)]
x86: Remove legacy board init code

Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
11 years agox86: Remove unused portion of link script
Simon Glass [Wed, 17 Apr 2013 16:13:31 +0000 (16:13 +0000)]
x86: Remove unused portion of link script

Since we don't have real-mode code now, we can remove this chunk of the link
script.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
11 years agox86: Remove unused bios/pci code
Simon Glass [Wed, 17 Apr 2013 16:13:30 +0000 (16:13 +0000)]
x86: Remove unused bios/pci code

Graeme Russ pointed out that this code is no longer used. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
11 years agoavr32: fix relocation address calculation
Andreas Bießmann [Tue, 7 May 2013 23:25:17 +0000 (23:25 +0000)]
avr32: fix relocation address calculation

Commit 1865286466a5d0c7f2e3c37632da56556c838e9e (Introduce generic link
section.h symbol files) changed the __bss_end symbol type from char[] to
ulong. This led to wrong relocation parameters which ended up in a not working
u-boot. Unfortunately this is not clear to see cause due to RAM aliasing we
may get a 'half-working' u-boot then.

Fix this by dereferencing the __bss_end symbol where needed.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agobfin: Move gpio support for bf54x and bf60x into the generic driver folder.
Sonic Zhang [Thu, 2 May 2013 05:46:21 +0000 (13:46 +0800)]
bfin: Move gpio support for bf54x and bf60x into the generic driver folder.

The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx.
A lot of machine macros are used to accomodate both code in one gpio driver.
This patch split the old gpio driver and move new gpio2 support to the generic
gpio driver folder.

- To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's
config header file.
- The gpio2 driver supports bf54x, bf60x and future ADI processors, while the
older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561.
- All blackfin specific gpio function names are replaced by the generic gpio APIs.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
11 years agoblackfin: The buf variable in bfin_mac.c is not used and produces warning,
Marek Vasut [Fri, 19 Apr 2013 04:17:42 +0000 (12:17 +0800)]
blackfin: The buf variable in bfin_mac.c is not used and produces warning,

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>