Simon Glass [Sat, 15 Apr 2017 19:11:31 +0000 (13:11 -0600)]
rockchip: Print a message when returning to the bootrom
At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 14:37:54 +0000 (16:37 +0200)]
drivers/crypto/fsl: remove redundant logical contraint
'A || (!A && B)' is equivalent to 'A || B'.
Let's reduce the complexity of the statement in start_jr0().
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:31:53 +0000 (15:31 +0200)]
fsl/sata: correctly identify failed malloc
After allocating sata->cmd_hdr_tbl_offset we have to check
this variable and not variable sata.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:23:49 +0000 (15:23 +0200)]
ddr: fsl: incorrect logical constraint in populate_memctl_options
(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40)
is always true.
We should use && here.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:15:40 +0000 (15:15 +0200)]
FPGA: drivers/fpga/ivm_core.c: incorrect printf
The number of arguments for printf does not match the
format string.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:05:46 +0000 (15:05 +0200)]
usbtty: avoid potential NULL pointer dereference
If current_urb is NULL it should not be dereferenced.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 11:28:13 +0000 (13:28 +0200)]
yaffs2: remove redundant condition
If !parent, the changed line is not reached.
So there is no need to check the value again.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 11:05:40 +0000 (13:05 +0200)]
tools/env: avoid memory leak in fw_setenv
If realloc fails we should release the old buffer.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 10:29:20 +0000 (12:29 +0200)]
arm: omap-common: add missing va_end()
Each call of va_start must be matched by a call of va_end.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 14 Apr 2017 23:47:51 +0000 (19:47 -0400)]
travis-ci: Switch over to Linaro gcc-6.3.1 toolchains for ARM
Linaro provides a number of pre-built GCC toolchains for both 32 and
64bit ARM. Switch to their 2017.02 release of gcc-6.3.1 for both.
Cc: Koen Kooi <koen.kooi@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 14 Apr 2017 23:47:50 +0000 (19:47 -0400)]
buildman: Allow 'gnueabihf' toolchains for ARM
Many toolchains for ARM use the 'gnueabihf' suffix rather than just
'gnueabi', so allow these to be used, but with a lower priority than
'gnueabi' ones.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 14 Apr 2017 02:10:24 +0000 (11:10 +0900)]
sysreset: psci: support system reset in a generic way with PSCI
If the system is running PSCI firmware, the System Reset function
(func ID: 0x80000009) is supposed to be handled by PSCI, that is,
the SoC/board specific reset implementation should be moved to PSCI.
U-Boot should call the PSCI service according to the arm-smccc
manner.
The arm-smccc is supported on ARMv7 or later. Especially, ARMv8
generation SoCs are likely to run ARM Trusted Firmware BL31. In
this case, U-Boot is a non-secure world boot loader, so it should
not be able to reset the system directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 02:10:23 +0000 (11:10 +0900)]
ARM: adjust arm-smccc code for use in U-Boot
Adjust ARM SMC Calling Convention code for U-Boot:
- Replace the license block with SPDX
- Change path to asm-offsets.h
- Define UNWIND() as no-op
- Add Kconfig entry
- Add asm-offsets
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 02:10:22 +0000 (11:10 +0900)]
ARM: import arm-smccc code from Linux 4.11-rc6
Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:
[Linux] [U-Boot]
arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h -> include/linux/arm-smccc.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 02:05:48 +0000 (11:05 +0900)]
blackfin: ibf-dsp561: remove orphan Blackfin board
This is a Blackfin board that commit
ea3310e8aafa ("Blackfin:
Remove") missed to remove.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 01:55:00 +0000 (10:55 +0900)]
drivers: remove Blackfin specific drivers
These drivers have no user since commit
ea3310e8aafa ("Blackfin:
Remove").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Masahiro Yamada [Fri, 14 Apr 2017 01:54:59 +0000 (10:54 +0900)]
cmd: remove Blackfin specific commands
These commands have no user since commit
ea3310e8aafa ("Blackfin:
Remove").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 14 Apr 2017 01:53:56 +0000 (10:53 +0900)]
tools: moveconfig: remove GCC prefix of obsolete architecture
Recently, U-Boot removed support for these architectures.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tyler Hall [Wed, 12 Apr 2017 20:29:17 +0000 (16:29 -0400)]
cramfs: basic symlink support
Handle symlinks to files in the current directory. Other cases could be
handled with additional code, but this is a start.
Add explicit errors for absolute paths and links found in the middle of
a path (directories). Other cases like '..' or '.' will result with the
file not being found as when those path components are explicitly
provided.
Add a helper to decompress a null-terminated link name which is shared
with cramfs_list_inode.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Tyler Hall [Wed, 12 Apr 2017 20:29:16 +0000 (16:29 -0400)]
cramfs: block pointers are 32 bits
Using a variably-sized type is incorrect here since we're reading a
fixed file format. Fixes cramfs on 64-bit platforms.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Tyler Hall [Wed, 12 Apr 2017 20:29:15 +0000 (16:29 -0400)]
cmd: cramfs: use map_sysmem for sandbox support
As with most other commands, this needs to factor in the sysmem offset
in the sandbox or it will try to dereference the simulated physical
address directly.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Tom Rini [Mon, 17 Apr 2017 22:16:49 +0000 (18:16 -0400)]
Prepare v2017.05-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 17 Apr 2017 02:08:13 +0000 (22:08 -0400)]
Merge git://git.denx.de/u-boot-rockchip
Tom Rini [Mon, 17 Apr 2017 02:07:52 +0000 (22:07 -0400)]
Merge git://git.denx.de/u-boot-dm
Philipp Tomsich [Sat, 1 Apr 2017 10:59:25 +0000 (12:59 +0200)]
rockchip: rk3399: spl: add UART0 support for SPL
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.
As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.
As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 10 Apr 2017 02:41:46 +0000 (10:41 +0800)]
rockchip: pmic: Enable RK808 for rk3399 evb
For using mipi display, we need to enable lcd3v3
which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 10 Apr 2017 02:17:03 +0000 (10:17 +0800)]
rockchip: i2c: Enable i2c for rk3399
To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 10 Apr 2017 01:53:31 +0000 (09:53 +0800)]
rockchip: rk3399: Add missing sentinel in syscon
when enable PMIC rk808,the system will halt at very
early stage,log is shown as bellow.
INFO: plat_rockchip_pmu_init(1211): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
time 44561b, 0 (<<----Just stop here)
It's caused by the absence of "{ }" in syscon_rk3399.c
,which will lead to memory overflow like below.According
to Sysmap file ,we can find the function buck_get_value
of rk808 is just follow the compatible struct,the pointer
"of_match" point to "buck_get_value",but it is not a
struct and don't have member of compatible, In this case,
system crash. So,on the face, it looks like that rk808 is
guilty.but he is really innocent.
while (of_match->compatible) { <<----------
if (!strcmp(of_match->compatible, compat)) {
*of_idp = of_match;
return 0;
}
of_match++;
}
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Klaus Goger [Fri, 7 Apr 2017 17:13:38 +0000 (19:13 +0200)]
rockchip: ARM64: split RK3399-Q7 board off the RK3399-EVB board
The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.
It provides the following feature set:
* up to 4GB DDR3
* on-module SPI-NOR flash
* on-module eMMC (with 8-bit interace)
* SD card (on a baseboad) via edge connector
* Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
* HDMI/eDP/MIPI displays
* 2x MIPI-CSI
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
* on-module STM32 Cortex-M0 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
- USB<->CAN bridge controller
Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 7 Apr 2017 17:09:37 +0000 (19:09 +0200)]
rockchip: dts: rk3399-puma: make the DTS dual-licensed
The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed.
This updates the licensing info in the rk3399-puma.dts.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Fri, 7 Apr 2017 10:38:52 +0000 (12:38 +0200)]
rockchip: sysreset: rk3188: Make sure remap is off on warm-resets
The warm-reset of rk3188 socs keeps the remap setting as it was, so if
it was enabled, the cpu would start from address 0x0 of the sram instead
of address 0x0 of the bootrom, thus making the reset hang.
Therefore make sure the remap is disabled before attempting a warm reset.
Cold reset is not affected by this at all.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 7 Apr 2017 10:12:55 +0000 (18:12 +0800)]
rockchip: rk3399: do not use lower address
The lower address is reserved for ATF, do not use it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Wed, 5 Apr 2017 22:19:36 +0000 (00:19 +0200)]
rockchip: rk3188: enable remap function
Most Rockchip socs have the ability to either map the bootrom or a sram
area to the starting address of the cpu by flipping a bit in the GRF.
Newer socs leave this untouched and mapped to the bootrom but the legacy
loaders on rk3188 and before enabled the remap functionality and the
current smp implementation in the Linux kernel also requires it to be
enabled, to bring up secondary cpus.
So to keep smp working in the kernel, mimic the behaviour of the legacy
bootloaders and enable the remap functionality.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Wed, 5 Apr 2017 22:19:18 +0000 (00:19 +0200)]
rockchip: cosmetic: Move rock board to its correct position
Somehow
43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") moved
the rock board in between some rk3288 board, probably as a result of
rebasing.
So move it back to its original position above all rk3288 boards.
Fixes:
43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Sat, 1 Apr 2017 06:49:54 +0000 (14:49 +0800)]
rockchip: Add USB to the default boot targets
Now that most rockchip SoC based board have usb host support, enable
USB boot targets by default.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build errors when CONFIG_CMD_USB not defined:
Signed-off-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Sat, 1 Apr 2017 06:46:52 +0000 (14:46 +0800)]
rockchip: tinker: configs: Add USB, PXE, DHCP to the default boot targets
tinker board support ethernet and usb host, so enable USB, PXE and DHCP support.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 29 Mar 2017 19:20:29 +0000 (21:20 +0200)]
rockchip: dts: rk3399-puma: disable 'fifo-mode' in sdmmc
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 29 Mar 2017 19:20:28 +0000 (21:20 +0200)]
rockchip: spl: rk3399: disable DDR security regions for SPL
The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).
System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.
With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Fri, 14 Apr 2017 00:51:47 +0000 (08:51 +0800)]
board: sama5d3_xplained: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 14 Apr 2017 00:51:46 +0000 (08:51 +0800)]
board: sama5d3_xplained: Clean up code
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 14 Apr 2017 00:51:45 +0000 (08:51 +0800)]
board: sama5d3_xplained: Update to support DM/DT
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Fix build error with sama5d3_xplained_mmc:
Signed-off-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Fri, 14 Apr 2017 00:51:44 +0000 (08:51 +0800)]
board: sama5d3xek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 14 Apr 2017 00:51:43 +0000 (08:51 +0800)]
board: sama5d3xek: Clean up code
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Remove CONFIG_PHY_MICREL as per previous patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Fri, 14 Apr 2017 00:51:42 +0000 (08:51 +0800)]
board: sama5d3xek: Update to support DM/DT
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add back CONFIG_PHY_MICREL to prevent a build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 15 Apr 2017 02:05:17 +0000 (22:05 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video
Simon Glass [Mon, 10 Apr 2017 17:34:59 +0000 (11:34 -0600)]
dm: led: Add a new 'led' command
When driver model is used for LEDs, provide a command to allow LED access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:58 +0000 (11:34 -0600)]
led: Mark existing driver as legacy
The existing 'led' command does not support driver model. Rename it to
indicate that it is legacy code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:57 +0000 (11:34 -0600)]
dm: led: Add support for blinking LEDs
Allow LEDs to be blinked if the driver supports it. Enable this for
sandbox so that the tests run.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:56 +0000 (11:34 -0600)]
dm: led: Support toggling LEDs
Add support for toggling an LED into the uclass interface. This can be
efficiently implemented by the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:55 +0000 (11:34 -0600)]
dm: led: Add support for getting the state of an LED
It is useful to be able to read the LED as well as write it. Add this to
the uclass and update the GPIO driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:54 +0000 (11:34 -0600)]
dm: led: Adjust the LED uclass
At present this is very simple, supporting only on and off. We want to
also support toggling and blinking. As a first step, change the name of
the main method and use an enum to indicate the state.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:53 +0000 (11:34 -0600)]
dm: led: Rename struct led_uclass_plat
These structures are normally named with 'uc' instead of 'uclass'. Change
this one for consistency.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:52 +0000 (11:34 -0600)]
dm: led: Add a missing blank line in the Kconfig file
There should be a blank line between each option. Add one before LED_GPIO.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:51 +0000 (11:34 -0600)]
sandbox: Add some test LEDs
Add some LEDs to the standard sandbox device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:08 +0000 (13:42 +0200)]
dm: scsi: fix divide-by-0 error in scsi_scan()
With DM_SCSI enabled, blk_create_devicef() is called with blkz = 0, leading
to a divide-by-0 exception.
scsi_detect_dev() can be used to get the required parameters (block size
and number of blocks) from the drive before calling blk_create_devicef().
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:07 +0000 (13:42 +0200)]
scsi: move the partition initialization out of the scsi detection
We might want to get information about the scsi device without initializing the partition.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:06 +0000 (13:42 +0200)]
scsi: make the LUN a parameter of scsi_detect_dev()
This is a cosmetic change. target and LUN have kind of the same role in
this function. One of them was passed as a parameter and the other was
embedded in a structure. For consistency, pass both of them as parameters.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:01 +0000 (13:42 +0200)]
arm: omap: sata: compile out board-level sata code when CONFIG_DM_SCSI is defined
When CONFIG_DM_SCSI is defined, the SATA initialization will be implemented
in the scsi-uclass driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Fri, 7 Apr 2017 11:42:00 +0000 (13:42 +0200)]
arm: omap: sata: move enable sata clocks to enable_basic_clocks()
All the clocks which has to be enabled has to be done in
enable_basic_clocks(), so moving enable sata clock to common
clocks enable function.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 14 Apr 2017 14:06:28 +0000 (10:06 -0400)]
buildman: Translate more strings to latin-1
When writing out some of our results we may now have UTF-8 characters
in there as well. Translate these to latin-1 and ignore any errors (as
this is for diagnostic and given the githash anything else can be
reconstructed by the user.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 14 Apr 2017 14:58:49 +0000 (10:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
Troy Kisky [Tue, 11 Apr 2017 01:23:11 +0000 (18:23 -0700)]
usb: return 0 from usb_stor_get_info even if removable media
This fixes a regression caused by
commit
07b2b78ce4bc8ae25e066c65245eaf58c0d9a67c
dm: usb: Convert USB storage to use driver-model for block devs
which caused part_init to be called when it was not previously.
Without this patch, the following happens when a USB sd card reader is used.
=> usb start
starting USB...
USB0: Port not available.
USB1: USB EHCI 1.00
scanning bus 1 for devices... 3 USB Device(s) found
scanning usb for storage devices... Device NOT ready
Request Sense returned 02 3A 00
### ERROR ### Please RESET the board ###
This happens because dev_desc->blksz is 0.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Eddie Cai [Thu, 6 Apr 2017 03:37:04 +0000 (11:37 +0800)]
usb: dwc2: invalidate the dcache before starting the DMA
We should invalidate the dcache before starting the DMA. In case there are
any dirty lines from the DMA buffer in the cache, subsequent cache-line
replacements may corrupt the buffer in memory while the DMA is still going on.
Cache-line replacement can happen if the CPU tries to bring some other memory
locations into the cache while the DMA is going on.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Philipp Tomsich [Thu, 6 Apr 2017 14:58:53 +0000 (16:58 +0200)]
usb: dwc3: gadget: make cache-maintenance on event buffers more robust
Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).
The original code was doing the following (on AArch64, which
translates a 'flush' into a 'clean + invalidate'):
# during initialisation:
1. allocate buffers via memalign
=> buffers may still be modified (cached, dirty)
# during interrupt processing
2. clean + invalidate buffers
=> may commit stale data from a modified cacheline
3. read from buffers
This could lead to garbage info being written to buffers before
reading them during even-processing.
To make the event processing more robust, we use the following sequence
for the cache-maintenance:
# during initialisation:
1. allocate buffers via memalign
2. clean + invalidate buffers
(we only need the 'invalidate' part, but dwc3_flush_cache()
always performs a 'clean + invalidate')
# during interrupt processing
3. read the buffers
(we know these lines are not cached, due to the previous
invalidation and no other code touching them in-between)
4. clean + invalidate buffers
=> writes back any modification we may have made during event
processing and ensures that the lines are not in the cache
the next time we enter interrupt processing
Note that with the original sequence, we observe reproducible
(depending on the cache state: i.e. running dhcp/usb start before will
upset caches to get us around this) issues in the event processing (a
fatal synchronous abort in dwc3_gadget_uboot_handle_interrupt on the
first time interrupt handling is invoked) when running USB mass
storage emulation on our RK3399-Q7 with data-caches on.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Thu, 6 Apr 2017 14:58:52 +0000 (16:58 +0200)]
usb: dwc3: ensure consistent types for dwc3_flush_cache
The dwc3_flush_cache() call was declared and used inconsistently:
* The declaration assumed 'int' for addresses (a potential issue
when running in a LP64 memory model).
* The invocation cast the address to 'long'.
This change ensures that both the declaration and usage of this
function consistently uses 'uintptr_t' for correct behaviour even
when the allocated buffers (to be flushed) reside outside of the
lower 32bits of memory.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Felipe Balbi [Wed, 22 Feb 2017 15:12:41 +0000 (17:12 +0200)]
usb: gadget: g_dnl: don't set iProduct nor iSerialNumber
Both these numbers are calculated in runtime and dynamically assigned
to the device descriptor during bind().
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Felipe Balbi [Wed, 22 Feb 2017 15:12:40 +0000 (17:12 +0200)]
usb: gadget: g_dnl: only set iSerialNumber if we have a serial#
We don't want to claim that we support a serial number string and
later return nothing. Because of that, if g_dnl_serial is an empty
string, let's skip setting iSerialNumber to a valid number.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Felipe Balbi [Wed, 22 Feb 2017 15:12:39 +0000 (17:12 +0200)]
usb: gadget: g_dnl: hold maximum string descriptor
A USB String descriptor can be up to 255 characters long and it's not
NULL terminated according to the USB spec. This means our
MAX_STRING_SERIAL should be 256 (to cope with NULL terminator).
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
eric.gao@rock-chips.com [Mon, 10 Apr 2017 02:02:20 +0000 (10:02 +0800)]
video: Fix crash when scroll screen
After enabling log printing to lcd, when the screen starts
scrolling, system crashes. Log is shown as bellow:
"Synchronous Abort" handler, esr 0x96000045
"Synchronous Abort" handler, esr 0x96000045
Checking the source code, we found that the variable "pixels"
gets a wrong value:
int pixels = VIDEO_FONT_HEIGHT * vid_priv->line_length;
"pixels" here means the value of pixels for a character, rather
than the bytes for a character. So the variable "pixels" is 4
times bigger than it's exact value, which will cause the memory
overflow when the cpu runs the following code:
for (i = 0; i < pixels; i++)
*dst++ = clr; <<----
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Songjun Wu [Tue, 11 Apr 2017 08:33:31 +0000 (16:33 +0800)]
at91: video: DT binding for HLCDC driver
DT binding documentation for atmel HLCDC driver.
Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
Tom Rini [Fri, 14 Apr 2017 13:05:57 +0000 (09:05 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Fri, 14 Apr 2017 13:05:46 +0000 (09:05 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mmc
Songjun Wu [Tue, 11 Apr 2017 08:33:30 +0000 (16:33 +0800)]
at91: video: Support driver-model for the HLCD driver
Add driver-model support to this driver.
Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
Kever Yang [Fri, 10 Mar 2017 04:05:14 +0000 (12:05 +0800)]
usb: dwc2: add support for external vbus supply
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Dalon Westergreen [Thu, 13 Apr 2017 14:30:36 +0000 (07:30 -0700)]
arm: socfpga: sr1500 use environment in common header
This removes the default environment from the sr1500 header
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
This board has no upstream devicetree in the kernel source,
so set to socfpga_cyclone5_sr1500.dtb.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
- set devicetree name to match socfpga_{fpga model}_{board model}.dts
pattern
Dalon Westergreen [Thu, 13 Apr 2017 14:30:35 +0000 (07:30 -0700)]
arm: socfpga: Socrates use environment in common header
This removes the default environment from the socrates headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
Dalon Westergreen [Thu, 13 Apr 2017 14:30:34 +0000 (07:30 -0700)]
arm: socfpga: SoCKit use environment in common header
This removes the default environment from the SoCKit headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
Dalon Westergreen [Thu, 13 Apr 2017 14:30:33 +0000 (07:30 -0700)]
arm: socfpga: DE1 use environment in common header
This removes the default environment from the de1 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
This board does not have a devicetree in the upstream kernel
source so set devicetree to socfpga_cyclone5_de1_soc.dtb.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in V2:
- Remove unneeded CONFIG_BOOTFILE
- set devicetree name to match socfpga_{fpga model}_{board model}.dts
pattern
Dalon Westergreen [Thu, 13 Apr 2017 14:30:32 +0000 (07:30 -0700)]
arm: socfpga: C5 SoCDK use environment in common header
This removes the default environment from the C5 SoCDK headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
In addition to the above, add support to boot from the custom
a2 type partition.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
Dalon Westergreen [Thu, 13 Apr 2017 14:30:31 +0000 (07:30 -0700)]
arm: socfpga: A5 SoCDK use environment in common header
This removes the default environment from the A5 socdk headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
Add support to boot from the custom a2 type partition.
Change default devicetree name to match devicetree name in
upstream kernel source.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v3:
- Fix small typo in defconfig, missing "C"
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
- Fix dtb name
a5config test
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Dalon Westergreen [Thu, 13 Apr 2017 14:30:30 +0000 (07:30 -0700)]
arm: socfpga: DE0 use environment in common header
This removes the default environment from the de0 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.
In addition to the above, add support to boot from the custom
a2 type partition
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE
Dalon Westergreen [Thu, 13 Apr 2017 14:30:29 +0000 (07:30 -0700)]
arm: socfpga: Add distro boot to socfpga common header
This adds a common environment and support for distro boot
in the common socfpga header.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
--
Changes in v5:
- Per Frank, to support OpenSuse the ENV must be after the GPT
Changes in v4:
- Move env back to being right after the MBR
Changes in v3:
- fix spacing between asterix
- remove verify=n as a default setting
Changes in v2:
- Remove unneeded CONFIG_BOOTFILE and fdt_addr
- cleanup spacing in MMC env size
common
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Ley Foon Tan [Wed, 5 Apr 2017 09:32:51 +0000 (17:32 +0800)]
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan [Wed, 5 Apr 2017 09:32:47 +0000 (17:32 +0800)]
fdt: Add compatible strings for Arria 10
Add compatible strings for Intel Arria 10 SoCFPGA device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 5 Dec 2016 17:17:52 +0000 (18:17 +0100)]
ARM: socfpga: Disable OC on MCVEVK
Disable the OC test on MCVEVK as the old PHY version does not provide
this information. This fixes the USB OTG operation.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 29 Oct 2016 20:08:39 +0000 (22:08 +0200)]
ARM: socfpga: mcvevk: Add default dfu_alt_info
Add default DFU altinfo for eMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 29 Oct 2016 19:15:56 +0000 (21:15 +0200)]
ARM: socfpga: Reduce the DFU buffer size
There is no point in having such gargantuan buffer, it only requires
huge malloc area. Reduce the DFU buffer size.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 5 Apr 2017 11:17:03 +0000 (13:17 +0200)]
ARM: socfpga: Rename MCVEVK
The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: Marek Vasut <marex@denx.de>
Chee, Tien Fong [Wed, 29 Mar 2017 03:49:16 +0000 (11:49 +0800)]
ARM: socfpga: boot0 hook: remove macro from boot0 header file
Commit
ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole
header file") miss out cleaning macro in this header file, and this
has broken implementation of a boot header capability in socfpga
SPL. Remove the macro in this file, and recovering it back
to proper functioning.
Fixes:
ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole
header file")
Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
Georges Savoundararadj [Tue, 28 Mar 2017 05:56:04 +0000 (22:56 -0700)]
ARM: socfpga: cyclone5-socdk: Enable ports A & C
With the port C enabled, we can read the GPI input state of:
* the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4])
* the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8])
Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Signed-off by: Sid-Ali Teir <git.syedelec@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Marek Vasut <marex@denx.de>
Stephen Arnold [Fri, 24 Mar 2017 01:58:08 +0000 (18:58 -0700)]
ARM: socfpga: add fpga build and bsp handoff instructions to readme
This patch adds the steps to manually (re)build a Quartus FPGA project,
generate the required BSP glue, and update u-boot handoff files for
mainline SPL support. Requires Quartus toolchain and current U-Boot.
Signed-off-by: Steve Arnold <stephen.arnold42@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Stefan Agner [Tue, 11 Apr 2017 05:42:14 +0000 (11:12 +0530)]
board: toradex: colibri_vf: Add DCU support for Colibri Vybrid
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Toradex Colibri Vybrid
module.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Stefan Agner [Tue, 11 Apr 2017 05:42:13 +0000 (11:12 +0530)]
video: fsl_dcu_fb: add additional modes for DCU
Add common widescreen modes 800x480 and 1024x600.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Stefan Agner [Tue, 11 Apr 2017 05:42:12 +0000 (11:12 +0530)]
video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting
DCU_LAYER_MAX_NUM is currently used for DCU_MODE_BLEND_ITER and it
actually overflows the maximum value of BLEND_ITER for Vybrid and
LS102XA. Fix this by using a default value of 2.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Stefan Agner [Tue, 11 Apr 2017 05:42:11 +0000 (11:12 +0530)]
video: fsl_dcu_fb: Enable pixel clock after initialization
When enabling the DCU and pixel clock, the test mode is activated
since this is the reset configuration. The test mode immediately
shows a red screen on a LCD. A moment later, the DCU gets
initialized properly.
This patch enables the pixel clock after initialization of the DCU
control register. This avoids this initial flicker on LCD screens.
While at it change the polarity of pixel clock to display samples
data on the rising edge.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Stefan Agner [Tue, 11 Apr 2017 05:42:10 +0000 (11:12 +0530)]
video: fsl_dcu_fb: fix framebuffer to the end of memory
Fix the framebuffer location to the very end of the available memory.
This allows to remove the area from available memory for the kernel,
which in turn allows to display the splash screen through the Linux
kernel boot process.
Ideas has been taken from the sunxi display driver, e.g.
20779ec3a5 ("sunxi: video: Dynamically reserve framebuffer memory")
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Sanchayan Maity [Tue, 11 Apr 2017 05:42:09 +0000 (11:12 +0530)]
Convert CONFIG_FSL_DCU_FB to Kconfig
Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB
and convert it to Kconfig.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Alex Deymo [Sun, 2 Apr 2017 08:24:34 +0000 (01:24 -0700)]
mmc: sdhci: Wait for SDHCI_INT_DATA_END when transferring.
sdhci_transfer_data() function transfers the blocks passed up to the
number of blocks defined in mmc_data, but returns immediately once all
the blocks are transferred, even if the loop exit condition is not met
(bit SDHCI_INT_DATA_END set in the STATUS word).
When doing multiple writes to mmc, returning right after the last block
is transferred can cause the write to fail when sending the
MMC_CMD_STOP_TRANSMISSION command right after the
MMC_CMD_WRITE_MULTIPLE_BLOCK command, leaving the mmc driver in an
unconsistent state until reboot. This error was observed in the rpi3
board.
This patch waits for the SDHCI_INT_DATA_END bit to be set even after
sending all the blocks.
Test: Reliably wrote 2GiB of data to mmc in a rpi3.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jocelyn Bohr [Sun, 2 Apr 2017 08:24:33 +0000 (01:24 -0700)]
mmc: bcm2835_sdhci: Speed up mmc writes.
The linux kernel driver for this module does not use a delay when
writing to the SDHCI_BUFFER register. This patch mimics that behavior
in order to speed up the mmc writes on the Raspberry Pi.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Thu, 13 Apr 2017 02:29:22 +0000 (10:29 +0800)]
mmc: gen_atmel_mci: add driver model support for mci
Add the driver model support for Atmel mci while retaining the
existing legacy code. This allows the driver to support boards
that have converted to driver model as well as those that have not.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>