oweals/u-boot.git
9 years agoAllow objcopy to work without filling gaps with 0xff
Simon Glass [Fri, 31 Jul 2015 15:31:23 +0000 (09:31 -0600)]
Allow objcopy to work without filling gaps with 0xff

This is currently done for all targets, since 0xff is the default erased
value for most flash devices. In some cases this is not what we want (e.g.
for EFI images) so provide a command to do a vanilla objcopy.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agoelf: Add a few definitions for 64-bit relocation
Simon Glass [Fri, 31 Jul 2015 15:31:21 +0000 (09:31 -0600)]
elf: Add a few definitions for 64-bit relocation

Provide the types necessary to relocate 64-bit images.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: serial: Correct logic in serial_find_console_or_panic()
Simon Glass [Fri, 31 Jul 2015 15:31:20 +0000 (09:31 -0600)]
dm: serial: Correct logic in serial_find_console_or_panic()

In a final attempt to find a console UART this function uses the first
first available serial device. However the check for a valid device is
inverted.

This code is only executed when there is in fact no serial UART, but at
present it can fail to reach the panic_str() call in this case, and start
trying to use a non-existent UART.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: core: Check for empty list in uclass_find_device()
Simon Glass [Fri, 31 Jul 2015 15:31:19 +0000 (09:31 -0600)]
dm: core: Check for empty list in uclass_find_device()

This function needs to check the list has entries before traversing it.
Fix this bug.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agoSupport removing default assembler flags
Simon Glass [Fri, 31 Jul 2015 15:31:18 +0000 (09:31 -0600)]
Support removing default assembler flags

The CFLAGS_REMOVE_<file> feature allows default C compiler flags to be
removed for particular files. Add the same feature for assembler, using
AFLAGS_REMOVE_<file>.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
9 years agocommon: command add '\n' for debug msg
Peng Fan [Tue, 28 Jul 2015 14:45:37 +0000 (22:45 +0800)]
common: command add '\n' for debug msg

Add '\n' for debug msg.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agolib: fdt: fix indent of #ifdef..#endif conditional
Masahiro Yamada [Sat, 1 Aug 2015 07:03:25 +0000 (16:03 +0900)]
lib: fdt: fix indent of #ifdef..#endif conditional

Match the depth of indentation between #ifdef and #endif
for better readability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agocommon: Print nothing in the __weak checkboard()
Bin Meng [Fri, 31 Jul 2015 07:24:40 +0000 (00:24 -0700)]
common: Print nothing in the __weak checkboard()

Do not print confusing "Board: Unknown" during boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agogitignore: Add defconfig and fdtgrep
Bin Meng [Fri, 31 Jul 2015 07:24:39 +0000 (00:24 -0700)]
gitignore: Add defconfig and fdtgrep

Ignore defconfig and tools/fdtgrep.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: bayleybay: Configure PCI IRQ
Bin Meng [Thu, 30 Jul 2015 10:49:18 +0000 (03:49 -0700)]
x86: bayleybay: Configure PCI IRQ

Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add Intel Bayley Bay board support
Bin Meng [Thu, 30 Jul 2015 10:49:17 +0000 (03:49 -0700)]
x86: Add Intel Bayley Bay board support

Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add microcode for BayTrail-I B0 stepping
Bin Meng [Thu, 30 Jul 2015 10:49:16 +0000 (03:49 -0700)]
x86: Add microcode for BayTrail-I B0 stepping

This commit adds the microcode blob for BayTrail-I B0 stepping,
CPUID signature 30671h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: baytrail: Update UPD setting for FSP Gold4 release
Bin Meng [Thu, 30 Jul 2015 10:49:15 +0000 (03:49 -0700)]
x86: baytrail: Update UPD setting for FSP Gold4 release

BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: minnowmax: Remove smsc47x superio codes
Bin Meng [Thu, 30 Jul 2015 10:49:14 +0000 (03:49 -0700)]
x86: minnowmax: Remove smsc47x superio codes

On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Sanity test on vesa parameters before setting up kernel screen_info
Bin Meng [Thu, 30 Jul 2015 10:49:13 +0000 (03:49 -0700)]
x86: Sanity test on vesa parameters before setting up kernel screen_info

We should not set up kernel screen_info when the vesa parameters are
insane, otherwise kernel will panic.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: qemu: Add MP initialization
Bin Meng [Mon, 27 Jul 2015 11:16:08 +0000 (19:16 +0800)]
x86: qemu: Add MP initialization

Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a 'pause' instruction in __udelay() for QEMU target
Miao Yan [Mon, 27 Jul 2015 11:16:07 +0000 (19:16 +0800)]
x86: Add a 'pause' instruction in __udelay() for QEMU target

When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.

This patch adds a 'pause' instruction in __udelay() only for QEMU
target, to give other VCPUs a chance to run. When QEMU sees the
'pause' instruction, it will yeild the execution to other CPUs.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agodoc: dm: Update pci-info.txt for pci support
Bin Meng [Mon, 27 Jul 2015 07:33:43 +0000 (00:33 -0700)]
doc: dm: Update pci-info.txt for pci support

Correct two typos and mention how pci bus will be probed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: pci: Allow scan bridge child devices before relocation
Bin Meng [Mon, 27 Jul 2015 07:33:39 +0000 (00:33 -0700)]
dm: pci: Allow scan bridge child devices before relocation

On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. Remove such
limitation so that dm pci can be used before relocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 4 Aug 2015 16:21:45 +0000 (12:21 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

9 years agoconfigs: ti_armv7_keystone2: replace addr_uboot with loadaddr
Vitaly Andrianov [Mon, 3 Aug 2015 19:54:32 +0000 (15:54 -0400)]
configs: ti_armv7_keystone2: replace addr_uboot with loadaddr

This patch replaces not existing addr_uboot environment variable by
loadaddr at get_uboot_net and burn_uboot_xxx commands. Otherwise these
commands are broken.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
9 years agoarmv8/ls2085ardb: Add USB support for ls2085ardb
Nikhil Badola [Fri, 26 Jun 2015 11:32:18 +0000 (17:02 +0530)]
armv8/ls2085ardb: Add USB support for ls2085ardb

Add USB XHCI support for ls2085rdb platform

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv8/ls2085aqds: Add USB support for ls2085aqds
Nikhil Badola [Fri, 26 Jun 2015 11:32:00 +0000 (17:02 +0530)]
armv8/ls2085aqds: Add USB support for ls2085aqds

Add USB XHCI support for ls2085qds platform

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv8/lsch3/config: Define USB XHCI controller base address for LS2085A
Nikhil Badola [Fri, 26 Jun 2015 11:31:50 +0000 (17:01 +0530)]
armv8/lsch3/config: Define USB XHCI controller base address for LS2085A

Define base address of both usb xhci controllers in lsch3 config
in the format (IMMR + offset) for LS2085A

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
Nikhil Badola [Fri, 26 Jun 2015 11:29:21 +0000 (16:59 +0530)]
armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A

Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/ddr/fsl: Adjust bstopre value
York Sun [Thu, 23 Jul 2015 21:04:48 +0000 (14:04 -0700)]
drivers/ddr/fsl: Adjust bstopre value

By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agodrivers/crypto/fsl: clean-up - use fdt_setprop_u32 helper
horia.geanta@freescale.com [Wed, 8 Jul 2015 14:24:58 +0000 (17:24 +0300)]
drivers/crypto/fsl: clean-up - use fdt_setprop_u32 helper

Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/crypto/fsl: fix snooping for write transactions
horia.geanta@freescale.com [Wed, 8 Jul 2015 14:24:57 +0000 (17:24 +0300)]
drivers/crypto/fsl: fix snooping for write transactions

HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.

For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU

Fixes: b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/crypto/fsl: fix "era" property value on LE platforms
horia.geanta@freescale.com [Wed, 8 Jul 2015 14:24:56 +0000 (17:24 +0300)]
drivers/crypto/fsl: fix "era" property value on LE platforms

Use fdt_setprop_u32() instead of fdt_setprop().

Fixes: 0181937fa371a ("crypto/fsl: Add fixup for crypto node")
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/pci/layerscape: Add EP mode support
Minghuan Lian [Fri, 10 Jul 2015 03:35:09 +0000 (11:35 +0800)]
drivers/pci/layerscape: Add EP mode support

The patch will initialize PCIe controller on EP mode
1. Setup bar:
   bar0 32bit 4K for specific configuration
   bar1 32bit 8K for MSIX
   bar2 64bit 4K for descriptor of memory
   bar4 64bit 1M for DMA memory test
2. Setup iATU:
   iATU inbound 0-3 to map bar transaction to memory address
   started at CONFIG_SYS_PCI_EP_MEMORY_BASE
   iATU outbound 0 to map 4G memory space

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/pci: Add function to find an extended capability
Minghuan Lian [Fri, 10 Jul 2015 03:35:08 +0000 (11:35 +0800)]
drivers/pci: Add function to find an extended capability

PCIe extends device's configuration space to 4k and provides
extended capability. The patch adds function to find them.
The code is ported from Linux PCIe driver.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/fsl-mc: flib changes for mc 8.0.0
Prabhakar Kushwaha [Tue, 7 Jul 2015 10:10:06 +0000 (15:40 +0530)]
drivers/fsl-mc: flib changes for mc 8.0.0

MC firware version 8.0.0 contains new command flags. This patch
contains modifications in FLIB files to support the new command flags.

Signed-off-by: Itai Katz <itai.katz@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/crypto/fsl: enable raw data instead of von Neumann data
Alex Porosanu [Tue, 5 May 2015 13:48:35 +0000 (16:48 +0300)]
drivers/crypto/fsl: enable raw data instead of von Neumann data

The sampling of the oscillator can be done in multiple modes for
generating the entropy value. By default, this is set to von
Neumann. This patch changes the sampling to raw data, since it
has been discovered that the generated entropy has a better
'quality'.

Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/crypto/fsl: change starting entropy delay value
Alex Porosanu [Tue, 5 May 2015 13:48:34 +0000 (16:48 +0300)]
drivers/crypto/fsl: change starting entropy delay value

The entropy delay (the length in system clocks of each
entropy sample) for the RNG4 block of CAAM is dependent
on the frequency of the SoC. By elaborate methods, it
has been determined that a good starting value for all
platforms integrating the CAAM IP is 3200. Using a
higher value has additional benefit of  speeding up
the process of instantiating the RNG, since the entropy
delay will be increased and instantiation of the RNG
state handles will be reattempted by the driver. If the
starting value is low, for certain platforms, this can
lead to a quite lengthy process.
This patch changes the starting value of the length of
the entropy sample to 3200 system clocks.
In addition to this change, the attempted entropy delay
values are now printed on the console upon initialization
of the RNG block.

Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/crypto/fsl: disable RNG oscillator maximum frequency check
Alex Porosanu [Tue, 5 May 2015 13:48:33 +0000 (16:48 +0300)]
drivers/crypto/fsl: disable RNG oscillator maximum frequency check

The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the
oscillator, when SEC runs at its maximum frequency. For certain platforms
(f.i. T2080), the oscillator is very fast and thus if the SEC runs at
a lower than normal frequency, the ring oscillator is incorrectly detected
as being out of bounds.

This patch effectively disables the maximum frequency check, by setting a
high enough maximum allowable frequency for the oscillator. The reasoning
behind this is that usually a broken oscillator will run too slow
(i.e. not run at all) rather than run too fast.

Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/ls1021a/etsec: Enable Tx Data and TxBD snooping
Alison Wang [Thu, 9 Jul 2015 03:09:05 +0000 (11:09 +0800)]
armv7/ls1021a/etsec: Enable Tx Data and TxBD snooping

To improve eTSEC performance on LS1021A Rev2.0,
snooping of all transmit frames from memory and
all transmit BD memory accesses in enabled.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/ls1021a: allow OCRAM access permission as R/W in SPL
Alison Wang [Thu, 9 Jul 2015 02:50:07 +0000 (10:50 +0800)]
armv7/ls1021a: allow OCRAM access permission as R/W in SPL

On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin table
Wang Dongsheng [Thu, 18 Jun 2015 10:32:58 +0000 (18:32 +0800)]
armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin table

Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.

Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/ls1021atwr: program the regulator for deep sleep
chenhui zhao [Fri, 15 May 2015 06:42:30 +0000 (14:42 +0800)]
armv7/ls1021atwr: program the regulator for deep sleep

Program the external regulator to switch off voltage in deep sleep.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/ls1021atwr: added deep sleep support in uboot
Tang Yuantian [Thu, 14 May 2015 09:20:28 +0000 (17:20 +0800)]
armv7/ls1021atwr: added deep sleep support in uboot

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/lS1021atwr: Enable bootscript for secure boot
gaurav rana [Tue, 12 May 2015 06:55:01 +0000 (12:25 +0530)]
armv7/lS1021atwr: Enable bootscript for secure boot

Enable bootscript support in secure boot for establishing
chain of trust on LS1021atwr.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodriver/qe: use strncpy instead of strcpy
Zhao Qiang [Tue, 5 May 2015 07:53:33 +0000 (15:53 +0800)]
driver/qe: use strncpy instead of strcpy

strncpy is safer than strcpy, use it to instead of strcpy.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/qe: transform parameter to compatible type
Zhao Qiang [Tue, 5 May 2015 07:53:32 +0000 (15:53 +0800)]
drivers/qe: transform parameter to compatible type

when using printf, the parameter type need to be compatible
type, so transform them to compatible type

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/ls1021a: Reserve secure code into RAM instead of OCRAM
Zhuoyu Zhang [Tue, 24 Mar 2015 09:27:37 +0000 (17:27 +0800)]
armv7/ls1021a: Reserve secure code into RAM instead of OCRAM

For ls1021a, Reserve secure code in to memory in case OCRAM
is needed by other usage.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoPrepare v2015.10-rc1 v2015.10-rc1
Tom Rini [Mon, 3 Aug 2015 14:52:14 +0000 (10:52 -0400)]
Prepare v2015.10-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
9 years agofsl_esdhc.c: Always make check_and_invalidate_dcache_range available
Tom Rini [Sun, 2 Aug 2015 14:27:52 +0000 (10:27 -0400)]
fsl_esdhc.c: Always make check_and_invalidate_dcache_range available

This function is called from esdhc_send_cmd so we need it available to
everyone.

Signed-off-by: Tom Rini <trini@konsulko.com>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-imx
Tom Rini [Sun, 2 Aug 2015 11:40:37 +0000 (07:40 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx

9 years agoarm: mx6: tqma6: fix build for WRU-IV baseboard
Stefano Babic [Sun, 26 Jul 2015 12:28:25 +0000 (14:28 +0200)]
arm: mx6: tqma6: fix build for WRU-IV baseboard

Fix:
 undefined reference to `spi_flash_free'
 undefined reference to `spi_flash_probe'

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefan Roese <sr@denx.de>
9 years agoimx: mx6ul_14x14_evk add basic board support
Peng Fan [Mon, 20 Jul 2015 11:28:35 +0000 (19:28 +0800)]
imx: mx6ul_14x14_evk add basic board support

1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
   supports sd for usdhc2, but can do hardware rework to make usdhc2 support
   emmc.

Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device
 Reset cause: POR
 Board: MX6UL 14x14 EVK
 I2C:   ready
 DRAM:  512 MiB
 MMC:   FSL_SDHC: 0, FSL_SDHC: 1
 *** Warning - bad CRC, using default environment

 In:    serial
 Out:   serial
 Err:   serial
 Net:   CPU Net Initialization Failed
 No ethernet found.
 Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: imx6_spl add mx6ul support
Peng Fan [Mon, 20 Jul 2015 11:28:34 +0000 (19:28 +0800)]
imx: imx6_spl add mx6ul support

i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use
same address with i.MX6SX.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx:mx6ul add dram spl configuration and header file
Peng Fan [Mon, 20 Jul 2015 11:28:33 +0000 (19:28 +0800)]
imx:mx6ul add dram spl configuration and header file

1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
   only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
   runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
   IO configuration.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agomx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL
Peng Fan [Mon, 20 Jul 2015 11:28:32 +0000 (19:28 +0800)]
mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL

DRAM space starts from 0x80000000 for i.MX6UL, so need to
fix LOADADDR, SYS_TEXT_BASE.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agomxc: gpio add i.MX6UL support
Peng Fan [Mon, 20 Jul 2015 11:28:31 +0000 (19:28 +0800)]
mxc: gpio add i.MX6UL support

i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL
Peng Fan [Mon, 20 Jul 2015 11:28:30 +0000 (19:28 +0800)]
imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL

PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul update soc related settings
Peng Fan [Mon, 20 Jul 2015 11:28:29 +0000 (19:28 +0800)]
imx: mx6ul update soc related settings

1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agoimx: mx6ul select SYS_L2CACHE_OFF
Peng Fan [Mon, 20 Jul 2015 11:28:28 +0000 (19:28 +0800)]
imx: mx6ul select SYS_L2CACHE_OFF

i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx:mx6ul add clock support
Peng Fan [Mon, 20 Jul 2015 11:28:27 +0000 (19:28 +0800)]
imx:mx6ul add clock support

1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
   MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
   but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
   sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
   || defined....", only need one CONFIG_PCIE_IMX in header file.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul remove errata for i.MX6UL
Peng Fan [Mon, 20 Jul 2015 11:28:26 +0000 (19:28 +0800)]
imx: mx6ul remove errata for i.MX6UL

Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx-common: timer: add i.MX6UL support
Peng Fan [Mon, 20 Jul 2015 11:28:25 +0000 (19:28 +0800)]
imx-common: timer: add i.MX6UL support

Add i.MX6UL GPT timer support.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
Peng Fan [Mon, 20 Jul 2015 11:28:24 +0000 (19:28 +0800)]
imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL

Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul: Update imx registers head file
Peng Fan [Mon, 20 Jul 2015 11:28:23 +0000 (19:28 +0800)]
imx: mx6ul: Update imx registers head file

1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
   "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
   because we can use runtime check

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul: Add pins IOMUX head file
Peng Fan [Mon, 20 Jul 2015 11:28:22 +0000 (19:28 +0800)]
imx: mx6ul: Add pins IOMUX head file

Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agoimx: mx6ul: Add i.MX6UL CPU type
Peng Fan [Mon, 20 Jul 2015 11:28:21 +0000 (19:28 +0800)]
imx: mx6ul: Add i.MX6UL CPU type

Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agosf: kconfig: add kconfig options for spi flashes
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:38 +0000 (17:19 +0300)]
sf: kconfig: add kconfig options for spi flashes

Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig.

Cc: Jagan Teki <jteki@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agousb: kconfig: create a menu for usb
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:37 +0000 (17:19 +0300)]
usb: kconfig: create a menu for usb

With recent additions to USB Kconfig the number of USB options had grown
large enough to warrant a separate menu for USB.

Add a Kconfig menu for USB.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agousb: kconfig: usb keyboard kconfig
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:36 +0000 (17:19 +0300)]
usb: kconfig: usb keyboard kconfig

Add Kconfig options for USB keyboard and use them for cm-fx6.

Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: usb: kconfig: add USB_EHCI_MX6 kconfig option
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:35 +0000 (17:19 +0300)]
arm: mx6: usb: kconfig: add USB_EHCI_MX6 kconfig option

Add USB_EHCI_MX6 option to menuconfig and use it when migrating cm-fx6 usb
config to defconfig.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: kconfig: don't select CPU_V7 per board
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:34 +0000 (17:19 +0300)]
arm: mx6: kconfig: don't select CPU_V7 per board

CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again
by boards that depend on ARCH_MX6.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agoarm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:33 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6

cm-fx6 is an MX6 based board, and the menuconfig hierarchy should
reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: move CMD configs to defconfig
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:32 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: move CMD configs to defconfig

Move CONFIG_CMD_* options that can be selected in menuconfig to cm-fx6
defconfig.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: setup hdmi only on hdmi enable
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:31 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: setup hdmi only on hdmi enable

Refactor display code to only setup hdmi if do_enable_hdmi() is invoked.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: add support for displaytype env var
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:30 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: add support for displaytype env var

Add support for selecting display preset using the environment variable
"displaytype". This is a preparation for future merging of compulab
omap3_display.c display selection code with the cm-fx6 display selection code.

The "panel" environment variable is retained for backwards compatibility.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: make it possible to not init display
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:29 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: make it possible to not init display

Implement a cm-fx6 specific board_video_skip() to provide the option to not
initialize the display.

The new function does not init display if the environment variable "panel" is
not defined, or if it is set to an unsupported value.

Collateral changes:
- Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific).
- Don't use detect_hdmi(), since env controlled init makes it unnecessary.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: map HDMI to IPU1 DI0 explicitly
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:28 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: map HDMI to IPU1 DI0 explicitly

U-Boot does not explicitly assign the display to an IPU interface. Instead, it
relies on the power-on default of DI0.

Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI
display no longer works in U-Boot.

Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoimx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Peng Fan [Sat, 11 Jul 2015 03:38:47 +0000 (11:38 +0800)]
imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support

1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
   and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)

CPU:   Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoimx: mx6sabresd/sabreauto runtime setting fdt_file
Peng Fan [Sat, 11 Jul 2015 03:38:46 +0000 (11:38 +0800)]
imx: mx6sabresd/sabreauto runtime setting fdt_file

Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.

Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: mx6qp Enable PRG clock for IPU
Peng Fan [Sat, 11 Jul 2015 03:38:45 +0000 (11:38 +0800)]
imx: mx6qp Enable PRG clock for IPU

The i.MX6DQP has a PRG module, need to enable its clock for using IPU.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP
Ye.Li [Sat, 11 Jul 2015 03:38:44 +0000 (11:38 +0800)]
imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP

Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: mx6: ccm: Change the clock settings for i.MX6QP
Peng Fan [Sat, 11 Jul 2015 03:38:43 +0000 (11:38 +0800)]
imx: mx6: ccm: Change the clock settings for i.MX6QP

Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.

In c files, use runtime check and discard #ifdef.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: add cpu type for i.MX6QP/DP
Peng Fan [Sat, 11 Jul 2015 03:38:42 +0000 (11:38 +0800)]
imx: add cpu type for i.MX6QP/DP

Add cpu type for i.MX6QP/DP.

This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Sat, 1 Aug 2015 00:16:21 +0000 (20:16 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Sat, 1 Aug 2015 00:16:04 +0000 (20:16 -0400)]
Merge git://git.denx.de/u-boot-x86

9 years agopowerpc/T104xRDB: Remove vbank check redundant code
Priyanka Jain [Thu, 30 Jul 2015 04:50:18 +0000 (10:20 +0530)]
powerpc/T104xRDB: Remove vbank check redundant code

sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1023rdb: eMMC boot without external SD card
Shengzhou Liu [Tue, 28 Jul 2015 02:46:47 +0000 (10:46 +0800)]
powerpc/t1023rdb: eMMC boot without external SD card

eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4240: update serdes table
Shaohui Xie [Wed, 29 Jul 2015 03:28:36 +0000 (11:28 +0800)]
powerpc/t4240: update serdes table

Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3
support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1023rdb: add support for T1023RDB RevC
Shengzhou Liu [Wed, 17 Jun 2015 08:37:01 +0000 (16:37 +0800)]
powerpc/t1023rdb: add support for T1023RDB RevC

Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM
Aneesh Bansal [Tue, 16 Jun 2015 05:06:43 +0000 (10:36 +0530)]
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM

For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Aneesh Bansal [Tue, 16 Jun 2015 05:06:30 +0000 (10:36 +0530)]
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040

Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Aneesh Bansal [Tue, 16 Jun 2015 05:06:00 +0000 (10:36 +0530)]
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopatman: Don't run patman when it is imported as a module
Simon Glass [Thu, 30 Jul 2015 19:47:41 +0000 (13:47 -0600)]
patman: Don't run patman when it is imported as a module

Commit 488d19c (patman: add distutils based installer) has the side effect
of making patman run twice with each invocation. Fix this by checking for
'main program' invocation in patman.py. This is good practice in any case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
9 years agoarmv8: caches: Added routine to set non cacheable region
Siva Durga Prasad Paladugu [Fri, 26 Jun 2015 12:35:07 +0000 (18:05 +0530)]
armv8: caches: Added routine to set non cacheable region

Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.

Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Wed, 29 Jul 2015 22:58:39 +0000 (18:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra

9 years agopowerpc/T102xRDB: Enable ifc nand ecc encode and decode
Jaiprakash Singh [Fri, 22 May 2015 09:51:07 +0000 (15:21 +0530)]
powerpc/T102xRDB: Enable ifc nand ecc encode and decode

IFC nand ecc encode and decode mode are not correctly
set in CSOR register during nand initialization.Enable
ecc encode/decode in 4-bit mode

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025
Nikhil Badola [Thu, 21 May 2015 03:37:53 +0000 (09:07 +0530)]
powerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025

Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1
for p1025 as it has one USB controller

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/b4860qds: Update README for DIP switch information
Raghav Dogra [Thu, 14 May 2015 11:17:16 +0000 (16:47 +0530)]
powerpc/b4860qds: Update README for DIP switch information

The board manual desribes ON as boolean 1 and OFF as boolean 0.
Updating README with correct boolean values.

Signed-off-by: Raghav Dogra <raghav@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1024: update fman liodn for mac1
Shengzhou Liu [Thu, 14 May 2015 08:51:39 +0000 (16:51 +0800)]
powerpc/t1024: update fman liodn for mac1

MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce
macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have
same Port ID and same offset of address with 1G MAC.
Update it to match with the setting of fman in t1024 device
tree, otherwise there is no 'fsl,liodn' in
/proc/device-tree/soc@ffe000000/fman@400000/port@88000/

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t104x, t102x: Update CPC debug register value in PBI commands
Priyanka Jain [Thu, 7 May 2015 08:54:31 +0000 (14:24 +0530)]
powerpc/t104x, t102x: Update CPC debug register value in PBI commands

Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4rdb: fix cpld reset altbank
Shaohui Xie [Wed, 29 Apr 2015 06:56:53 +0000 (14:56 +0800)]
powerpc/t4rdb: fix cpld reset altbank

cpld reset altbank should always reset to bank4 no matter what
current bank is.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue
Ying Zhang [Fri, 24 Apr 2015 07:49:15 +0000 (15:49 +0800)]
powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue

Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.

In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms
gaurav rana [Thu, 26 Mar 2015 10:22:47 +0000 (15:52 +0530)]
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms

defconfig files are added and SFP version for these platforms
is updated.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>