oweals/u-boot.git
7 years agoarm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G
Stefan Roese [Thu, 9 Mar 2017 13:35:28 +0000 (14:35 +0100)]
arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G

The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool
Stefan Roese [Mon, 13 Mar 2017 05:50:04 +0000 (06:50 +0100)]
net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool

As pointed out by Stefan Chulski, this variable is unused and should be
removed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Configure SMI PHY address needed for PHY polling
Stefan Roese [Fri, 10 Mar 2017 05:07:45 +0000 (06:07 +0100)]
net: mvpp2: Configure SMI PHY address needed for PHY polling

On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Enable PHY polling mode on PPv2.2
Stefan Roese [Thu, 9 Mar 2017 11:01:57 +0000 (12:01 +0100)]
net: mvpp2: Enable PHY polling mode on PPv2.2

Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID
Stefan Roese [Wed, 22 Mar 2017 14:11:00 +0000 (15:11 +0100)]
net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID

Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add GoP and NetC support for port 0 (SFI)
Stefan Roese [Wed, 22 Mar 2017 14:09:38 +0000 (15:09 +0100)]
net: mvpp2: Add GoP and NetC support for port 0 (SFI)

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)
Stefan Roese [Wed, 22 Mar 2017 14:07:30 +0000 (15:07 +0100)]
net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII
Stefan Roese [Wed, 22 Mar 2017 13:15:40 +0000 (14:15 +0100)]
net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII

Read the "phy-speed" DT property to differentiate between 1 and 2.5GB
SGMII operations. Please note that its unclear right now, if this
DT property will be accepted in mainline Linux. If not, we need to
revisit this code and change it to use the accepted property.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Restructure probe / init functions
Stefan Roese [Wed, 22 Mar 2017 13:11:16 +0000 (14:11 +0100)]
net: mvpp2: Restructure probe / init functions

This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: include/phy.h: Add new PHY interface modes
Stefan Roese [Thu, 23 Feb 2017 10:58:26 +0000 (11:58 +0100)]
net: include/phy.h: Add new PHY interface modes

This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will
be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add RX and TX FIFO configuration for PPv2.2
Stefan Roese [Wed, 1 Mar 2017 12:09:42 +0000 (13:09 +0100)]
net: mvpp2: Add RX and TX FIFO configuration for PPv2.2

This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Handle eth device naming in multi-CP case correctly
Stefan Roese [Fri, 24 Feb 2017 09:12:41 +0000 (10:12 +0100)]
net: mvpp2: Handle eth device naming in multi-CP case correctly

Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoarm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver
Stefan Roese [Mon, 20 Feb 2017 11:25:26 +0000 (12:25 +0100)]
arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver

Since we've now integrated the A7k/8k support in the mvpp2 ethernet
driver, lets enable the support for both Marvell developments boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoarm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
Thomas Petazzoni [Mon, 20 Feb 2017 11:27:25 +0000 (12:27 +0100)]
arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K

This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Enable compilation for Armada 7K/8K platforms
Stefan Roese [Wed, 15 Feb 2017 10:42:59 +0000 (11:42 +0100)]
net: mvpp2: Enable compilation for Armada 7K/8K platforms

Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2.c: Clear all buffer / descriptor areas before usage
Stefan Roese [Thu, 16 Feb 2017 12:29:08 +0000 (13:29 +0100)]
net: mvpp2.c: Clear all buffer / descriptor areas before usage

This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Move probe function from MISC to ETH DM driver
Stefan Roese [Thu, 16 Feb 2017 14:26:06 +0000 (15:26 +0100)]
net: mvpp2: Move probe function from MISC to ETH DM driver

This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Add MDIO support for PPv2.2
Stefan Roese [Thu, 16 Feb 2017 07:31:32 +0000 (08:31 +0100)]
net: mvpp2: Add MDIO support for PPv2.2

In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: finally add the PPv2.2 compatible string
Thomas Petazzoni [Mon, 20 Feb 2017 10:54:31 +0000 (11:54 +0100)]
net: mvpp2: finally add the PPv2.2 compatible string

Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: adapt rxq distribution to PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 08:03:16 +0000 (09:03 +0100)]
net: mvpp2: adapt rxq distribution to PPv2.2

In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field
  'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
  RXQs per port. This field is initialized during ->probe() depending
  on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
  number of RXQs by multiplying the number of ports by the maximum of
  RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
  to cope with the different allocation strategy between PPv2.1 and
  PPv2.2. Due to this change, the 'next_first_rxq' argument of this
  function is no longer needed and is removed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: rework RXQ interrupt group initialization for PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 07:46:37 +0000 (08:46 +0100)]
net: mvpp2: rework RXQ interrupt group initialization for PPv2.2

This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: add AXI bridge initialization for PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 07:41:07 +0000 (08:41 +0100)]
net: mvpp2: add AXI bridge initialization for PPv2.2

The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: handle misc PPv2.1/PPv2.2 differences
Thomas Petazzoni [Mon, 20 Feb 2017 10:42:51 +0000 (11:42 +0100)]
net: mvpp2: handle misc PPv2.1/PPv2.2 differences

This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: handle register mapping and access for PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 07:03:37 +0000 (08:03 +0100)]
net: mvpp2: handle register mapping and access for PPv2.2

This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one
  area per port.

- On PPv2.2, we have a first area for the common registers, and a
  second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2
Thomas Petazzoni [Mon, 20 Feb 2017 10:36:57 +0000 (11:36 +0100)]
net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2

In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: adapt mvpp2_defaults_set() to PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 05:57:24 +0000 (06:57 +0100)]
net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2

This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2
Thomas Petazzoni [Thu, 16 Feb 2017 05:53:51 +0000 (06:53 +0100)]
net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2

The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: adjust the allocation/free of BM pools for PPv2.2
Thomas Petazzoni [Mon, 20 Feb 2017 10:29:16 +0000 (11:29 +0100)]
net: mvpp2: adjust the allocation/free of BM pools for PPv2.2

This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:

- Checking that the number of buffer pointers is a multiple of 16, as
  required by the hardware.

- Adjusting the size of the DMA coherent area allocated for buffer
  pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per
  buffer, as opposed to 2 pointers of 32-bits per buffer in
  PPv2.1. The size in bytes is now stored in a new field of the
  mvpp2_bm_pool structure.

- On PPv2.2, getting the physical and virtual address of each buffer
  requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order
  bits of those addresses. A new utility function
  mvpp2_bm_bufs_get_addrs() is introduced to handle this.

- On PPv2.2, releasing a buffer requires writing the high order 32 bits
  of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no
  longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors
Thomas Petazzoni [Mon, 20 Feb 2017 10:08:46 +0000 (11:08 +0100)]
net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors

This commit adds the definition of the PPv2.2 HW descriptors, adjusts
the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts
the accessors to work on both PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: introduce an intermediate union for the TX/RX descriptors
Thomas Petazzoni [Wed, 15 Feb 2017 15:25:53 +0000 (16:25 +0100)]
net: mvpp2: introduce an intermediate union for the TX/RX descriptors

Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descriptors can only be accessed and modified through the accessor
functions. A follow-up commit will add the descriptor definitions for
PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: add hw_version field in "struct mvpp2"
Thomas Petazzoni [Wed, 15 Feb 2017 13:08:59 +0000 (14:08 +0100)]
net: mvpp2: add hw_version field in "struct mvpp2"

In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.

Having the MVPP21 and MVPP22 definitions available will allow to start
adding the necessary conditional code to support PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: add and use accessors for TX/RX descriptors
Thomas Petazzoni [Wed, 15 Feb 2017 14:35:00 +0000 (15:35 +0100)]
net: mvpp2: add and use accessors for TX/RX descriptors

The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.

For now, the mvpp2_port argument passed to the accessors is not used,
but it will be used in follow-up to update the descriptor according to
the version of the IP being used.

Apart from the mechanical changes to use the newly introduced
accessors, a few other changes, needed to use the accessors, are made:

- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first
  argument, as it is needed to use the accessors.

- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first
  argument, for the same reason.

- In mvpp2_rx_error(), instead of accessing the RX descriptor in each
  case of the switch, we introduce a local variable to store the
  packet size.

- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie"
  variable to store the RX descriptor cookie, rather than accessing
  it from the descriptor each time.

- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the
  packet size from the TX descriptor, we use the actual value
  available in the function, which is used to set the TX descriptor
  packet size a few lines before.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: store physical address of buffer in rx_desc->buf_cookie
Thomas Petazzoni [Mon, 20 Feb 2017 09:37:59 +0000 (10:37 +0100)]
net: mvpp2: store physical address of buffer in rx_desc->buf_cookie

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: remove support for buffer header
Thomas Petazzoni [Mon, 20 Feb 2017 09:29:43 +0000 (10:29 +0100)]
net: mvpp2: remove support for buffer header

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: use "dma" instead of "phys" where appropriate
Thomas Petazzoni [Mon, 20 Feb 2017 09:27:51 +0000 (10:27 +0100)]
net: mvpp2: use "dma" instead of "phys" where appropriate

As indicated by Russell King, the mvpp2 driver currently uses a lot
"phys" or "phys_addr" to store what really is a DMA address. This commit
clarifies this by using "dma" or "dma_addr" where appropriate.

This is especially important as we are going to introduce more changes
where the distinction between physical address and DMA address will be
key.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: enable building on 64-bit platforms (more U-Boot specific)
Stefan Roese [Wed, 15 Feb 2017 11:46:18 +0000 (12:46 +0100)]
net: mvpp2: enable building on 64-bit platforms (more U-Boot specific)

Some more U-Boot specific 64bit support changes, mostly changing u32
to unsigned long.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: enable building on 64-bit platforms
Thomas Petazzoni [Wed, 15 Feb 2017 11:31:53 +0000 (12:31 +0100)]
net: mvpp2: enable building on 64-bit platforms

The mvpp2 is going to be extended to support the Marvell Armada 7K/8K
platform, which is ARM64. As a preparation to this work, this commit
enables building the mvpp2 driver on ARM64, by:

 - Adjusting the Kconfig dependency

 - Fixing the types used in the driver so that they are 32/64-bits
   compliant. We use dma_addr_t for DMA addresses, and unsigned long
   for virtual addresses.

It is worth mentioning that after this commit, the driver is for now
still only used on 32-bits platforms, and will only work on 32-bits
platforms.

Changed by Stefan for U-Boot:
Removed the Kconfig change as it does not apply to U-Boot this way.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: simplify MVPP2_PRS_RI_* definitions
Thomas Petazzoni [Wed, 15 Feb 2017 11:19:36 +0000 (12:19 +0100)]
net: mvpp2: simplify MVPP2_PRS_RI_* definitions

Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.

Therefore, such definitions should just be set to 0x0. In addition, as
suggested by Russell King, we change the _MASK definitions to also use
the BIT() macro so that it is clear they are related to the values
defined afterwards.

For example:

 #define MVPP2_PRS_RI_L2_CAST_MASK              0x600
 #define MVPP2_PRS_RI_L2_UCAST                  ~(BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

becomes

 #define MVPP2_PRS_RI_L2_CAST_MASK              (BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_UCAST                  0x0
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and
MVPP2_PRS_RI_L2_BCAST) are always applied with
MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for
MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).

It fixes the following warnings when building the driver on a 64-bit
platform (which is not possible as of this commit, but will be enabled
in a follow-up commit):

drivers/net/ethernet/marvell/mvpp2.c: In function â€˜mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow]
 #define MVPP2_PRS_RI_L2_UCAST   ~(BIT(9) | BIT(10))
                                  ^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro â€˜MVPP2_PRS_RI_L2_UCAST’
     mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT
Thomas Petazzoni [Wed, 15 Feb 2017 11:16:23 +0000 (12:16 +0100)]
net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: remove unused register definitions
Thomas Petazzoni [Wed, 15 Feb 2017 11:15:01 +0000 (12:15 +0100)]
net: mvpp2: remove unused register definitions

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: simplify mvpp2_bm_bufs_add()
Thomas Petazzoni [Wed, 15 Feb 2017 11:13:43 +0000 (12:13 +0100)]
net: mvpp2: simplify mvpp2_bm_bufs_add()

The mvpp2_bm_bufs_add() currently creates a fake cookie by calling
mvpp2_bm_cookie_pool_set(), just to be able to call
mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract
the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.

Instead of doing this convoluted thing, just call mvpp2_bm_pool_put()
directly, since we have the BM pool ID.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: mvpp2: Round up top tx buffer boundaries for dcache ops
Stefan Roese [Thu, 16 Feb 2017 12:58:37 +0000 (13:58 +0100)]
net: mvpp2: Round up top tx buffer boundaries for dcache ops

check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.

This gets rid of the warnings:
CACHE: Misaligned operation at range ...

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agobitops.h: Include bitsperlong.h as needed for GENMASK_ULL
Stefan Roese [Mon, 20 Feb 2017 15:50:26 +0000 (16:50 +0100)]
bitops.h: Include bitsperlong.h as needed for GENMASK_ULL

The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is
defined in the bitsperlong.h header. Lets include this header as
the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver
uses this macro.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoarc: use timer driver for ARC boards
Vlad Zakharov [Tue, 21 Mar 2017 11:49:49 +0000 (14:49 +0300)]
arc: use timer driver for ARC boards

This commit replaces legacy timer code with usage of arc timer
driver.

It removes arch/arc/lib/time.c file and selects CONFIG_CLK,
CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default.
Therefore we remove CONFIG_CLK option from less common axs101 and
axs103 defconfigs.

Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from
axs10x.h, tb100.h and nsim.h configs files as it is no longer required.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoarc: dts: separate single axs10x.dts file
Vlad Zakharov [Tue, 21 Mar 2017 11:49:48 +0000 (14:49 +0300)]
arc: dts: separate single axs10x.dts file

We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.

Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.

So this commit is the first step on the road to unified device tree blobs.

First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.

Also we delete axs10x.dts as it is no longer used.

One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodrivers: timer: Introduce ARC timer driver
Vlad Zakharov [Tue, 21 Mar 2017 11:49:47 +0000 (14:49 +0300)]
drivers: timer: Introduce ARC timer driver

This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.

This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoarm: mvebu: Add gdsys ControlCenter-Compact board
Dirk Eibach [Wed, 22 Feb 2017 15:07:23 +0000 (16:07 +0100)]
arm: mvebu: Add gdsys ControlCenter-Compact board

The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.

It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.

On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agodm: Add callback to modify the device tree
mario.six@gdsys.cc [Wed, 22 Feb 2017 15:07:22 +0000 (16:07 +0100)]
dm: Add callback to modify the device tree

Certain boards come in different variations by way of utilizing daughter
boards, for example. These boards might contain additional chips, which
are added to the main board's busses, e.g. I2C.

The device tree support for such boards would either, quite naturally,
employ the overlay mechanism to add such chips to the tree, or would use
one large default device tree, and delete the devices that are actually
not present.

Regardless of approach, even on the U-Boot level, a modification of the
device tree is a prerequisite to have such modular families of boards
supported properly.

Therefore, we add an option to make the U-Boot device tree (the actual
copy later used by the driver model) writeable, and add a callback
method that allows boards to modify the device tree at an early stage,
at which, hopefully, also the application of device tree overlays will
be possible.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: theadorable: Add 'pcie' test command
Stefan Roese [Fri, 10 Mar 2017 14:40:32 +0000 (15:40 +0100)]
arm: mvebu: theadorable: Add 'pcie' test command

This board specific command tests for the presence of a specified PCIe
device (via vendor-ID and device-ID). If the device is not detected,
this will get printed. If the device is detected, the board will get
resetted so that an easy loop test can be done. The board will reboot
until the PCIe device is not detected.

Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: theadorable: Add board-specific PEX detection pulse width
Stefan Roese [Fri, 10 Mar 2017 14:40:31 +0000 (15:40 +0100)]
arm: mvebu: theadorable: Add board-specific PEX detection pulse width

Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).

In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: AXP: Add possiblity to configure PEX detection pulse width
Stefan Roese [Fri, 10 Mar 2017 14:40:30 +0000 (15:40 +0100)]
arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width

Tests have shown that on some boards the default width of the
configuration pulse for the PEX link detection might lead to
non-established PCIe links (link down). Especially under certain
conditions (higher temperature) and with specific PCIe devices
(in the case on the theadorable board its a Atheros PCIe WLAN
device). To enable a board-specific detection pulse width this weak
array "serdes_pex_pulse_width[4]" is introduced which can be
overwritten if needed by a board-specific version. If the board
code does not provide a non-weak version of this variable, the
default value will be used. So nothing is changed from the
current setup on the supported board.

Many thanks to Adam from Marvell for all his insights here and
his suggestion about testing with a changed detection pulse width.

Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Adam Shobash <adams@marvell.com>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: a37xx: Remove DM_I2C_COMPAT from the board config
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:33 +0000 (13:52 +0200)]
arm64: a37xx: Remove DM_I2C_COMPAT from the board config

Remove DM_I2C_COMPAT from the board configurations for
Armada 37xx platform boards for supressing the buid tim
warning.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: a37xx: Disable DB configurations on ESPRESSOBin board
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:32 +0000 (13:52 +0200)]
arm64: a37xx: Disable DB configurations on ESPRESSOBin board

Bypass XHCI and AHCi board configuration flow on ESPRESSOBin
community board.
The community board does not have i2c expander and USB VBUS
is always on, so the scan for AHCi and USB devices can be
faster without unneded configurations.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Add default config for ESPRESSOBin board
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:31 +0000 (13:52 +0200)]
arm64: mvebu: Add default config for ESPRESSOBin board

Add initial default configuration for Marvell ESPRESSOBin
community board based on Aramda-3720 SoC

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: dts: Add device tree for ESPRESSOBin board
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:30 +0000 (13:52 +0200)]
arm64: dts: Add device tree for ESPRESSOBin board

Initial DTS file for Marvell ESPRESSOBin comunity board
based on Armada-3720 SoC.
The Marvell ESPRESSOBin is a tiny board made by Globalscale
and available on KickStarter site. It has dual core Armv8
Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM,
mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0
interfaces, Gigabit Ethernet switch with 3 ports, micro-SD
socket and two 46-pin GPIO connectors.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agomvebu: a37xx: Add init for ESPRESSBin Topaz switch
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:29 +0000 (13:52 +0200)]
mvebu: a37xx: Add init for ESPRESSBin Topaz switch

Implement the board-specific network init function for
ESPRESSOBin community board, setting the on-board Topaz
switch port to forward mode and allow network connection
through any of the available Etherenet ports.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agomvebu: neta: a37xx: Add fixed link support to neta driver
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:28 +0000 (13:52 +0200)]
mvebu: neta: a37xx: Add fixed link support to neta driver

Add support for fixed link to NETA driver.
This feature requreed for proper support of SFP modules
and onboard connected devices like Ethernet switches

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agomvebu: neta: Add support for board init function
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:27 +0000 (13:52 +0200)]
mvebu: neta: Add support for board init function

Add ability to use board-specific initialization flow
to NETA driver (for instance Ethernet switch bring-up)

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: a37xx: Handle pin controls in early board init
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:26 +0000 (13:52 +0200)]
arm64: a37xx: Handle pin controls in early board init

Fix the default pin control values in a board-specific
function on early board init stage.
This fix allows the NETA driver to work in RGMII
mode until the full-featured pin control driver gets
introduced.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: a37xx: dts: Add pin control nodes to DT
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:25 +0000 (13:52 +0200)]
arm64: a37xx: dts: Add pin control nodes to DT

Add pin control nodes for North and South bridges to
Armada-37xx DT

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: a37xx: Enable bubt command support on A3720-DB
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:24 +0000 (13:52 +0200)]
arm64: a37xx: Enable bubt command support on A3720-DB

Enable mvebu bubt command support on A3720 DB

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: a37xx: Enable Marvell ETH PHY support
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:23 +0000 (13:52 +0200)]
arm64: a37xx: Enable Marvell ETH PHY support

Enable support for Marvell Ethernet PHYs on A37xx platforms

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Rename the db-88f3720 to armada-37xx platform
Konstantin Porotchkin [Thu, 16 Feb 2017 11:52:22 +0000 (13:52 +0200)]
arm64: mvebu: Rename the db-88f3720 to armada-37xx platform

Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agomvebu: usb: xhci: Add VBUS regulator supply to the host driver
Konstantin Porotchkin [Sun, 12 Feb 2017 09:10:30 +0000 (11:10 +0200)]
mvebu: usb: xhci: Add VBUS regulator supply to the host driver

The USB device should linked to VBUS regulator through "vbus-supply"
DTS property.
This patch adds handling for "vbus-supply" property inside the USB
device entry for turning on the VBUS regulator upon the host adapter probe.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: Add default configuraton for MACCHIATOBin board
Konstantin Porotchkin [Thu, 9 Feb 2017 10:39:37 +0000 (12:39 +0200)]
arm64: mvebu: Add default configuraton for MACCHIATOBin board

Add default configuration for MACHHIATOBin community board
based on Aramda-8040 SoC.

Change-Id: Ic6b562065c0929ec338492452f765115c15a6188
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: dts: Add DTS file for MACCHIATOBin board
Rabeeh Khoury [Thu, 9 Feb 2017 10:39:10 +0000 (12:39 +0200)]
arm64: mvebu: dts: Add DTS file for MACCHIATOBin board

Added A8040 dts file for community board MACCHIATIBin.
The patch includes the following features:
AP -  Serial console (connected to onboard FTDI usb to serial)
CP0 - PCIe x4, SATA, I2C and 10G KR
      (connected to Marvell 3310 10G copper / SFP+ phy)
CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR
      (connected to Marvell 3310 10G copper / SFP+ phy),
      SGMII connected to onboard 1512 1Gbps copper phy,
      and additional SGMII connected to SFP
      (default 1Gbps can be configured to 2.5Gbps).

Network interface naming -
egiga0 - CP0 KR
egiga1 - CP1 KR
egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot)
egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agomvebu: pcie: Add support for GPIO reset for PCIe device
Konstantin Porotchkin [Wed, 8 Feb 2017 15:34:13 +0000 (17:34 +0200)]
mvebu: pcie: Add support for GPIO reset for PCIe device

Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y

Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: dts: Add i2c1 pin definitions to CPM
Konstantin Porotchkin [Wed, 8 Feb 2017 15:34:12 +0000 (17:34 +0200)]
arm64: mvebu: dts: Add i2c1 pin definitions to CPM

Add i2c-1 pin mappings to CP0(master) DTSI file

Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm64: mvebu: gpio: Add GPIO nodes to A8K family devices
Konstantin Porotchkin [Wed, 8 Feb 2017 15:34:11 +0000 (17:34 +0200)]
arm64: mvebu: gpio: Add GPIO nodes to A8K family devices

Add GPIO nodes to AP-806 and CP-110-master DTSI files.

Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agodtoc: make ScanTree recurse into subnodes
Philipp Tomsich [Wed, 22 Feb 2017 18:06:04 +0000 (19:06 +0100)]
dtoc: make ScanTree recurse into subnodes

Previously, dtoc could only process the top-level nodes which led to
device nodes in hierarchical trees to be ignored. E.g. the mmc0 node
in the following example would be ignored, as only the soc node was
processed:

  / {
soc {
mmc0 {
/* ... */
};
};
  };

This introduces a recursive helper method ScanNode, which is used by
ScanTree to recursively parse the entire tree hierarchy.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodrivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register
Jean-Jacques Hiblot [Mon, 13 Feb 2017 15:17:49 +0000 (16:17 +0100)]
drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register

We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.

If SYSCON is not supported, the driver reverts to the old way of getting
the address from the 3rd memory range

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
7 years agoregmap: use fdt address translation
Jean-Jacques Hiblot [Mon, 13 Feb 2017 15:17:48 +0000 (16:17 +0100)]
regmap: use fdt address translation

In the DTS, the addresses are defined relative to the parent bus. We need
to translate them to get the address as seen by the CPU core.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
7 years agodm: core: Fix Handling of global_data moving in SPL
Lokesh Vutla [Mon, 13 Feb 2017 03:51:22 +0000 (09:21 +0530)]
dm: core: Fix Handling of global_data moving in SPL

commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL")
handles relocation of GD in SPL if spl_init() is called before
board_init_r(). So, uclass_root.next need not be initialized always
and accessing uclass_root.next->prev gives an abort. Update the
uclass_root only if it is available.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agommc: xenon_sdhci: Add missing host->max_clk to Xenon SDHCI driver
Stefan Roese [Mon, 20 Mar 2017 16:00:32 +0000 (17:00 +0100)]
mmc: xenon_sdhci: Add missing host->max_clk to Xenon SDHCI driver

The Xenon SDHCI driver just missed the integration of this patch:

git ID 6d0e34bf
mmc: sdhci: Distinguish between base clock and maximum peripheral frequency

With this patch applied, the SDHCI subsystem complains now with this warning
while probing:

sdhci_setup_cfg: Hardware doesn't specify base clock frequency

This patch fixes this issue, by providing the missing host->max_clk
variable to the SDHCI subsystem.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Hu Ziji <huziji@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
7 years agommc: drop unnecessary send_status request
Xu Ziyuan [Sun, 12 Mar 2017 06:19:04 +0000 (14:19 +0800)]
mmc: drop unnecessary send_status request

It's redundant to send cmd13 after cmd9 whose response is not R1b. The
card devices will not be busy w/ cmd9.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
7 years agommc: sdhci: only flush cache for data command
Kevin Liu [Wed, 8 Mar 2017 07:16:44 +0000 (15:16 +0800)]
mmc: sdhci: only flush cache for data command

No need to flush cache for command without data.

Signed-off-by: Kevin Liu <kevinliu@asrmicro.com>
7 years agommc: tangier: Add Intel Tangier eMMC/SDHCI driver
Felipe Balbi [Mon, 20 Feb 2017 11:24:14 +0000 (14:24 +0300)]
mmc: tangier: Add Intel Tangier eMMC/SDHCI driver

This patch adds Intel Tangier eMMC/SDHCI driver.

Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI
controller is one of the devices which are *not* on a PCI and, hence,
cannot be enumerated by standard PCI means. This driver, allows for
SDHCI controller on Tangier SoC to work in U-Boot.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7 years agommc: pci: Add CONFIG_MMC_PCI
Felipe Balbi [Mon, 20 Feb 2017 11:24:13 +0000 (14:24 +0300)]
mmc: pci: Add CONFIG_MMC_PCI

We don't want pci_mmc to compile every time x86 compiles, only when
there's a platform that needs it. For that reason, we're adding a new
CONFIG_MMC_PCI which platforms can choose to enable.

Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 years agoconfigs: am43xx_evm: Enable SPL_DM
Lokesh Vutla [Tue, 21 Feb 2017 06:10:44 +0000 (11:40 +0530)]
configs: am43xx_evm: Enable SPL_DM

Enable SPL_DM on all AM43xx based platforms

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoARM: AM43xx: Enable DM_I2C/SPI/ETH
Lokesh Vutla [Tue, 21 Feb 2017 06:10:43 +0000 (11:40 +0530)]
ARM: AM43xx: Enable DM_I2C/SPI/ETH

Enable DM_I2C/SPI/ETH for all AM43XX based boards.
Enable it using imply keyword so that a user can
disable this when not needed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: dts: am43xx: Add u-boot specific dtsi
Lokesh Vutla [Tue, 21 Feb 2017 06:10:42 +0000 (11:40 +0530)]
ARM: dts: am43xx: Add u-boot specific dtsi

Add u-boot specific dtsi for am43xx-gp-evm so
that it will be used for SPL.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoconfigs: dra7xx_evm: Enable SPL_DM
Lokesh Vutla [Fri, 10 Feb 2017 15:07:20 +0000 (20:37 +0530)]
configs: dra7xx_evm: Enable SPL_DM

Enable SPL_DM on all DRA7 based platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoconfigs: am57xx_evm: Enable SPL_DM
Lokesh Vutla [Fri, 10 Feb 2017 15:07:19 +0000 (20:37 +0530)]
configs: am57xx_evm: Enable SPL_DM

Enable SPL_DM on all AM57xx based platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: dts: OMAP5+: Add u-boot specific dtsi
Lokesh Vutla [Fri, 10 Feb 2017 15:07:18 +0000 (20:37 +0530)]
ARM: dts: OMAP5+: Add u-boot specific dtsi

Add u-boot specific dtsi so that this will be
included automatically while building dts.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP2+: define _image_binary_end to fix SPL_OF_CONTROL
Lokesh Vutla [Fri, 10 Feb 2017 15:07:17 +0000 (20:37 +0530)]
ARM: OMAP2+: define _image_binary_end to fix SPL_OF_CONTROL

To make SPL_OF_CONTROL work on OMAP2+ SoCs, _image_binary_end must be
defined in the linker script along with CONFIG_SPL_SEPARATE_BSS.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agospl: Correct call to spl_common_init() with SPL_STACK_R_MALLOC_SIMPLE_LEN
Tom Rini [Mon, 20 Mar 2017 18:19:27 +0000 (14:19 -0400)]
spl: Correct call to spl_common_init() with SPL_STACK_R_MALLOC_SIMPLE_LEN

Calls to IS_ENABLED() on a non-y/n option will always be false, even
when set.  We can correct this by adding a new bool value that is set
based on the conditions required for SPL_STACK_R_MALLOC_SIMPLE_LEN to be
set instead.

Fixes: 340f418acd11 ("spl: Add spl_early_init()")
Reported-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v2:
- Fix thinko pointed out by Lokesh

7 years agoboard: ns2: Add support for Broadcom Northstar 2
Jon Mason [Fri, 17 Mar 2017 16:12:14 +0000 (12:12 -0400)]
board: ns2: Add support for Broadcom Northstar 2

Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k).  The
BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
processors targeting a broad range of networking applications.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
7 years agoda850: Add instructions to copy AIS image to NAND
ahaslam@baylibre.com [Fri, 17 Mar 2017 15:55:23 +0000 (16:55 +0100)]
da850: Add instructions to copy AIS image to NAND

Add instructions to write an AIS image to NAND
by using the u-boot nand tools.

Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
7 years agoPass empty CFLAGS on invocation of libfdt/setup.py
Max Filippov [Thu, 16 Mar 2017 22:23:55 +0000 (15:23 -0700)]
Pass empty CFLAGS on invocation of libfdt/setup.py

When building u-boot tools in cross-build environment CFLAGS environment
variable set up for target is taken into an account when building code
for host. Make it empty on invocation of python.

This fixes the following build errors when cross-compiling for xtensa:

  cc1: error: unrecognized command line option "-mlongcalls"
  cc1: error: unrecognized command line option "-mauto-litpools"

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoKconfig: Don't use RSA_FREESCALE_EXP on IMX
George McCollister [Thu, 16 Mar 2017 21:17:06 +0000 (16:17 -0500)]
Kconfig: Don't use RSA_FREESCALE_EXP on IMX

The CAAM in IMX parts doesn't support public key hardware acceleration
(PKHA), so don't use RSA_FREESCALE_EXP. If you try to use it on IMX
(assuming you have the clocks enabled first) you will get back an
"Invalid KEY Command" error since PKHA isn't a valid key destination for
these parts.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoARM: am43xx: fix SOC revision print outs
Tero Kristo [Thu, 16 Mar 2017 07:48:54 +0000 (09:48 +0200)]
ARM: am43xx: fix SOC revision print outs

Currently, AM43xx just re-uses the version strings from AM33xx which is
wrong; the actual values for AM43xx are different. Fix this by adding
a separate version string array for AM43xx and use this instead.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agotest-fit.py: Minor grammar/spelling/clarification tweaks
Robert P. J. Day [Mon, 13 Mar 2017 10:50:55 +0000 (06:50 -0400)]
test-fit.py: Minor grammar/spelling/clarification tweaks

* Add note that execution needs Python development package installed
* Standardize on upper case "FIT", "FDT" as necessary for clarity
* Fix "tempoerary", "linex" typos

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
7 years agopart_efi: document device-tree binding for part_efi configuration
Philipp Tomsich [Wed, 1 Mar 2017 20:10:41 +0000 (21:10 +0100)]
part_efi: document device-tree binding for part_efi configuration

This adds documentation on the u-boot,efi-partition-entries-offset
property (which overrides CONFIG_EFI_PARTITION_ENTRIES_OFF, if
present).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodoc: move documentation for /config node into a separate file
Philipp Tomsich [Wed, 1 Mar 2017 20:10:40 +0000 (21:10 +0100)]
doc: move documentation for /config node into a separate file

This moves the description of the /config node from README.fdt-control
into a separate file doc/device-tree-bindings/config.txt.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agopart_efi: support padding between the GPT header and partition entries
Philipp Tomsich [Wed, 1 Mar 2017 20:10:39 +0000 (21:10 +0100)]
part_efi: support padding between the GPT header and partition entries

Some architectures require their SPL loader at a fixed address within
the first 16KB of the disk. To avoid an overlap with the partition
entries of the EFI partition table, the first safe offset (in bytes,
from the start of the device) for the entries can be set through
CONFIG_EFI_PARTITION_ENTRIES_OFF (via Kconfig)

When formatting a device with an EFI partition table, we may need to
leave a gap between the GPT header (always in LBA 1) and the partition
entries. The GPT header already contains a field to specify the
on-disk location, which has so far always been set to LBA 2. With this
change, a configurable offset will be translated into a LBA address
indicating where to put the entries.

Now also allows an override via device-tree using a config-node (see
doc/device-tree-bindings/config.txt for documentation).

Tested (exporting an internal MMC formatted with this) against Linux,
MacOS X and Windows.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: __maybe_unused on config_offset to avoid warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agonet: don't override ethernet address environment
Roger Quadros [Mon, 13 Mar 2017 13:04:33 +0000 (15:04 +0200)]
net: don't override ethernet address environment

If the ethernet address environment is set with a valid
ethernet address prevent overriding it as it is most likely
set by the user and he/she doesn't want board code to
automatically override it whatsoever.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoARM: k2g: setup PRU ethernet MAC addresses
Roger Quadros [Mon, 13 Mar 2017 13:04:32 +0000 (15:04 +0200)]
ARM: k2g: setup PRU ethernet MAC addresses

PRU ethernet MAC address range is present in the
board EEPROM. Parse it and setup eth?addr
environment variables.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoARM: Use Kconfig for board EEPROM's I2C bus and chip address
Roger Quadros [Mon, 13 Mar 2017 13:04:31 +0000 (15:04 +0200)]
ARM: Use Kconfig for board EEPROM's I2C bus and chip address

In stead of defining the board EEPROM address in the board headers
let's define them in the board config files and make them
configurable by Kconfig.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoboard: ti: am57xx-idk: Auto detect LCD Panel
Nishanth Menon [Mon, 13 Mar 2017 13:04:30 +0000 (15:04 +0200)]
board: ti: am57xx-idk: Auto detect LCD Panel

AM571x IDK and AM572x IDK have optional LCD Kits that can be purchased.
These can be one of OSD101T2045 or the newer OSD101T2587. The LCD panel
itself has no registers that can be used to identify the panel, however,
the touchscreen controllers on the panels are different.

Hence to ease user experience, we can use the touch screen controller's
ID information to detect what kind of panel we use and select the
appropriate kernel dtb for the platform configuration.

NOTE: AM572x IDK default configuration is for LCD Connectivity, however
the AM571x IDK has a jumper (J51) that needs to be mounted for the IDK
to operate with LCD (Vs two PRUSS ethernet port option).

Touchscreen ID information is documented in:
http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf

Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoboard: ti: am571x-idk: Update pinmux for ICSS2 Ethernet
Roger Quadros [Mon, 13 Mar 2017 13:04:29 +0000 (15:04 +0200)]
board: ti: am571x-idk: Update pinmux for ICSS2 Ethernet

Use the same convention that was used for ICSS1 Ethernet
- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>