David Wu [Tue, 16 Apr 2019 13:50:56 +0000 (21:50 +0800)]
pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomux
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
David Wu [Tue, 16 Apr 2019 13:50:55 +0000 (21:50 +0800)]
pinctrl: rockchip: Split the common set_mux() into per Soc
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
David Wu [Tue, 16 Apr 2019 13:50:54 +0000 (21:50 +0800)]
pinctrl: rockchip: Remove redundant spaces
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
David Wu [Tue, 16 Apr 2019 13:50:53 +0000 (21:50 +0800)]
pinctrl: rockchip: Add pull-pin-default param and remove unused param
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 7 May 2019 01:36:32 +0000 (09:36 +0800)]
Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl"
This reverts commit
502980914b2d6f9ee85a823aa3ef9ead76c0b7f2.
This is a superseded version, revert this to apply new patch set.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Simon Glass [Sat, 27 Apr 2019 01:03:39 +0000 (19:03 -0600)]
rockchip: chromebook_minnie: Enable sound
Enable sound for this board, which has the same codec as jerry.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 9 Nov 2018 03:21:38 +0000 (11:21 +0800)]
rockchip: rk3399: update defconfig for TPL
The SPL is now running at SDRAM, and 0x10000 is used by BL31,
and the ARM SPL do not support relocate now, we need reserved
0x50000 so that it won't overwrite the code when we load the
bl31 to target space.
We should remove this after we enable the relocate feature.
The SPL need malloc 0x9000 for MMC as buffer used for transfer
data to IRAM(The EMMC DMA can not transfer data to IRAM directly).
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 1 Apr 2019 09:20:53 +0000 (17:20 +0800)]
rockchip: ram: rk3399: update for TPL
Init the ddr sdram in TPL instead of SPL, update the code.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Kever Yang [Fri, 9 Nov 2018 03:18:15 +0000 (11:18 +0800)]
rockchip: rk3399: add tpl support
Rockchip platform suppose to use TPL(run in SRAM) as dram init and
SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be
limited by SRAM size.
This patch add rk3399-board-tpl.c and its common configs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 1 Apr 2019 09:15:53 +0000 (17:15 +0800)]
rockchip: add u-boot-tpl-v8.lds
We don't have both sram and sdram in TPL, so update from:
arch/arm/cpu/armv8/u-boot-spl.lds
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 29 Mar 2019 14:48:31 +0000 (22:48 +0800)]
rockchip: px5: add timer0 dts node as tick timer
Let's use rockchip timer before stimer patches can be merged.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 29 Mar 2019 14:48:30 +0000 (22:48 +0800)]
rockchip: rk3368: remove uart iomux init in SPL
The iomux should have been set in board_debug_uart_init(),
do not set in board_init_f(), remove it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 29 Mar 2019 14:48:29 +0000 (22:48 +0800)]
rockchip: dmc: rk3368: update rank number for evb-px5
evb-px5 has only 1 CS, update for it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Kever Yang [Fri, 29 Mar 2019 14:48:28 +0000 (22:48 +0800)]
rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add
condition to limit it not affect TPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 12 Feb 2019 07:19:07 +0000 (15:19 +0800)]
rockchip: px5: update defconfig for TPL/SPL
Add options to support TPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 29 Mar 2019 14:48:26 +0000 (22:48 +0800)]
rockchip: px5: update SPL size for spl/tpl
Use larger space for load bl31 in SPL
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Kever Yang [Fri, 29 Mar 2019 14:48:25 +0000 (22:48 +0800)]
rockchip: px5 update dts for spl/tpl
TPL need dmc to init ddr sdram, and emmc, boot-order.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Kever Yang [Fri, 29 Mar 2019 14:48:24 +0000 (22:48 +0800)]
rockchip: rk3368: support UART2/4 in board_debug_uart_init()
evb-rk3368 is using UART2 and PX5 evb is using UART4
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Kever Yang [Wed, 6 Sep 2017 01:33:22 +0000 (09:33 +0800)]
rockchip: evb-rk322x: update defconfig with tpl and optee support
Enable all the options for TPL/SPL and OPTEE.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:28 +0000 (20:41 +0800)]
rockchip: evb-rk3229: add README file for OP-TEE support
Detail of step by step to bring up the board with OP-TEE support.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:27 +0000 (20:41 +0800)]
rockchip: evb-rk3229: remove unnecessary defines
Prefer to use default setting like other SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:26 +0000 (20:41 +0800)]
rockchip: rk322x: dts: enable uart2 for SPL/TPL
When we use DM_SERIAL for serial driver, we need enable the
dts node for the debug console.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:25 +0000 (20:41 +0800)]
sysreset: enable driver support in SPL/TPL
SPL/TPL also need use sysreset for some feature like panic callback.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:24 +0000 (20:41 +0800)]
rockchip: rk322x: add tpl support
Move original spl to tpl, and add spl to load next stage firmware,
adapt all the address and option for them.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:23 +0000 (20:41 +0800)]
rockchip: clk: rk322x: fix assert clock value
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:22 +0000 (20:41 +0800)]
rockchip: rk322x: add CLK_EMMC_SAMPLE clock support
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:21 +0000 (20:41 +0800)]
arm: add a separate stack for TPL
TPL stack may different from SPL and sys stack, add support for
separate one when the board defines it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:20 +0000 (20:41 +0800)]
arm: add option for TPL support in arm 32bit
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY
and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 2 Apr 2019 12:41:19 +0000 (20:41 +0800)]
Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"
This reverts commit
f338cca1d2bce906b049722d2fdbf527a4963b61.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 6 May 2019 03:21:13 +0000 (11:21 +0800)]
arm: remove ARCH_ROCKCHIP macro in common code
This is fix to:
e2a12f590d rockchip: use 'arch-rockchip' as header file path
The V2 of origin patch set has fix this, but we merge V1 by
mistake, so lets correct it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 6 May 2019 03:21:12 +0000 (11:21 +0800)]
rockchip: add common header boot0.h and gpio.h for soc
boot0.h and gpio.h will be used by system and include by
'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 8 May 2019 03:41:16 +0000 (21:41 -0600)]
x86: samus: Add a target to boot through TPL
Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 May 2019 03:41:14 +0000 (21:41 -0600)]
x86: samus: Update device tree for verified boot
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 May 2019 03:41:13 +0000 (21:41 -0600)]
x86: samus: Update device tree for SPL
Add tags to allow required nodes to be present in SPL / TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:12 +0000 (10:52 -0600)]
x86: Add a simple TPL implementation
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:27 +0000 (10:52 -0600)]
x86: Add a way to jump from TPL to SPL
When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:22 +0000 (10:52 -0600)]
x86: samus: Increase the pre-reloc memory again
This is again too small, so increase it slightly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:26 +0000 (10:52 -0600)]
x86: broadwell: Update PCH to work in TPL
The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:24 +0000 (10:52 -0600)]
x86: Enable the RTC on all boards
With the move to Kconfig this option should be set in Kconfig, not in the
config header file. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:21 +0000 (10:52 -0600)]
x86: Fix device-tree indentation
With the use of a phandle we can outdent the device tree nodes a little.
Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:20 +0000 (10:52 -0600)]
x86: Update device tree for Chromium OS verified boot
The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:19 +0000 (10:52 -0600)]
x86: Update device tree for TPL
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:16 +0000 (10:52 -0600)]
x86: Add documentation on the samus flashmap
There are quite a few variables which control where things appear in the
final ROM image. Add a flashmap in the documentation to make this easier
to figure out.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed "x86: Update the memory map a little" in]
[bmeng: fixed typo of 'documentation' in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:08 +0000 (21:59 -0600)]
x86: Support PCI VGA ROM when TPL is used
When TPL is in use, U-Boot proper should support initing the VGA ROM even
though the 32-bit init portion is in SPL. Update the condition to handle
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:07 +0000 (21:59 -0600)]
x86: Don't generate a bootstage report in SPL
This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:06 +0000 (21:59 -0600)]
x86: Don't set up MTRRs in SPL
The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:05 +0000 (21:59 -0600)]
x86: Support TPL in Intel common code
Update the Makefie rules to ensure that the correct files are built when
TPL is being used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:15 +0000 (10:52 -0600)]
x86: sysreset: Implement the get_last() method
Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:14 +0000 (10:52 -0600)]
x86: sysreset: Implement power-off if available
On modern x86 devices we can power the system off using the power-
management features of the PCH. Add an implementation for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:13 +0000 (10:52 -0600)]
x86: sysreset: Separate out the EFI code
The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.
Separate out the implementation to improve the situation enough to allow
a future patch to add new sysreset features.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:03 +0000 (21:59 -0600)]
x86: broadwell: Implement PCH_REQ_PMBASE_INFO
Implement this ioctl() to support power off.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:02 +0000 (21:59 -0600)]
x86: ivybridge: Implement PCH_REQ_PMBASE_INFO
Implement this ioctl() to support power off.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:01 +0000 (21:59 -0600)]
x86: pch: Add an ioctl to read power-management info
Add a new ioctl() request to read information about the power-management
system. This can be used to power off the device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:59 +0000 (21:58 -0600)]
x86: mrccache: Add more debugging
When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:57 +0000 (21:58 -0600)]
x86: Support saving MRC data from SPL
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:56 +0000 (21:58 -0600)]
x86: Add common Intel code for SPL
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:55 +0000 (21:58 -0600)]
x86: broadwell: Select refcode and CPU code for SPL
Allow broadwell to build for SPL and include the reference code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:54 +0000 (21:58 -0600)]
x86: broadwell: Allow booting from SPL
At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:53 +0000 (21:58 -0600)]
x86: Allow 16-bit init to be in TPL
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:52 +0000 (21:58 -0600)]
x86: Add support for starting from SPL/TPL
When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.
Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:51 +0000 (21:58 -0600)]
x86: broadwell: Split CPU init
Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:50 +0000 (21:58 -0600)]
x86: broadwell: Move init of debug UART to cpu.c
At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:49 +0000 (21:58 -0600)]
x86: broadwell: Allow SDRAM init from SPL
At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.
Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:48 +0000 (21:58 -0600)]
x86: broadwell: Improve SDRAM debugging output
Add debugging during SDRAM init so that problems are easier to
diagnose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:47 +0000 (21:58 -0600)]
x86: Add a handoff header file
Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:46 +0000 (21:58 -0600)]
x86: Support booting with TPL
Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.
Add a new Kconfig option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:45 +0000 (21:58 -0600)]
x86: Support SPL and TPL
At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.
Enable the options for both along with some suitable default options
needed to boot through these phases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:43 +0000 (21:58 -0600)]
x86: dts: Add device-tree labels for rtc and reset
Add labels for these nodes so that board DT files can reference them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:42 +0000 (21:58 -0600)]
x86: Add a way to reinit the cpu
We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:41 +0000 (21:58 -0600)]
x86: mp_init: Use proper error numbers
At present many of the functions in this file return -1 as an error
number. which is -EPERM. Update the code to use real error numbers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:44 +0000 (21:58 -0600)]
x86: Update a stale comment about ifdtool
We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:40 +0000 (21:58 -0600)]
x86: start64: Fix copyright message
There is a typo in this header. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 May 2019 03:41:15 +0000 (21:41 -0600)]
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
This reverts commit
aec4298ccb337106fd0115b91d846a022fdf301d.
Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.
The offending line is in UCLASS_DRIVER(pci):
.per_device_auto_alloc_size = sizeof(struct pci_controller),
This means that all PCI devices have the controller struct associated
with them. The solution is to move the regions[] member out of the array,
makes its size dynamic, or split UCLASS_PCI into controllers and
non-controllers, as the comment suggests.
For now, revert the commit to get things running again.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:11 +0000 (10:52 -0600)]
cros_ec: Use a hyphen in the uclass name
Device-tree rules require that aliases use a hyphen rather than a
underscore. Update the uclass name to fit with this.
This allows device-tree aliases to be used to refer to cros-ec devices,
for example:
aliases {
cros-ec0 = &ec;
cros-ec1 = &pd;
};
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:38 +0000 (21:58 -0600)]
spl: Allow sandbox to build a device-tree file
At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.
Note that the new logic is not quite the same as the old logic. It was
previously assumed that checking for:
$(CONFIG_$(SPL_TPL_)OF_CONTROL)
$(CONFIG_OF_SEPARATE)
$(CONFIG_$(SPL_TPL_)OF_PLATDATA)
producing 'yy' meant that the first two were 'y' and the last was empty.
Strictly speaking it would be possible for any two of the three to be 'y'
and still yield the same result. However, that was not the intention of
the new logic, since OF_PLATDATA always ensures that no device-tree file
is included. So in effect the new logic is the same, with the addition of
OF_HOSTFILE as an option for OP_SEPARATE.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:36 +0000 (21:58 -0600)]
dm: core: Fix translate condition in ofnode_get_addr_size()
Update the condition to translate only if this is enabled for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:39 +0000 (21:58 -0600)]
binman: Allow sections to have an offset
At present sections are always placed automatically. Even if an 'offset'
property is provided it is ignored. Update the logic to support an offset
for sections.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:35 +0000 (21:58 -0600)]
binman: Add a missing comment in Entry_vblock
An important property is missing. Update the entry comment to include
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:34 +0000 (21:58 -0600)]
binman: Don't show image-skip message by default
This message is not very important since it is simply indicating that the
user's instructions are being followed. Only show it when the verbosity
level is above the default.
Also drop the unnecessary extra newline on this message, which causes two
line breaks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:33 +0000 (21:58 -0600)]
binman: Don't generate an error in 'text' entry constructor
It is not good practice to raise an exception in a constructor. In this
case the 'text' entry may not actually be used, if -i is used to filter
out the images that get built.
Move the exception to where the data is actually used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Carlo Caione [Thu, 24 Jan 2019 08:54:37 +0000 (08:54 +0000)]
net: phy: realtek: Introduce quirk to mark RXC not stoppable
When EEE is supported by the PHY and the driver allows it, libphy in the
kernel is configuring the PHY to stop receiving the xMII clock while it
is signaling LPI. While this (usually) works fine in the kernel this is
causing issues in U-Boot when rebooting from the linux kernel with this
bit set (without having the possibility to reset the PHY) where the PHY
suddenly stops working.
A new quirk is introduced to unconditionally reset this bit. If the
quirk is not enabled using the proper configuration symbol, the PHY state
is not changed.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:08 +0000 (17:25 +0000)]
cmd: mdio: Switch to generic helpers when accessing the registers
Switch to use the generic helpers to access the MMD registers so that we
can used the same command also for C45 PHYs, C22 PHYs with direct and
indirect access and PHYs implementing a custom way to access the
registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:07 +0000 (17:25 +0000)]
net: phy: ti: use generic helpers to access MMD registers
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:06 +0000 (17:25 +0000)]
net: phy: Add generic helpers to access MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Heinrich Schuchardt [Sun, 5 May 2019 19:58:35 +0000 (21:58 +0200)]
efi_loader: signature of ExitBootServices()
Consistently use efi_uintn_t as type of memory keys.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <graf@amazon.com>
Heinrich Schuchardt [Sun, 5 May 2019 14:55:06 +0000 (16:55 +0200)]
efi_loader: LoadImage() check source size
If the size of the source buffer is 0, return EFI_LOAD_ERROR.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.6)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 5 May 2019 14:55:06 +0000 (16:55 +0200)]
efi_loader: LoadImage() check parent image
If the parent image handle does not refer to a loaded image return
EFI_INVALID_PARAMETER.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.1)
Mark our root node as a loaded image to avoid an error when using it as
parent image.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 5 May 2019 09:24:53 +0000 (11:24 +0200)]
efi_loader: HandleProtocol parameter checks
HandleProtocol() and OpenProtocol() have to return EFI_UNSUPPORTED if the
protocol is not installed on the handle.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 5 May 2019 09:56:23 +0000 (11:56 +0200)]
efi_loader: use EFI_PRINT instead of debug
For correct indentation of messages in the UEFI API implementation use
EFI_PRINT() instead of debug().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 5 May 2019 08:37:51 +0000 (10:37 +0200)]
efi_loader: CloseProtocol() requires valid agent handle
Return EFI_INVALID_PARAMETER from CloseProtcol() if the agent handle is not
valid.
Return EFI_INVALID_PARAMETER if the optional controller handle is not
valid.
Return immediately from efi_search_obj if the handle is NULL.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sat, 4 May 2019 20:44:13 +0000 (22:44 +0200)]
efi_selftest: unit test for RegisterProtocolNotify()
Provide a unit test for the RegisterProtocolNotify() boot service.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sat, 4 May 2019 15:27:54 +0000 (17:27 +0200)]
efi_loader: implement RegisterProtocolNotify()
The RegisterProtocolNotify() boot service registers an event to be
notified upon the installation of a protocol interface with the
specified GUID.
Add the missing implementation.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sat, 4 May 2019 22:07:34 +0000 (00:07 +0200)]
efi_loader: EVT_NOTIFY_SIGNAL events
The notification function of events of type EVT_NOTIFY_SIGNAL should always
be queued when SignalEvent() is called.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sat, 4 May 2019 17:48:38 +0000 (19:48 +0200)]
efi_selftest: remove redundant function efi_st_memcmp()
Function memcmp() is available in efi_freestanding.c. So we do not remove a
further implementation.
Replace all usages of efi_st_memcmp() by memcmp().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 May 2019 18:07:04 +0000 (20:07 +0200)]
efi_loader: unload applications upon Exit()
Implement unloading of images in the Exit() boot services:
* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 May 2019 16:25:45 +0000 (18:25 +0200)]
efi_loader: implement UnloadImage()
Implement the UnloadImage() boot service
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 May 2019 17:04:32 +0000 (19:04 +0200)]
efi_loader: move efi_unload_image() down in source
Move efi_unload_image() down in source to avoid forward declaration in
follwing page.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 May 2019 12:20:18 +0000 (14:20 +0200)]
efi_loader: mark started images
In UnloadImage() we need to know if an image is already started.
Add a field to the handle structure identifying loaded and started images.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sat, 4 May 2019 15:37:32 +0000 (17:37 +0200)]
efi_loader: correct parameter check in LocateHandle()
If LocateHandle() does not find an entry EFI_NOT_FOUND has to be returned
even if BufferSize is NULL.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sat, 4 May 2019 08:12:50 +0000 (10:12 +0200)]
efi_loader: allowable event types in CreateEventEx()
CreateEventEx() does not allow the following event types:
* EVT_SIGNAL_EXIT_BOOT_SERVICES
* EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
This check is needed to pass the UEFI SCT conformance test.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@csgraf.de>