riscv: dts: move out AE350 L2 node from cpus node

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: cache: Flush L2 cache before jump to linux

Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: ax25: add imply v5l2 cache controller

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: ae350: use the v5l2 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: cache: add v5l2 cache controller driver

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: cache: Add enable and disable ops for sandbox and test

Add cache enable and disable ops for test coverage.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: cache: Add enable and disable ops for cache uclass

Add cache enable/disable ops to the DM cache uclass driver

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: andes_plic: init plic by scanning each cpu node

Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().

This way can support to skip some harts which maybe marked as
unavailable, but the cpu node exists indeed.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: update fix_rela_dyn

The addend is now added for RELOC_TYPE relocs.  Also, changed the loop
structure so that all the R_RISCV_RELATIVE relocs are not required to
be at the beginning of the list.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>

riscv: tools: Handle addend to absolute reloc in prelink-riscv

Previously the handling of R_RISCV_32 and R_RISCV_64 would simply
insert the value of the symbol and ignore any addend.  However, there
exist relocs where the addend is non-zero:

0000000080250900 R_RISCV_64        efi_runtime_services+0x0000000000000068
0000000080250910 R_RISCV_64        efi_runtime_services+0x0000000000000038
0000000080250920 R_RISCV_64        efi_runtime_services+0x0000000000000018
0000000080250930 R_RISCV_64        efi_runtime_services+0x0000000000000020
0000000080250980 R_RISCV_64        efi_runtime_services+0x0000000000000048
0000000080250990 R_RISCV_64        efi_runtime_services+0x0000000000000050
00000000802509a0 R_RISCV_64        efi_runtime_services+0x0000000000000058
0000000080250940 R_RISCV_64        systab+0x0000000000000030
0000000080250950 R_RISCV_64        systab+0x0000000000000040
0000000080250960 R_RISCV_64        systab+0x0000000000000050
0000000080250970 R_RISCV_64        systab+0x0000000000000060

In these cases the addend needs to be added to the symbol value to get
the correct value for the reloc.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>

sifive-fu540: config: Add mmc0 as a boot target device

Add the mmc0 device as a BOOT_TARGET_DEVICES.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: sifive: fu540: set serial environment variable from otp

This patch sets the serial# environment variable by reading the
board serial number from the OTP memory region.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

riscv: cpu: Skip unavailable hart in the get_count() op

We should not count in hart that is marked as not available in the
device tree in riscv_cpu_get_count().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

Merge branch 'master' of git://git.denx.de/u-boot-sh

- r8a66597 usb changes

Merge branch '2019-08-30-master-imports'

- Assorted bug fixes

Makefile: fix newline escaping for CONFIG_DEFAULT_ENV_FILE

I wanted this to be compatible with mkenvimage, including the ability
to embed newlines in variables by escaping them. But I failed to check
that it works more than once.

Fixes: f3d8f7dd73a (Allow providing default environment from file)
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>

Revert "vexpress64: fvp dram: add DRAM configuration"

This reverts commit fc04b923541d984b1544056fd3bfa8129d4e5aac where the
FVP DRAM configuration was added.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>

siemens: avoid out of bound access

char num[1];
sprintf(num, "%d", i);

leads to a buffer overrun.

Simplify the overly complex coding.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>

arm: omap2: am43xx: Enable CONFIG_DM_USB

Enable CONFIG_DM_USB to remove compile warning for
am43xx based targets:

===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>

Makefile: clean build generated SPL binary for TI AM65x

TI AM65x platforms (evm and HS) generate an SPL image
'tispl.bin*' and there is no rule for cleanup.
Added entry for cleanup in clean target.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>

configs: enable CONFIG_BLOCK_CACHE for mt7623n_bpir2

This patch enables CONFIG_BLOCK_CACHE for mt7623n_bpir2.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

mmc: invalidate block cache after hwpart switched successfully

eMMC device has multiple hw partitions both address from zero. However the
mmc driver lacks block cache invalidation for switch hwpart. This causes a
problem that data of current hw partition is cached before switching to
another hw partition. And the following read operation of the latter hw
partition will get wrong data when reading from the addresses that have
been cached previously.

To solve this problem, invalidate block cache after a successful
mmc_switch_part() operation.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Felix Brack <fb@ltec.ch>

Revert "blk: Invalidate block cache when switching hwpart"

This reverts commit 0ebe112d09b48230ba4be833cd3504b06997d9a4.

Most block devices have only one hwpart. Multiple hwparts only found used
by eMMC devices in u-boot. The mmc driver do blk_dselect_hwpart() at the
beginning of mmc_bread() which causes block cache being invalidated too
frequently and makes block cache useless.

So it's not a good idea to put blkcache_invalidate() in the common
functions. It should be called inside mmc_select_hwpart().

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Felix Brack <fb@ltec.ch>

board_f: fix noncached reservation calculation

The current code in reserve_noncached() has two issues:

1) The first update of gd->start_addr_sp always rounds down to a section
start. However, the equivalent calculation in cache.c:noncached_init()
always first rounds up to a section start, then subtracts a section size.
These two calculations differ if the initial value is already rounded to
section alignment.

2) The second update of gd->start_addr_sp subtracts exactly
CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in
cache.c:noncached_init() rounds the noncached size up to section
alignment before subtracting it. The two calculations differ if the
noncached region size is not a multiple of the MMU section size.

In practice, one/both of those issues causes a practical problem on
Jetson TX1; U-Boot triggers a synchronous abort during initialization,
likely due to overlapping use of some memory region.

This change fixes both these issues by duplicating the exact calculations
from noncached_init() into reserve_noncached().

However, this fix assumes that gd->start_addr_sp on entry to
reserve_noncached() exactly matches mem_malloc_start on entry to
noncached_init(). I haven't traced the code to see whether it absolutely
guarantees this in all (or indeed any!) cases. Consequently, I added some
comments in the hope that this condition will continue to be true.

Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area")
Cc: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

Merge tag 'efi-2019-10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for v2019.10-rc4

Enable the unit test for UEFI runtime service Exit() on x86_64.
Use as standalone UEFI binary for testing the handling of exceptions.

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB,
P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS

Merge tag 'u-boot-amlogic-20190828' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- add missing g12b clock driver compatible, fixing odroid-n2 usb support

efi_selftest: use standalone UEFI program for exception

To fully demonstrate crash outputs for UEFI images provide a standalone
UEFI application that tries to invoke an illegal opcode.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

efi_selftest: enable Exit() unit test on x86_64

Enable unit tests for StartImage() and Exit() unit tests on x86_64.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

configs: MPC8548CDS: Enable PCIe driver

Enable the DM PCIe driver in MPC8548CDS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

MPC8548: dts: Added PCIe DT node

MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add MPC8548 PCIe support

Add compatible string for MPC8548 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected

Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P5040DS: Enable PCIe driver

Enable the DM PCIe driver in P5040DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
eviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P5040: dts: Added PCIe DT nodes

P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P5040 PCIe support

Add compatible string for P5040 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P4080DS: Enable PCIe driver

Enable the DM PCIe driver in P4080DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P4080: dts: Added PCIe DT nodes

P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P4080 PCIe support

Add compatible string for P4080 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P3041DS: Enable PCIe driver

Enable the DM PCIe driver in P3041DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P3041: dts: Added PCIe DT nodes

P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P3041 PCIe support

Add compatible string for P3041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P2041RDB: Enable PCIe driver

Enable the DM PCIe driver in P2041RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P2041: dts: Added PCIe DT nodes

P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P2041 PCIe support

Add compatible string for P2041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: p_corenet: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines for P2041RDB,
P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is
 not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P2020RDB: Enable PCIe driver

Enable the DM PCIe driver in P2020RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P2020: dts: Added PCIe DT nodes

P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P1020RDB: Enable PCIe driver

Enable the DM PCIe driver in P1020RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
for P1020, P1021, P1024, P1025 and P2020 RDB boards.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P1020: dts: Added PCIe DT nodes

P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs

Add compatible string for PCIe of P1020, P1021, P1024, P1025
and P2020 SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines for P1020,
P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI
is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: T1042D4RDB: Enable PCIe driver

Enable the DM PCIe driver in T1042D4RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

t104x: dts: Added PCIe DT nodes

T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add T104x PCIe support

Add compatible string for T104x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T104xRDB: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: T1024RDB: Enable PCIe driver

Enable the DM PCIe driver in T1024RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040

Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and
the PCIE4 related macros, as there are only 3 PCIe controllers
on T102x SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

t102x: dts: Added PCIe DT nodes

T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add T102x PCIe support

Add compatible string for T102x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T102xRDB: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: T4240RDB: Enable PCIe driver

Enable the DM PCIe driver in T4240RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

t4240: dts: Added PCIe DT nodes

T4240 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add T4240 PCIe support

Add compatible string for T4240 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T4RDB: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: T2080RDB: Enable PCIe driver

Enable the DM PCIe driver in T2080RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T208xRDB: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Fix the calculation of controller index

The PCIe controller register address in CCSR is different
on various platforms, the current code erroneously use
the hardcoded address (0xffe240000) and stride (0x10000)
to calculate the controller's index.

Fix it by adding the related info to the driver data
structure.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Fix the Class Code fixup function

The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.

So add the Class Code fixup for the block revision < 3.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef

This can avoid build error:
The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only
defined on the platforms that select the CONFIG_FOO, while
it's not defined on platforms that do not select the
CONFIG_FOO.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

clk: meson-g12b: add compatible

The G12B clock controller is almost identical to the G12A and
so far the differences don't matter.  Adding the G12B compatible
makes USB work on the Odroid-N2.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Merge branch 'u-boot-stm32_20190827' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Fixes and update related to STM32MP1 platforms

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Support of device tree model for T2080RDB, T4240RDB, T1024RDB,
T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and
MPC8548CDS. Also support of  i2c dm model.

Merge tag 'for-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c

i2c bugfixes for 2019.10
- misc: i2c_eeprom: verify that the chip is functional at probe()
- i2c: mxc_i2c: Remove i2c_idle_bus from probe
- i2c-mux-gpio: Fix GPIO request flag issue

stm32mp1: update README for remoteproc support

Add information for remoteproc usage to load firmware in M4 coprocessor
on stm32mp157.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: add example files for FIT generation

Add example of its files to generate FIT to start kernel
on ev1 or dk2 board with
- only kernel and dtb = fit_copro_kernel_dtb.its
- kernel, M4 copro firmware and dtb = it_copro_kernel_dtb.its

Add extlinux example to manage config in generated FIT.

Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: Add copro image support for M4 firmware

Implements copro image loading with FIT.
Once image is loaded with remoteproc,
the M4 coprocessor is automatically started.

Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

image: add new "copro" image type

Define new image type for coprocessor images.
It is used in FIT to identify the files loaded
with remoteproc command (elf or bin).

Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

stm32mp1: Add remoteproc support for m4 coprocessor

Alignment with kernel patch proposal for binding:

[PATCH v4 0/8] stm32 m4 remoteproc on STM32MP157c
https://lkml.org/lkml/2019/5/14/159

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

misc: change RCC form MISC to NOP uclass

The RCC driver have no operation so the new NOP uclass
is more appropriate. It only used as parent for clock and reset driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: board update command stboard on misc_read result

Update management of misc_read, which now return length of data
after the commit 8729b1ae2cbd ("misc: Update read() and write()
methods to return bytes xfered")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: update sysconf_init on misc_read result

Update management of misc_read in sysconf_init, which now return
length of data after the commit 8729b1ae2cbd ("misc: Update read()
and write() methods to return bytes xfered")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: update test on misc_read result

Update the stm32mp1 baord after the commit 8729b1ae2cbd
("misc: Update read() and write() methods to return bytes xfered")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stpmic1: simplify stpmic1_sysreset_request

Retrieve parent device from dev->parent instead of
calling uclass_get_device_by_driver()

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

pmu: stpmic1: change specific NVM api to MISC

Use MISC u-class to export the NVM register (starting at 0xF8 offset)
and avoid specific API.
- SHADOW have offset < 0.
- NVM have register > 0

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

bsec: update after MISC u-class update

Since the commit 8729b1ae2cbd ("misc: Update read() and
write() methods to return bytes xfered"); The misc bsec driver
need to be adapted to reflect the number of transferred bytes.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

MAINTAINERS: update ARM STM STM32MP and STM32MP1 BOARD

Add the missing driver and files for mach-stm32mp / stm32mp1 product.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: clk: use gd to store frequency information

Use existing gd structure to store frequency information
which can be used in drivers or arch without new request.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: clk: remove debug traces

Remove many debug trace.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: Makefile cleanup

Don't compile psci for SPL build.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

stm32mp1: ram: add pattern parameter in infinite write test

Add pattern for infinite test_read and test_write, that
allow to change the pattern to test without recompilation;
default pattern is 0xA5A5AA55.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>