oweals/u-boot.git
5 years agoi2c: mux: Generate longer i2c mux name
Michal Simek [Thu, 31 Jan 2019 15:31:03 +0000 (16:31 +0100)]
i2c: mux: Generate longer i2c mux name

For !DM case busses are listed as
ZynqMP> i2c bus
Bus 0: zynq_0
Bus 1: zynq_0->PCA9544A@0x75:0
Bus 2: zynq_0->PCA9544A@0x75:1
Bus 3: zynq_0->PCA9544A@0x75:2
Bus 4: zynq_1
Bus 5: zynq_1->PCA9548@0x74:0
Bus 6: zynq_1->PCA9548@0x74:1
Bus 7: zynq_1->PCA9548@0x74:2
Bus 8: zynq_1->PCA9548@0x74:3
Bus 9: zynq_1->PCA9548@0x74:4
Bus 10: zynq_1->PCA9548@0x75:0
Bus 11: zynq_1->PCA9548@0x75:1
Bus 12: zynq_1->PCA9548@0x75:2
Bus 13: zynq_1->PCA9548@0x75:3
Bus 14: zynq_1->PCA9548@0x75:4
Bus 15: zynq_1->PCA9548@0x75:5
Bus 16: zynq_1->PCA9548@0x75:6
Bus 17: zynq_1->PCA9548@0x75:7

where is exactly describing i2c bus topology.
By moving to DM case i2c mux buses are using names from DT and because
i2c-muxes describing sub busses with the same names like i2c@0, etc it
is hard to identify which bus is where.
Linux is adding topology information to i2c-mux busses to identify them
better.
This patch is doing the same and composing bus name with topology
information.

When patch is applied with topology information on zcu102-revA.
ZynqMP> i2c bus
Bus 0: i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2: i2c@ff020000->i2c-mux@75->i2c@0
Bus 3: i2c@ff020000->i2c-mux@75->i2c@1
Bus 4: i2c@ff020000->i2c-mux@75->i2c@2
Bus 1: i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5: i2c@ff030000->i2c-mux@74->i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6: i2c@ff030000->i2c-mux@74->i2c@1
Bus 7: i2c@ff030000->i2c-mux@74->i2c@2
Bus 8: i2c@ff030000->i2c-mux@74->i2c@3
Bus 9: i2c@ff030000->i2c-mux@74->i2c@4
Bus 10: i2c@ff030000->i2c-mux@75->i2c@0
Bus 11: i2c@ff030000->i2c-mux@75->i2c@1
Bus 12: i2c@ff030000->i2c-mux@75->i2c@2
Bus 13: i2c@ff030000->i2c-mux@75->i2c@3
Bus 14: i2c@ff030000->i2c-mux@75->i2c@4
Bus 15: i2c@ff030000->i2c-mux@75->i2c@5
Bus 16: i2c@ff030000->i2c-mux@75->i2c@6
Bus 17: i2c@ff030000->i2c-mux@75->i2c@7

Behavior before the patch is applied.
ZynqMP> i2c bus
Bus 0: i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2: i2c@0
Bus 3: i2c@1
Bus 4: i2c@2
Bus 1: i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5: i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6: i2c@1
Bus 7: i2c@2
Bus 8: i2c@3
Bus 9: i2c@4
Bus 10: i2c@0
Bus 11: i2c@1
Bus 12: i2c@2
Bus 13: i2c@3
Bus 14: i2c@4
Bus 15: i2c@5
Bus 16: i2c@6
Bus 17: i2c@7

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agoi2c: Fill req_seq in i2c_post_bind()
Michal Simek [Thu, 31 Jan 2019 15:31:02 +0000 (16:31 +0100)]
i2c: Fill req_seq in i2c_post_bind()

For i2c controllers which are missing alias in DT there is no req_seq
setup. This function is setting up proper ID based on highest found
alias ID.

On zcu102 this is the behavior when patch is applied.
ZynqMP> i2c bus
Bus 0: i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2: i2c@0
Bus 3: i2c@1
Bus 4: i2c@2
Bus 1: i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5: i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6: i2c@1
Bus 7: i2c@2
Bus 8: i2c@3
Bus 9: i2c@4
Bus 10: i2c@0
Bus 11: i2c@1
Bus 12: i2c@2
Bus 13: i2c@3
Bus 14: i2c@4
Bus 15: i2c@5
Bus 16: i2c@6
Bus 17: i2c@7

Before this patch applied (controllers have -1 ID)
ZynqMP> i2c bus
Bus 0: i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus -1: i2c@0
Bus -1: i2c@1
Bus -1: i2c@2
Bus 1: i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus -1: i2c@0  (active 0)
   54: eeprom@54, offset len 1, flags 0
Bus -1: i2c@1
Bus -1: i2c@2
Bus -1: i2c@3
Bus -1: i2c@4
Bus -1: i2c@0
Bus -1: i2c@1
Bus -1: i2c@2
Bus -1: i2c@3
Bus -1: i2c@4
Bus -1: i2c@5
Bus -1: i2c@6
Bus -1: i2c@7

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agoi2c: dm: Record maximum id of devices before probing devices
Michal Simek [Thu, 31 Jan 2019 15:31:01 +0000 (16:31 +0100)]
i2c: dm: Record maximum id of devices before probing devices

There is a need to find out the first free i2c ID which can be used for
i2s buses (including i2c buses connected to i2c mux). Do it early in
init and share this variable with other i2c classes for uniq bus
identification.

add from hs:
fix build problem in i2c-uclass.c for omap devices

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agodm: core: Add tests for dev_read_alias_highest_id()
Michal Simek [Thu, 31 Jan 2019 15:31:00 +0000 (16:31 +0100)]
dm: core: Add tests for dev_read_alias_highest_id()

It is checking the highest alias ID for eth, gpio, pci, i2c and error
code on non existing alias.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agodm: core: Introduce dev_read_alias_highest_id()
Michal Simek [Thu, 31 Jan 2019 15:30:59 +0000 (16:30 +0100)]
dm: core: Introduce dev_read_alias_highest_id()

It is wrapper for calling of_alias_get_highest_id() when live tree is
enabled and fdtdec_get_alias_highest_id() if not.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agofdt: Introduce fdtdec_get_alias_highest_id()
Michal Simek [Thu, 31 Jan 2019 15:30:58 +0000 (16:30 +0100)]
fdt: Introduce fdtdec_get_alias_highest_id()

Find out the highest alias ID used for certain subsystem.
This call will be used for alocating IDs for i2c buses which are not
described in DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agodm: core: Add of_alias_get_highest_id()
Michal Simek [Thu, 31 Jan 2019 15:30:57 +0000 (16:30 +0100)]
dm: core: Add of_alias_get_highest_id()

The same functionality was added to Linux for i2c bus registration with this
commit message:

"
of: base: add function to get highest id of an alias stem

I2C supports adding adapters using either a dynamic or fixed id. The
latter is provided by aliases in the DT case. To prevent id collisions
of those two types, install this function which gives us the highest
fixed id, so we can then let the dynamically created ones come after
this highest number.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
"

Add it also to U-Boot for DM I2C support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoPrepare v2019.04-rc1 v2019.04-rc1
Tom Rini [Fri, 8 Feb 2019 02:32:19 +0000 (21:32 -0500)]
Prepare v2019.04-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoconfigs: Resync with savedefconfig
Tom Rini [Thu, 7 Feb 2019 19:53:03 +0000 (14:53 -0500)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Thu, 7 Feb 2019 19:48:56 +0000 (14:48 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

- SPI-NOR support

5 years agoMAINTAINERS: Add an entry for SPI NOR
Vignesh R [Tue, 5 Feb 2019 05:59:29 +0000 (11:29 +0530)]
MAINTAINERS: Add an entry for SPI NOR

Add myself as co-maintainer for U-Boot SPI NOR subsystem.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: drop mtd/spi file from SPI entry]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agoconfigs: Don't use SPI_FLASH_BAR as default
Vignesh R [Tue, 5 Feb 2019 05:59:28 +0000 (11:29 +0530)]
configs: Don't use SPI_FLASH_BAR as default

Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agoconfigs: Remove SF_DUAL_FLASH
Vignesh R [Tue, 5 Feb 2019 05:59:27 +0000 (11:29 +0530)]
configs: Remove SF_DUAL_FLASH

SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
enums yield no user and therefore support seems to be incomplete. Remove
these configs so as to avoid confusion.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agospl: Kconfig: Enable SPI_FLASH_TINY by default for SPL
Vignesh R [Tue, 5 Feb 2019 05:59:26 +0000 (11:29 +0530)]
spl: Kconfig: Enable SPI_FLASH_TINY by default for SPL

SPL only needs to be able to read from SPI Flash to load next stage and
does not really need write/erase etc. Therefore in order to reduce SPI
Flash code size in SPL, enable SPI_FLASH_TINY, that only supports
reading from SPI flash, as default.

Note: Since, SPI_FLASH_TINY does not support SPI_FLASH_BAR,
SPI_FLASH_TINY is not enabled for boards with SPI controllers that
cannot support 4 byte addressing.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: Add lightweight SPI flash stack for SPL
Vignesh R [Tue, 5 Feb 2019 05:59:25 +0000 (11:29 +0530)]
mtd: spi: Add lightweight SPI flash stack for SPL

Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.

Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: Remove unused files
Vignesh R [Tue, 5 Feb 2019 05:59:24 +0000 (11:29 +0530)]
mtd: spi: Remove unused files

spi_flash and spi_flash_ids are no longer needed after SPI NOR
migration. Remove them.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: Switch to new SPI NOR framework
Vignesh R [Tue, 5 Feb 2019 05:59:23 +0000 (11:29 +0530)]
mtd: spi: Switch to new SPI NOR framework

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: sf_probe: Add "jedec, spi-nor" compatible string
Vignesh R [Tue, 5 Feb 2019 05:59:22 +0000 (11:29 +0530)]
mtd: spi: sf_probe: Add "jedec, spi-nor" compatible string

Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible
SPI Flash device nodes. Therefore make U-Boot also to look for the same
compatible string so that we can use Linux DTS files as is.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: spi-nor-core: Add back U-Boot specific features
Vignesh R [Tue, 5 Feb 2019 05:59:21 +0000 (11:29 +0530)]
mtd: spi: spi-nor-core: Add back U-Boot specific features

For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: spi-nor-core: Add SFDP support
Vignesh R [Tue, 5 Feb 2019 05:59:20 +0000 (11:29 +0530)]
mtd: spi: spi-nor-core: Add SFDP support

Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: spi-nor-core: Add 4 Byte addressing support
Vignesh R [Tue, 5 Feb 2019 05:59:19 +0000 (11:29 +0530)]
mtd: spi: spi-nor-core: Add 4 Byte addressing support

Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: spi-nor-core: Add SPI MEM support
Vignesh R [Tue, 5 Feb 2019 05:59:18 +0000 (11:29 +0530)]
mtd: spi: spi-nor-core: Add SPI MEM support

Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agomtd: spi: Port SPI NOR framework from Linux
Vignesh R [Tue, 5 Feb 2019 05:59:17 +0000 (11:29 +0530)]
mtd: spi: Port SPI NOR framework from Linux

Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agosh: bitops: add hweight*() macros
Vignesh R [Tue, 5 Feb 2019 05:59:16 +0000 (11:29 +0530)]
sh: bitops: add hweight*() macros

Add hweight*() macros required for moving to new SF layer

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
5 years agospi: Add non DM version of SPI_MEM
Vignesh R [Tue, 5 Feb 2019 05:59:15 +0000 (11:29 +0530)]
spi: Add non DM version of SPI_MEM

Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agospi: spi-mem: Claim SPI bus before spi mem access
Vignesh R [Tue, 5 Feb 2019 05:59:14 +0000 (11:29 +0530)]
spi: spi-mem: Claim SPI bus before spi mem access

It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agospi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size
Vignesh R [Tue, 5 Feb 2019 05:59:13 +0000 (11:29 +0530)]
spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size

Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agospi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes
Vignesh R [Tue, 5 Feb 2019 05:59:12 +0000 (11:29 +0530)]
spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes

SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agobitops: Fix GENMASK definition for Sandbox
Vignesh R [Tue, 5 Feb 2019 05:59:11 +0000 (11:29 +0530)]
bitops: Fix GENMASK definition for Sandbox

In arch/sandbox/include/asm/types.h we have
Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as
CONFIG_PHYS64 is not set

This messes up the current logic of GENMASK macro due to mismatch b/w
size of unsigned long (64 bit) and that of BITS_PER_LONG.
Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32
based on the host machine on which its being compiled.

Without this patch:
GENMASK(14,0) => 0x7fffffffffff
After this patch:
GENMASK(14,0) => 0x7fff

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoconfigs: Move CONFIG_SPI_FLASH into defconfigs
Vignesh R [Tue, 5 Feb 2019 05:59:10 +0000 (11:29 +0530)]
configs: Move CONFIG_SPI_FLASH into defconfigs

Completely move CONFIG_SPI_FLASH from remaining board header files to
defconfigs

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
5 years agoarm: dts: am33xx: introduce 'am33xx-u-boot.dtsi'
Hannes Schmelzer [Wed, 6 Feb 2019 11:49:50 +0000 (12:49 +0100)]
arm: dts: am33xx: introduce 'am33xx-u-boot.dtsi'

commit fdce9d35dc36 ("arm: dts: am33xx: Sync dts with Linux 4.20.0")
did remove the "u-boot,dm-spl" flag from the 'ocp' bus which was
introduced with
commit 19aa4ac09db9 ("dts: am33xx: add u-boot, dm-spl to ocp bus")

Due to this all boards having CONFIG_SPL_OF_CONTROL enabled are broken
because they cannot bind/probe the boot-media interface during SPL
stage.

This commit introduces the 'am33xx-u-boot.dtsi' which is included with
the auto include mechanism. The am33xx-u-boot-dtsi adds the important
"u-boot,dm-pre-reloc" to the 'ocp bus' (the root bus of almost all
peripherals, at least the bootable ones).

The peripherials (mmc, spi, ...) needed during SPL stage need to be
equipped with the 'u-boot,dm-pre-reloc' in their responsible dts file.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
5 years agoMAINTAINERS: update u-boot-atmel tree
Eugen Hristev [Tue, 5 Feb 2019 10:20:39 +0000 (10:20 +0000)]
MAINTAINERS: update u-boot-atmel tree

Update Atmel AT91 maintainership

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
5 years agoMAINTAINERS: Change fsl-qoriq, mpc85xx, mpc86xx maintainers
York Sun [Mon, 4 Feb 2019 16:22:58 +0000 (08:22 -0800)]
MAINTAINERS: Change fsl-qoriq, mpc85xx, mpc86xx maintainers

Change maintainers to Prabhakar Kushwaha for fsl-qoriq, mpc85xx
and mpc86xx.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Tue, 5 Feb 2019 13:37:21 +0000 (08:37 -0500)]
Merge git://git.denx.de/u-boot-marvell

- Move Armada XP / 38x PCIe driver to DM_PCI from me
- Move Armada XP / 38x LCD driver to DM_VIDEO from me
- Add uDPU board (Armada-3720) from Vladimir

[trini: Fix warning in pci-uclass.c by removing ret from
pci_uclass_child_post_bind as it no longer calls functions with
        a return code to catch.]
Signed-off-by: Tom Rini <trini@konsulko.com>II
5 years agoMerge tag 'for-master-20190205' of git://git.denx.de/u-boot-rockchip
Tom Rini [Tue, 5 Feb 2019 13:32:52 +0000 (08:32 -0500)]
Merge tag 'for-master-20190205' of git://git.denx.de/u-boot-rockchip

Removes artifacts (.rej-files) from the last merge.

5 years agoarm: mvebu: theadorable: Enable video / LCD support with the new DM driver
Stefan Roese [Wed, 30 Jan 2019 07:54:13 +0000 (08:54 +0100)]
arm: mvebu: theadorable: Enable video / LCD support with the new DM driver

With the new DM_VIDEO support in the Armada XP LCD driver, this patch
adds the needed DT node for the LCD controller to the theadorable dts
file. This DT property is not added to the Armada XP dtsi files, as this
LCD feature is pretty unusual for this SoC and I personally know of no
other board that uses this controller.

This patch also enables CONFIG_BMP_16BPP/24BPP/32BPP, as the "old" bmp
command supported these BMP files.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
5 years agovideo: Armada XP: Move driver to DM_VIDEO
Stefan Roese [Wed, 30 Jan 2019 07:54:11 +0000 (08:54 +0100)]
video: Armada XP: Move driver to DM_VIDEO

This patch moves the Armada XP video / LCD driver to DM_VIDEO. With this
move, the legacy interface board_video_init() is removed from the
theadorable board code (only user of this video driver). The support
via DT will be added in a separate patch.

This patch also enables DM_VIDEO for the theadorable board, as this is
needed to not break git bisect'ability.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
5 years agoarm64: mvebu: Add basic support for uDPU board
Vladimir Vid [Mon, 28 Jan 2019 16:27:58 +0000 (17:27 +0100)]
arm64: mvebu: Add basic support for uDPU board

This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC.
micro-DPU is the single-port FTTdp "distribution point unit" made by Methode Electronics
which offers complete modularity with replaceable SFP modules both for uplink and downlink
(G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable).

On-board features:
- 512 MiB DDR3
- 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC
- USB 2.0 Type-C connector
- 4GB eMMC
- ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type)

Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Luis Torres <luis.torres@methode.com>
Cc: Scott Roberts <scott.roberts@telus.com>
Cc: Paul Arola <paul.arola@telus.com>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: armada-xp-theadorable.dts: Enable PCIe DT nodes
Stefan Roese [Fri, 25 Jan 2019 10:52:45 +0000 (11:52 +0100)]
arm: mvebu: armada-xp-theadorable.dts: Enable PCIe DT nodes

Now that the PCIe driver supports DM and DT parsing, enable the PCIe DT
nodes that are used by this board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
5 years agoarm: mvebu: armada-xp/37x.dtsi: Sync PCIe DT nodes with Linux v4.20
Stefan Roese [Fri, 25 Jan 2019 10:52:44 +0000 (11:52 +0100)]
arm: mvebu: armada-xp/37x.dtsi: Sync PCIe DT nodes with Linux v4.20

This patch sync's the PCIe DT nodes with the recent Linux v4.20 version.
This change makes it easier to reference specific PCIe nodes in the
board dts files to e.g. enable a PCIe port as this is now necessary with
the new DM PCI driver for these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
5 years agopci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
Stefan Roese [Fri, 25 Jan 2019 10:52:43 +0000 (11:52 +0100)]
pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig

This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.

To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
5 years agopci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr
Stefan Roese [Fri, 25 Jan 2019 10:52:42 +0000 (11:52 +0100)]
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr

This function will be used by the Marvell Armada XP/38x PCIe driver,
which is moved to DM right now. So let's extract the functionality
from pci_uclass_child_post_bind() to make it available.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agorockchip: Remove rejected files with .rej suffix
Michal Simek [Tue, 5 Feb 2019 09:29:12 +0000 (10:29 +0100)]
rockchip: Remove rejected files with .rej suffix

Probably output of incorrect applying introduced by

"rockchip: defconfig: Clean the unused pinctrl config"
(sha1: 2ec3d25f8faab51c2334174a582a96ad28d96344)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agoMerge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip
Tom Rini [Sat, 2 Feb 2019 15:11:20 +0000 (10:11 -0500)]
Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip

u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs

5 years agoMerge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mips
Tom Rini [Sat, 2 Feb 2019 15:11:12 +0000 (10:11 -0500)]
Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mips

- MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
- MIPS: mt76xx: fix timer frequency

5 years agoMerge branch '2019-02-01-master-imports'
Tom Rini [Sat, 2 Feb 2019 15:08:50 +0000 (10:08 -0500)]
Merge branch '2019-02-01-master-imports'

- Various TI platforms have been updated and DTS files re-synced and
  options disabled if not used or migrated to the DM versions
- Improvements to the dumpimage tool
- Rename SPL FAT/EXT filesystem support symbols for consistency and then
  allow them to be used to save more space in SPL.
- More lmb fixes
- Partial migration of CONFIG_BUILD_TARGET

5 years agoKconfig: set default BUILD_TARGET for kirkwood
Chris Packham [Fri, 18 Jan 2019 07:46:43 +0000 (20:46 +1300)]
Kconfig: set default BUILD_TARGET for kirkwood

Now that BUILD_TARGET is in Kconfig we can define a default for boards
using the Kirkwood SoC.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
5 years agoKconfig: Migrate CONFIG_BUILD_TARGET
Jagan Teki [Fri, 18 Jan 2019 07:22:49 +0000 (12:52 +0530)]
Kconfig: Migrate CONFIG_BUILD_TARGET

Migrate CONFIG_BUILD_TARGET into Kconfig.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agotest: lib: lmb: add lmb test for multiple RAM banks
Simon Goldschmidt [Fri, 1 Feb 2019 20:23:59 +0000 (21:23 +0100)]
test: lib: lmb: add lmb test for multiple RAM banks

This adds one test case that checks that allocation with multiple
DRAM banks works correctly.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agolmb: handle more than one DRAM BANK
Simon Goldschmidt [Sat, 26 Jan 2019 21:13:04 +0000 (22:13 +0100)]
lmb: handle more than one DRAM BANK

This fixes the automatic lmb initialization and reservation for boards
with more than one DRAM bank.

This fixes the CVE-2018-18439 and -18440 fixes that only allowed to load
files into the firs DRAM bank from fs and via tftp.

Found-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agotools: dumpimage: Clarify help
Martyn Welch [Sat, 26 Jan 2019 02:31:54 +0000 (02:31 +0000)]
tools: dumpimage: Clarify help

Help message isn't clear over the use of the "-T" option (it's to declare
the type of image that the tool is operating on), which also is optional
as it defaults to the default image type. It's also missing a description
of the "-o" option, so add it.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
5 years agotools: dumpimage: Add help option and make error paths consistent
Martyn Welch [Sat, 26 Jan 2019 02:31:53 +0000 (02:31 +0000)]
tools: dumpimage: Add help option and make error paths consistent

The utility dumpimage has error paths that display the usage and others
that exit without displaying usage. Add an explicit help option to
dumpimage to display the usage and remove it's use in error paths to make
the error messages more obvious and errors paths more consistent.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
5 years agotools: dumpimage: Simplify internal logic
Martyn Welch [Sat, 26 Jan 2019 02:31:52 +0000 (02:31 +0000)]
tools: dumpimage: Simplify internal logic

There are 3 supported modes of operation:

1) Show version
2) List image contents
3) Extract image component

Option (1) terminates early, so only options (2) and (3) remain. Remove
redundant check for these modes.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
5 years agotools: dumpimage: Simplify arguments
Martyn Welch [Sat, 26 Jan 2019 02:31:51 +0000 (02:31 +0000)]
tools: dumpimage: Simplify arguments

The dump image utility has very confusing syntax. If called to list image
contents ("-l") it takes the image name as a positional argument. If the
utility is called to extract something from the image, the image must be
provided via the optional argument "-i" as well as the positional argument
but the value passed in the positional argument will be completely
ignored.

Simplify dumpimage by always providing the image as the first positional
argument. Assume we want to dump something from the image if we do not
provide the "-l" option for now.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
5 years agotools: dumpimage: Provide more feedback on error
Martyn Welch [Sat, 26 Jan 2019 02:31:50 +0000 (02:31 +0000)]
tools: dumpimage: Provide more feedback on error

The dumpimage utility errors out in a number of places without providing
sufficient feedback to allow the user to easily determine what they have
done wrong. Add addtional error messages to make the cause of the failure
more obvious.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
5 years agoregulator: pbias: Handle extended drain IO when changing omap36 PBIAS
Adam Ford [Thu, 24 Jan 2019 20:33:36 +0000 (14:33 -0600)]
regulator: pbias: Handle extended drain IO when changing omap36 PBIAS

The OMAP36 and DM37 TRM state to disable extneded drain IO before
changing the PBIAS.  This patch does this before pmic writes if
the CONFIG_MMC_OMAP36XX_PINS flag is set and the cpu family is
omap36xx

Signed-off-by: Adam Ford <aford173@gmail.com>
5 years agorockchip: rk3399: spl: ensure that debug_uart_init is called
Philipp Tomsich [Fri, 1 Feb 2019 15:48:31 +0000 (16:48 +0100)]
rockchip: rk3399: spl: ensure that debug_uart_init is called

With the latest changes to add support for the Chromebook Bob,
initialisation through debug_uart_init() did no longer get called for
other targets.

Fix this, by moving debug_uart_init() out of the Bob-specific

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: rk3399-puma: enable SPL_ATF_NO_PLATFORM_PARAM
Philipp Tomsich [Fri, 1 Feb 2019 14:24:26 +0000 (15:24 +0100)]
rockchip: rk3399-puma: enable SPL_ATF_NO_PLATFORM_PARAM

As we're working on the next update of our ATF (and U-Boot and the ATF
are out-of-sync), let's temporarily enable SPL_ATF_NO_PLATFORM_PARAM to
reduce compatibility issues.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agopinctrl: Kconfig: fix missing include of rockchip/Kconfig
Philipp Tomsich [Fri, 1 Feb 2019 14:15:38 +0000 (15:15 +0100)]
pinctrl: Kconfig: fix missing include of rockchip/Kconfig

After the merge of the new, generic pinctrl-code, the include for
rockchip/Kconfig was missing.  Add it here, so we can select the
pinctrl-driver for SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agopinctrl: Kconfig: sort includes alphabetically
Philipp Tomsich [Fri, 1 Feb 2019 14:11:48 +0000 (15:11 +0100)]
pinctrl: Kconfig: sort includes alphabetically

To make adding new subdirectories easier, let's enforce alphabetical
ordering of the includes of Kconfig files in the respective
subdirectories.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Add MAINTAINER entry for chromebook_speedy
Philipp Tomsich [Fri, 1 Feb 2019 08:34:06 +0000 (09:34 +0100)]
rockchip: Add MAINTAINER entry for chromebook_speedy

This adds a MAINTAINER entry for chromebook_speedy.

Without this, we get the following warnings from the maintainers
check:
    WARNING: no status info for 'chromebook_minnie'
    WARNING: no maintainers for 'chromebook_minnie'

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Add support for chromebook_bob
Simon Glass [Mon, 21 Jan 2019 21:53:36 +0000 (14:53 -0700)]
rockchip: Add support for chromebook_bob

Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)

Not included:
- Keyboard
- Display
- Sound
- USB
- TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: gru: Add extra device-tree settings
Simon Glass [Mon, 21 Jan 2019 21:53:35 +0000 (14:53 -0700)]
rockchip: gru: Add extra device-tree settings

Add some U-Boot-specific settings. These should really go in the
*u-boot.dtsi file, but it seems that rk3399 does not use that yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Implement spl_gpio in the GPIO driver
Simon Glass [Mon, 21 Jan 2019 21:53:34 +0000 (14:53 -0700)]
rockchip: Implement spl_gpio in the GPIO driver

Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Move pull-up/down enum into a common file
Simon Glass [Mon, 21 Jan 2019 21:53:33 +0000 (14:53 -0700)]
rockchip: Move pull-up/down enum into a common file

At present this enum is only available to rk3288. Move it so that other
rockchip SoCs can access it. It is needed for the SPL GPIO driver for
rk3999 in a later patch.

Also adjust the enum name to lower case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set env
Simon Glass [Mon, 21 Jan 2019 21:53:32 +0000 (14:53 -0700)]
rockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set env

Some boards use different stdio environment variables from the default.
Provide a #define for this which can be set before including the header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Tidy up board include-file ordering
Simon Glass [Mon, 21 Jan 2019 21:53:31 +0000 (14:53 -0700)]
rockchip: Tidy up board include-file ordering

These board files have inconsistent #include ordering. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: clk: Add mention of four new clocks
Simon Glass [Mon, 21 Jan 2019 21:53:30 +0000 (14:53 -0700)]
rockchip: clk: Add mention of four new clocks

These clocks are needed to get MMC running. We don't actually support
setting them yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHz
Simon Glass [Mon, 21 Jan 2019 21:53:29 +0000 (14:53 -0700)]
rockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHz

This memory is used on Bob. Add settings for this, taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Allow booting from SPI
Simon Glass [Mon, 21 Jan 2019 21:53:28 +0000 (14:53 -0700)]
rockchip: Allow booting from SPI

The u-boot,spl-boot-device property only allows MMC at present. Add SPI as
well for boards that boot from SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Clarify docs on SPI writing
Simon Glass [Mon, 21 Jan 2019 21:53:27 +0000 (14:53 -0700)]
rockchip: Clarify docs on SPI writing

We use every second block when creating a SPI image, so update the text to
say this explicitly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: evb_rk3399: Tidy up the README
Simon Glass [Mon, 21 Jan 2019 21:53:26 +0000 (14:53 -0700)]
rockchip: evb_rk3399: Tidy up the README

Add mention of a prerequisite needed to build the image. Also adjust the
English wording in a few places.

Ideally this should move to using binman to produce images, and avoid the
manual steps.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Adjust rk3399 device tree to be closer to linux
Simon Glass [Mon, 21 Jan 2019 21:53:25 +0000 (14:53 -0700)]
rockchip: Adjust rk3399 device tree to be closer to linux

This file has changed upstream, with some additions and changes. Move the
U-Boot version towards this.

Some USB changes seem to be incompatible with how the bindings work on
rockchip in U-Boot. Testing is needed to make sure that USB still works
correct, and adjust the code (not device tree) if not.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Bring in device tree files for rk3399-gru
Simon Glass [Mon, 21 Jan 2019 21:53:24 +0000 (14:53 -0700)]
rockchip: Bring in device tree files for rk3399-gru

Bring in these files from Linux v4.20.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Drop note about supporting other SoCs
Simon Glass [Mon, 21 Jan 2019 21:53:23 +0000 (14:53 -0700)]
rockchip: Drop note about supporting other SoCs

Quite a wide range of Rockchip SoCs are supported in mainline U-Boot now,
so drop the comment about needing to add more.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Add mention of other boards
Simon Glass [Mon, 21 Jan 2019 21:53:22 +0000 (14:53 -0700)]
rockchip: Add mention of other boards

At present some Rockchip SoCs and boards are not mentioned in the README.
So that people can see which SoCs are supported, expand the list to
include everything.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agogpio: Add a simple GPIO API for SPL
Simon Glass [Mon, 21 Jan 2019 21:53:21 +0000 (14:53 -0700)]
gpio: Add a simple GPIO API for SPL

In space-constrained environments or before driver model is available, it
is sometimes necessary to set GPIO values. Add an SPL API for this, to
allow early board code to change GPIOs. The caller must provide the
register address, so that the drivers can be fairly generic.

This API can be implemented by GPIO drivers, behind a suitable guard,
like #ifdef CONFIG_SPL_BUILD.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agogpio: Use more command-specific enums values
Simon Glass [Mon, 21 Jan 2019 21:53:20 +0000 (14:53 -0700)]
gpio: Use more command-specific enums values

At present this file uses GPIO_OUTPUT and GPIO_INPUT as its sub-command
values. These are pretty generic names. Add a 'C' suffix to avoid possible
conflicts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agoclk: Improve debug message in clk_set_default_rates()
Simon Glass [Mon, 21 Jan 2019 21:53:19 +0000 (14:53 -0700)]
clk: Improve debug message in clk_set_default_rates()

It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agolib: Allow using display_buffer() in SPL
Simon Glass [Mon, 21 Jan 2019 21:53:18 +0000 (14:53 -0700)]
lib: Allow using display_buffer() in SPL

At present this function uses printf() format strings that are not
supported in SPL, so the output just consists of %llx strings on 64-bit.
machines. Fix this by adding a special case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agoARM: dts: rk322x: Correct the uart2 default pin configuration
David Wu [Wed, 2 Jan 2019 13:02:35 +0000 (21:02 +0800)]
ARM: dts: rk322x: Correct the uart2 default pin configuration

To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agopinctrl: rockchip: Clean the unused rockchip pinctrl drivers
David Wu [Wed, 2 Jan 2019 13:02:23 +0000 (21:02 +0800)]
pinctrl: rockchip: Clean the unused rockchip pinctrl drivers

If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: defconfig: Clean the unused pinctrl config
David Wu [Wed, 2 Jan 2019 13:01:55 +0000 (21:01 +0800)]
rockchip: defconfig: Clean the unused pinctrl config

If we used the pinctrl-rockchip driver, these config is not needed,
so remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agopinctrl: rockchip: Add common rockchip pinctrl driver
David Wu [Wed, 2 Jan 2019 13:00:55 +0000 (21:00 +0800)]
pinctrl: rockchip: Add common rockchip pinctrl driver

Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agork3288: chrome: defconfig: Enable FDT for new pinctrl driver
David Wu [Wed, 2 Jan 2019 13:00:40 +0000 (21:00 +0800)]
rk3288: chrome: defconfig: Enable FDT for new pinctrl driver

The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
and enable SPL_OF_LIBFDT to make FDT be built in.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agoARM: rockchip: Remove the pinctrl request at rk3288-board-spl
David Wu [Wed, 2 Jan 2019 12:51:00 +0000 (20:51 +0800)]
ARM: rockchip: Remove the pinctrl request at rk3288-board-spl

If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agoARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
David Wu [Wed, 2 Jan 2019 12:50:59 +0000 (20:50 +0800)]
ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188

It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agoARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
David Wu [Wed, 2 Jan 2019 12:50:58 +0000 (20:50 +0800)]
ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL

When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver
David Wu [Wed, 2 Jan 2019 12:50:57 +0000 (20:50 +0800)]
rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver

The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make FDT be built in.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: add support for veyron-speedy (ASUS Chromebook C201)
Marty E. Plummer [Sun, 6 Jan 2019 02:12:08 +0000 (20:12 -0600)]
rockchip: add support for veyron-speedy (ASUS Chromebook C201)

This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc

Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: dts: rk3399-firely: add 'same-as-spl'
Mark Kettenis [Fri, 4 Jan 2019 19:49:32 +0000 (20:49 +0100)]
rockchip: dts: rk3399-firely: add 'same-as-spl'

Like on rk3399-puma we want to continue booting the fill U-Boot from
the same device as the SPL stage.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Drop call to rockchip_dnl_mode_check() for now
Simon Glass [Sat, 29 Dec 2018 13:16:41 +0000 (06:16 -0700)]
rockchip: Drop call to rockchip_dnl_mode_check() for now

This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which do not
have this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agosound: rockchip: Add sound support for jerry
Simon Glass [Fri, 28 Dec 2018 03:15:23 +0000 (20:15 -0700)]
sound: rockchip: Add sound support for jerry

Jerry uses a max98090 audio codec and the internal SoC I2S peripheral.
Enable sound support and add the required device-tree pieces.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Add a sound driver
Simon Glass [Fri, 28 Dec 2018 03:15:22 +0000 (20:15 -0700)]
rockchip: Add a sound driver

Add a sound driver for rk3288 supporting chromebook_jerry. This uses the
I2S driver, and existing audio codec and the clock/pinmux support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: Add an I2S driver
Simon Glass [Fri, 28 Dec 2018 03:15:21 +0000 (20:15 -0700)]
rockchip: Add an I2S driver

Add a driver for I2S which allows audio data to be sent from the SoC to
the audio codec. The sample rate and other settings are hard-coded for now
as there is no suitable device-tree binding available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agorockchip: rk3288: Add i2s pinctrl and clock support
Simon Glass [Fri, 28 Dec 2018 03:15:20 +0000 (20:15 -0700)]
rockchip: rk3288: Add i2s pinctrl and clock support

Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agoARM: DTS: am43xx: Enable the DTS entries for USB port #2 in SPL
Jean-Jacques Hiblot [Thu, 24 Jan 2019 14:42:52 +0000 (15:42 +0100)]
ARM: DTS: am43xx: Enable the DTS entries for USB port #2 in SPL

This is required to enable the USB port #2 in SPL when DM_USB is used.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
5 years agoARM: DTS: am43xx: Add aliases for the USB ports
Jean-Jacques Hiblot [Thu, 24 Jan 2019 14:42:51 +0000 (15:42 +0100)]
ARM: DTS: am43xx: Add aliases for the USB ports

Although not required, it doesn't hurt to explicitly map the USB ports to
a USB controller. Without this, the port number will be derived from the
binding order of the peripheral devices.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
5 years agoARM: DTS: Resync am3517-evm.dts with Linux 5.0-rc3
Adam Ford [Wed, 23 Jan 2019 18:46:42 +0000 (12:46 -0600)]
ARM: DTS: Resync am3517-evm.dts with Linux 5.0-rc3

The chosen node was added in the kernel.  This may come in handy
in the future, so resync with 5.0-rc3

Signed-off-by: Adam Ford <aford173@gmail.com>
5 years agoARM: dts: da850-evm: Re-sync with Kernel 5.0
Adam Ford [Wed, 23 Jan 2019 18:37:57 +0000 (12:37 -0600)]
ARM: dts: da850-evm: Re-sync with Kernel 5.0

Resync with Kernel 5.0-rc3

Signed-off-by: Adam Ford <aford173@gmail.com>