Allen Martin [Fri, 31 Aug 2012 08:30:09 +0000 (08:30 +0000)]
ARM: add tegra20 support to arm720t
Add support for tegra20 arm7 boot processor. This processor is used
to power on the Cortex A9 and transfer control to it. In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical except for cache and MMU.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:08 +0000 (08:30 +0000)]
tegra20: remove timer_init from SPL build
Don't use timer_init from tegra board.c. This comes out of arm720t
for the SPL build.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:07 +0000 (08:30 +0000)]
ARM: Fix arm720t SPL build
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:06 +0000 (08:30 +0000)]
MAKEALL: update to work with new boards.cfg syntax
Update MAKEALL to handle the optional SPL CPU field that was added to
boards.cfg. This impacts the cases in MAKEALL that have to match
against CPU type (field 3). In these cases use ':' as a field
separator to split the u-boot CPU from the SPL CPU.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:05 +0000 (08:30 +0000)]
mkconfig: remove bashisms and cleanup config.mk generation
This adds some cleanup to mkconfig related to SPL support. Bash
specific script has been replaced with awk for better shell
compatibility. config.mk generation is done through a subshell and
single redirect to improve readability.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:04 +0000 (08:30 +0000)]
tegra20: make board mkdir commands unconditional
Change the mkdir commands for the object directories to be
unconditional. This fixes an issue when building for SPL where
SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:03 +0000 (08:30 +0000)]
tegra20: tec: add tegra20-common-post.h
Add tegra20-common-post.h to be consistent with other tegra20 boards.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:02 +0000 (08:30 +0000)]
tegra20: rename CONFIG_MACH_TEGRA_GENERIC
Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA.
The meaning of the config options is now:
CONFIG_TEGRA - Any tegra chip
CONFIG_TEGRA20 - A tegra20 family chip
CONFIG_TEGRA30 - A tegra30 family chip (not added yet)
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:01 +0000 (08:30 +0000)]
tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:00 +0000 (08:30 +0000)]
tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Sun, 5 Aug 2012 16:07:22 +0000 (16:07 +0000)]
ARM: add Raspberry Pi model B board, using BCM2835 SoC
The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM,
contains an SMSC 9512 USB LAN/Hub chip, and various IO connectors.
For more details, see http://www.raspberrypi.org/.
Various portions (cache enable, MACH_TYPE setup, RAM size limit, stack
relocation to top of RAM) extracted from work by:
Oleksandr Tymoshenko <gonzo@bluezbox.com>.
GPIO driver enablement by Vikram Narayanan <vikram186@gmail.com>.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Tom Rini <trini@ti.com>
Stephen Warren [Sun, 5 Aug 2012 16:07:21 +0000 (16:07 +0000)]
ARM: add basic support for the Broadcom BCM2835 SoC
This SoC is used in the Raspberry Pi, for example.
For more details, see:
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf.
Initial support is enough to boot to a serial console, execute a minimal
set of U-Boot commands, download data over a serial port, and boot a
Linux kernel. No storage or network drivers are implemented.
GPIO driver originally by Vikram Narayanan <vikram186@gmail.com>
with many fixes from myself.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 5 Aug 2012 16:07:20 +0000 (16:07 +0000)]
ARM: arm1176: enable instruction cache in arch_cpu_init()
Note that this affects all users of the ARM1176 CPU that enable
CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as
tnetv107x.
Cc: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 5 Aug 2012 16:07:19 +0000 (16:07 +0000)]
README: fix references to config_cmd_default.h
All usage of config_cmd_default.h uses <> for the include statement.
Update the README to do the same, rather than using "".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:33 +0000 (08:59 +0000)]
snowball: Adding board specific cache cleanup routine
Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:32 +0000 (08:59 +0000)]
armv7: Adding cpu specific cache managmenent
Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
John Rigby [Tue, 31 Jul 2012 08:59:31 +0000 (08:59 +0000)]
u8500: Separating mmc config parameters from driver
Configuration in vexpress and u8500.v1 is different from what
is needed in u8500.v2. As such, card configuration specifics need
to reside in the board file rather than the driver.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:30 +0000 (08:59 +0000)]
u8500: Enabling power to MMC device on AB8500 V2
Register mapping has changed on power control chip between
the first and second revision.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:29 +0000 (08:59 +0000)]
u8500: Moving processor-specific functions to cpu area.
Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tom Rini <trini@ti.com>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:28 +0000 (08:59 +0000)]
snowball: applying power to LAN and GBF controllers
LAN and GBF need to be powered explicitely, doing so with
interface to AB8500 companion chip.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:27 +0000 (08:59 +0000)]
snowball: Moving to ux500.v2 addess scheme for PRCMU access
Addresses between ux500.v1 and ux500.v2 have changed slightly,
hence mandating a review of the PRCMU access methods.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:26 +0000 (08:59 +0000)]
snowball: Adding CPU clock initialisation
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:25 +0000 (08:59 +0000)]
snowball: Adding architecture dependent initialisation
Enabling timers and clocks in PRCMU and cleaning up mailbox.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Mathieu J. Poirier [Tue, 31 Jul 2012 08:59:24 +0000 (08:59 +0000)]
u8500: Moving prcmu to cpu directory
This is to allow the prcmu functions to be used by multiple
u8500-based processors.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Mathieu J. Poirier [Fri, 3 Aug 2012 11:05:12 +0000 (11:05 +0000)]
snowball: Add support for ux500 based snowball board
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Conflicts:
drivers/gpio/Makefile
Tom Rini [Wed, 27 Jun 2012 05:27:05 +0000 (05:27 +0000)]
davinci, c6x: Always use C version of reset code
We can safely use the same reset code written in C for both Davinci and
C6X platforms. In addition the C version of the code is marginally
smaller on Davinci.
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Jeroen Hofstee [Tue, 14 Aug 2012 10:39:29 +0000 (10:39 +0000)]
arm: omap: Fix switching back to nandecc sw.
Orjan Friberg wrote at [1]:
"For the beagleboard, ecc.size is not explicitly set when doing 'nandecc
sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's
set to 256 bytes.
When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when
changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly
the format has changed."
No patch has been submitted and the issue was still present. This patch
adds the mentioned solution. Tested on a tam3517 board.
[1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html
cc: Orjan Friberg <of@flatfrog.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
Heiko Schocher [Mon, 13 Aug 2012 23:51:04 +0000 (23:51 +0000)]
davinci: enbw_cmc: change switch init behaviour
change the behaviour of switch initialization:
- rename "pwl" to "lan" in hwconfig parameter
"lan" = port 1 with phy addr 2
"lmn" = port 2 with phy addr 3
- if we have a valid switch config file in flash, do not
evaluate the settings in the hwconfig "lan" or "lmn"
subcommand.
- if we have no valid switch config file in flash, start
the switch with default values, if we have a "lan" or
a "lmn" hwconfig subcommand. If no "lan" or "lmn" is
found in hwconfig, do nothing with the switch.
Signed-off-by: Heiko Schocher <hs@denx.de>
Satyanarayana, Sandhya [Thu, 9 Aug 2012 18:29:57 +0000 (18:29 +0000)]
am33xx evm: Update secure_emif_sdram_config during ddr init
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.
During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.
Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Sughosh Ganu [Thu, 9 Aug 2012 10:45:20 +0000 (10:45 +0000)]
da8xx/hawkboard: Add support for ohci host controller
Also enable the ohci port on hawkboard. These additions result in an
increased u-boot size -- adjust the same accordingly in the board's
config.
Move the usb header for da8xx platforms under arch-davinci.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Tom Rini [Thu, 9 Aug 2012 15:22:06 +0000 (08:22 -0700)]
armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stack
Make sure that when we setup the stack before calling s_init() we have
the stack have 8-byte alignment for ABI compliance.
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Thu, 9 Aug 2012 00:03:10 +0000 (17:03 -0700)]
omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms
Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms. As part of this we change some of the macros that are used
to be more clear. Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we
should have been doing this initially and do now.
Cc: Sricharan R <r.sricharan@ti.com>
Tested-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 8 Aug 2012 21:35:55 +0000 (14:35 -0700)]
am335x evm: Enable support for spi0
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 8 Aug 2012 21:29:51 +0000 (14:29 -0700)]
am33xx: Add support, update omap3 McSPI driver
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 8 Aug 2012 17:32:09 +0000 (10:32 -0700)]
am335x evm: Enable MMC1 pinmux
MMC1 is available in profile 2 on the GP EVM and is exposed on the
expansion header on beaglebone.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 8 Aug 2012 17:31:08 +0000 (10:31 -0700)]
am33xx: Correct MMC1, remove MMC2 support
- Correct the MMC1 base offset
- Remove MMC2 (that area is reserved and not MMC2).
- Add the real BOOT_DEVICE_MMC2 value
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 8 Aug 2012 16:03:07 +0000 (09:03 -0700)]
am335x evm: Initial support for AM335x GP EVM Profiles
The AM335x GP EVM can have one of 8 different profiles selected. Each
profile has a different set of peripherals and requires different pinmux
configurations that conflict with other profiles. i2c1 is an example of
a conflicted mux currently.
Signed-off-by: Tom Rini <trini@ti.com>
Otavio Salvador [Thu, 9 Aug 2012 04:12:44 +0000 (04:12 +0000)]
sc_sps_1: Adjust board config to use 'mxs' SoC code
Fix build failure due the move of mx28 code to 'mxs' SoC.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Benoît Thébaudeau [Wed, 8 Aug 2012 04:52:47 +0000 (04:52 +0000)]
rtc: imxdi: Initial support
Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Marek Vasut [Tue, 7 Aug 2012 00:01:52 +0000 (00:01 +0000)]
MX28: Add SchulerControl SC_SPS_1 platform
This i.MX28 platform supports the following:
* 2x FEC ethernet
* USB on USBH0
* I2C EEPROM
* SPI NVRAM
* LEDs
Signed-off-by: Marek Vasut <marex@denx.de>
Stathis Voukelatos [Tue, 7 Aug 2012 14:56:14 +0000 (15:56 +0100)]
i.MX28: bug fixes in PMU configuration code
Signed-off-by: Stathis Voukelatos <stathis.voukelatos@linn.co.uk>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Marek Vasut [Sun, 5 Aug 2012 00:36:16 +0000 (00:36 +0000)]
MX28: Move the u-boot.bd info CPUDIR/SOCDIR
This gets us rid of duplication of the same file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Sun, 5 Aug 2012 07:31:34 +0000 (07:31 +0000)]
vision2: do not overwrite the console
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Sun, 5 Aug 2012 07:31:33 +0000 (07:31 +0000)]
mx51evk: do not overwrite the console
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Stefano Babic [Sun, 5 Aug 2012 00:18:53 +0000 (00:18 +0000)]
MX5: mx53loco: do not overwrite the console
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Marek Vasut [Fri, 6 Jul 2012 21:25:57 +0000 (21:25 +0000)]
MX28: Fix MXS MMC DMA issues
The DMA didn't work properly because the DMA descriptor wasn't
properly cleaned after it was used once. Also, the DMA_ENABLE bit
was enabled/disabled too late.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Marek Vasut [Fri, 6 Jul 2012 21:25:56 +0000 (21:25 +0000)]
MX28: Transfer small blocks via PIO in MXS MMC
Large blocks (> 512b) shall be transfered via DMA to make
things a bit faster.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Marek Vasut [Fri, 6 Jul 2012 21:25:55 +0000 (21:25 +0000)]
MX28: Split out the PIO and DMA transfer functions
Move DMA and PIO data transfer parts into separate functions.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Marek Vasut [Fri, 6 Jul 2012 21:25:54 +0000 (21:25 +0000)]
MX28: Fix up the MMC driver DMA mode
The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1.
Also, it was using SSP0 DMA channel for all SSP devices.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Otavio Salvador [Sun, 5 Aug 2012 09:05:34 +0000 (09:05 +0000)]
mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCs
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Sun, 5 Aug 2012 09:05:33 +0000 (09:05 +0000)]
mxs: Clarify why we poweroff in case of brownout in 5v conflict
If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable
but this wasn't clear on code so a comment has been added to clarify
it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Sun, 5 Aug 2012 09:05:32 +0000 (09:05 +0000)]
mxs: Reowork SPL to use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Sun, 5 Aug 2012 09:05:31 +0000 (09:05 +0000)]
mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Sun, 5 Aug 2012 09:05:30 +0000 (09:05 +0000)]
mxs: prefix register acessor macros with 'mxs' prefix
As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Sun, 5 Aug 2012 09:05:29 +0000 (09:05 +0000)]
mxs: reorganize source directory for easy sharing of code in i.MXS SoCs
Most code can be shared between i.MX23 and i.MX28 as both are from
i.MXS family; this source directory structure makes easy to share code
among them.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Tue, 31 Jul 2012 08:10:06 +0000 (08:10 +0000)]
mx28evk: Turn on caches
Turn on data and instruction caches.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Otavio Salvador [Sat, 28 Jul 2012 11:44:20 +0000 (11:44 +0000)]
MX28: use a clear name for DDR2 initialization
The mx28 prefix has been added to the initialization data and function
so it is clear by which SoC it is used as i.MX233 will have a specific
one. While on that, we also change it to static.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Veli-Pekka Peltola [Mon, 9 Jul 2012 03:14:50 +0000 (03:14 +0000)]
Add support for Bluegiga APX4 Development Kit
This adds support for Bluegiga APX4 Development Kit. It is built around
Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC,
RTC and USB. APX4 has only one ethernet port.
Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>
Otavio Salvador [Sat, 28 Jul 2012 11:43:47 +0000 (11:43 +0000)]
MX28: extend print_cpuinfo() to use chip information
The information now is gathered from HW_DIGCTL_CHIPID register and
includes the chip modem and revision on the output.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Marek Vasut [Mon, 9 Jul 2012 00:48:33 +0000 (00:48 +0000)]
MX28: SPI: Add DMA transfer support
The DMA transfers happen only if the transfered data are larger
than 512 bytes. Otherwise PIO is used. This is a small speed
optimization.
The DMA transfer doesn't work if unaligned transfer is requested
due to the limitation of the DMA controller. This has to be fixed
by introducing generic bounce buffer. Therefore the DMA feature
is now disabled by default.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Marek Vasut [Mon, 9 Jul 2012 00:48:32 +0000 (00:48 +0000)]
MX28: SPI: Pull out the PIO transfer function
Pull out all the PIO transfer logic into separate function,
so DMA can be added.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Marek Vasut [Mon, 9 Jul 2012 00:48:31 +0000 (00:48 +0000)]
MX28: SPI: Refactor spi_xfer a bit
This makes it easier to adapt for addition of DMA support.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Otavio Salvador [Sat, 30 Jun 2012 05:07:32 +0000 (05:07 +0000)]
imx: Use a clear identification of an unidentified CPU type
In case an unidentified CPU type is detected it now returns
i.MX??, in a const char.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Markus Hubig [Tue, 7 Aug 2012 15:43:23 +0000 (17:43 +0200)]
at91: Add support for taskit AT91SAM9G20 boards.
This adds support for the AT91SAM9G20 boards by taskit GmbH.
Both boards, Stamp9G20 and PortuxG20, are integrated in one
file. PortuxG20 is basically a SBC built around the Stamp9G20.
Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.deve@googlemail.com>
Markus Hubig [Tue, 7 Aug 2012 15:43:22 +0000 (17:43 +0200)]
Enable the EMAC clock in at91_macb_hw_init().
Signed-off-by: Markus Hubig <mhubig@imko.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann [Tue, 7 Aug 2012 15:43:21 +0000 (17:43 +0200)]
MAINTAINERS: fix Andreas Bießmann AVR32 entry
The grasshopper board is a avr32 based device and belongs therefore to the avr32
section.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann [Tue, 7 Aug 2012 15:43:20 +0000 (17:43 +0200)]
MAINTAINERS: fix entry of Ilko Iliev
These boards have ARM cores, move to the ARM section.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Thu, 5 Jul 2012 17:21:46 +0000 (17:21 +0000)]
arm : Atmel : add at91sam9x5ek board support
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann [Mon, 2 Jul 2012 04:51:39 +0000 (04:51 +0000)]
doc/git-mailrc: update at91 and avr32
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Ilya Yanok [Tue, 7 Aug 2012 00:50:08 +0000 (00:50 +0000)]
am335x_evm: enable SMSC PHY driver
Beaglebone uses SMSC PHY which works incorrectly with generic PHY
driver so enable SMSC PHY driver to fix networking problems on
Beaglebone.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Enric Balletbò i Serra [Sun, 5 Aug 2012 00:55:56 +0000 (00:55 +0000)]
OMAP3: fix DRAM size for IGEP-based boards.
The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the
LPDDR memory consist on two dies of 256MiB.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
Laurence Withers [Mon, 30 Jul 2012 23:30:37 +0000 (23:30 +0000)]
DaVinci DA8xx: fix set_cpu_clk_info()
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...]
ARM frequency = 300 MHz
DSP frequency = -
536870913 MHz
DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Hadli, Manjunath <manjunath.hadli@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Laurence Withers [Mon, 30 Jul 2012 23:30:36 +0000 (23:30 +0000)]
DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Laurence Withers [Mon, 30 Jul 2012 23:30:35 +0000 (23:30 +0000)]
DaVinci DA850: UART2 clock ID comes from ASYNC3
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Laurence Withers [Mon, 30 Jul 2012 23:30:34 +0000 (23:30 +0000)]
DaVinci DA8xx: tidy up clock ID definition
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 1 Aug 2012 12:30:40 +0000 (12:30 +0000)]
doc/git-mailrc: Update 'ti' alias
Remove Sandeep, thanks for all the hard work!
Signed-off-by: Tom Rini <trini@ti.com>
Marek Vasut [Sat, 21 Jul 2012 05:02:23 +0000 (05:02 +0000)]
dm: Move OMAP GPIO driver to drivers/gpio/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Marek Vasut [Sat, 21 Jul 2012 05:02:27 +0000 (05:02 +0000)]
dm: Select CONFIG_SPL_GPIO_SUPPORT on OMAP
This fixes the breakage with SPL on most OMAP boards after the GPIO
driver was moved.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 31 Jul 2012 17:50:01 +0000 (10:50 -0700)]
am33xx: Rework pinmux functions
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
- Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 31 Jul 2012 16:37:08 +0000 (09:37 -0700)]
am33xx evm: Add CONFIG_CMD_EEPROM and related
am33xx boards have at least one eeprom and in the case of beaglebones
with capes, more.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 31 Jul 2012 15:55:01 +0000 (08:55 -0700)]
am33xx: Add support for TI AM335x StarterKit EVM
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
config_ddr with.
- Both of the above require filling in the header structure early, move
it into the data section.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 30 Jul 2012 23:13:10 +0000 (16:13 -0700)]
am33xx: Remove board/ti/am335x/evm.c
The intention has always been (and boards are to support) an i2c EEPROM
that will identify what hardware they are, allowing a single binary to
support multiple boards. As such, remove the 'evm.c' file as there is
nothing EVM centric in it currently, only SoC peripheral configuration.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 30 Jul 2012 21:49:50 +0000 (14:49 -0700)]
am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 30 Jul 2012 21:13:56 +0000 (14:13 -0700)]
am33xx: Rework config_ddr to make DDR3 support easier.
In order to support DDR3 as well as DDR2, we need to perform the same
init sequence, but with different values. So change config_ddr() to
toggle setting pointers/etc for what DDR2 wants, and then calling.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 30 Jul 2012 21:13:16 +0000 (14:13 -0700)]
am33xx: Move some variables in emif4.c, mark them static.
We need vtpreg and ddrctrl but no longer need a second ddrregs.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 30 Jul 2012 18:49:47 +0000 (11:49 -0700)]
am33xx: Correct and clean up ddr_regs struct
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 24 Jul 2012 23:49:58 +0000 (16:49 -0700)]
am33xx: Do not touch 'ratio1' fields
The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 24 Jul 2012 23:31:26 +0000 (16:31 -0700)]
am33xx: Rework config_io_ctrl slightly
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation). Rather than defining a struct and setting the
value repeatedly, just pass in the value.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 24 Jul 2012 21:55:38 +0000 (14:55 -0700)]
am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 24 Jul 2012 21:54:41 +0000 (14:54 -0700)]
am33xx: Turn a number of 'int' functions to 'void'
A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 24 Jul 2012 21:03:24 +0000 (14:03 -0700)]
am33xx: Document what we're doing with ddrctrl->ddrckectrl
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
we're operating in the normal mode where EMIF/PHY clock is controlled
by the PHY.
Signed-off-by: Tom Rini <trini@ti.com>
Vaibhav Bedia [Fri, 20 Apr 2012 07:58:16 +0000 (13:28 +0530)]
am335x: ddr_defs: Update EMIF parameters
EMIF parameters are calculated based on the AC timing
parameters from the SDRAM datasheet and the DDR frequency.
Current values for these paramters in AM335x U-Boot code,
though reliable, are not fully optimal. The most optimal
settings can be derived based on the guidelines published
at [1]. A pre-computed set of values with the most optimum
settings for AM335x EVM and BeagleBone can be found at [2].
[1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
[2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 24 Jul 2012 20:05:10 +0000 (13:05 -0700)]
am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 3 Jul 2012 16:20:06 +0000 (09:20 -0700)]
am33xx: Move the call to ddr_pll_config, make it take the frequency
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value. This call can be delayed
slightly to the point where we know which type of memory we have.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 3 Jul 2012 15:51:34 +0000 (08:51 -0700)]
am33xx: Pass to config_ddr the type of memory that is connected
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()). For now, pass in
the value of DDR2.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 3 Jul 2012 15:48:46 +0000 (08:48 -0700)]
am33xx: Make config_cmd_ctrl / config_ddr_data take const structs
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const. This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Thu, 26 Jul 2012 14:49:23 +0000 (07:49 -0700)]
am33xx: Rework DDR2 EMIF initalization slightly
With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Thu, 26 Jul 2012 00:04:12 +0000 (17:04 -0700)]
am33xx: Bugfix to config_sdram()
When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 3 Jul 2012 15:45:31 +0000 (08:45 -0700)]
am33xx: Remove extra check in enable_ddr_clocks
We do not need to check for EMIF_GCLK and L3_GCLK being active. This
was a hold-over from bringup and no longer required.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 29 May 2012 16:02:15 +0000 (09:02 -0700)]
am33xx: Convert to using <asm/emif.h> to describe the EMIF
Signed-off-by: Tom Rini <trini@ti.com>