oweals/u-boot.git
6 years agoarm: zynq: Add board support for cc108
Michal Simek [Thu, 2 Nov 2017 08:18:42 +0000 (09:18 +0100)]
arm: zynq: Add board support for cc108

cc108 board is wiring uart via PL which is good platform for SPL fpga
support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoarm: zynq: Enable qspi for zc770_xm013
Michal Simek [Thu, 2 Nov 2017 09:46:15 +0000 (10:46 +0100)]
arm: zynq: Enable qspi for zc770_xm013

Enable qspi driver and flashes for this board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Enable MACRONIX flash for zc702/zc706/zc770 xm010
Michal Simek [Thu, 2 Nov 2017 09:44:48 +0000 (10:44 +0100)]
arm: zynq: Enable MACRONIX flash for zc702/zc706/zc770 xm010

Enable MACRONIX flash for boards with QSPI enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Enable debug console on zc770 xm010 by default
Michal Simek [Thu, 2 Nov 2017 09:40:57 +0000 (10:40 +0100)]
arm: zynq: Enable debug console on zc770 xm010 by default

Enable debug console.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Enable bootz command for Xilinx platforms
Michal Simek [Thu, 2 Nov 2017 09:38:16 +0000 (10:38 +0100)]
arm: zynq: Enable bootz command for Xilinx platforms

bootz command is valid way how to boot Linux kernel. Enable it by
default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Sync location of DT properties with Linux
Michal Simek [Thu, 2 Nov 2017 08:24:12 +0000 (09:24 +0100)]
arm: zynq: Sync location of DT properties with Linux

This is trival change which only ensures the same location with Linux
kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Remove empty ifdef env structures from config file
Michal Simek [Thu, 2 Nov 2017 08:29:15 +0000 (09:29 +0100)]
arm: zynq: Remove empty ifdef env structures from config file

All these configs were moved to Kconfig that's why this empty ifdef
structure is not needed anymore.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Add device-type property for zynq ethernet phy nodes
Sai Pavan Boddu [Mon, 6 Mar 2017 12:47:19 +0000 (18:17 +0530)]
arm: zynq: Add device-type property for zynq ethernet phy nodes

Mention device-type = "ethernet-phy", as qemu will need this in absence
of compatible.

Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Add SCL & SDA GPIO entries for recovery
Chirag Parekh [Tue, 27 Dec 2016 16:37:58 +0000 (22:07 +0530)]
arm: zynq: Add SCL & SDA GPIO entries for recovery

Wire i2c pinmuxing gpio recovery for zc702.

Signed-off-by: Chirag Parekh <chiragp@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agomtd: nand: zynq: Add a config option to use 1st stage bootloader timing
Jeff Westfahl [Mon, 6 Nov 2017 08:34:46 +0000 (00:34 -0800)]
mtd: nand: zynq: Add a config option to use 1st stage bootloader timing

In legacy method, 1st stage bootloader was used to configure the HW
setting such as NAND timing. Hence, adding a config option in Zynq
NAND driver for the compatibility of device that using 1st stage
bootloder instead of U-boot SPL.

This commit is to add config option
CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use
timing values set by the 1st stage bootloader, instead of the hard-coded
values in the Zynq NAND driver.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Add support for SYZYGY Hub board
Tom McLeod [Thu, 28 Sep 2017 00:53:26 +0000 (17:53 -0700)]
arm: zynq: Add support for SYZYGY Hub board

Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
booting from SD.

Signed-off-by: Tom McLeod <tom.mcleod@opalkelly.com>
Cc: Michal Simek <monstr@monstr.eu>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm64: zynqmp: remove unnecessary logical constraint
Heinrich Schuchardt [Thu, 12 Oct 2017 23:14:27 +0000 (01:14 +0200)]
arm64: zynqmp: remove unnecessary logical constraint

In

if (a || b)
else if (!a)

the constraint (!a) is always true if else is reached and
can be removed.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agotest: Correct operation when tests pass
Simon Glass [Mon, 27 Nov 2017 03:25:55 +0000 (20:25 -0700)]
test: Correct operation when tests pass

When tests pass an error message is printed because of a variable that is
not initialised. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agospl: TI: Do not default to SPL_FIT_IMAGE_TINY being enabled
Tom Rini [Tue, 28 Nov 2017 01:07:47 +0000 (20:07 -0500)]
spl: TI: Do not default to SPL_FIT_IMAGE_TINY being enabled

This option prevents booting on am335x_evm at least along with most
likely other platforms.

Fixes: 337bbb629777 ("spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size")
Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoMerge git://www.denx.de/git/u-boot-imx
Tom Rini [Mon, 27 Nov 2017 12:22:11 +0000 (07:22 -0500)]
Merge git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoconfigs: icore-rqs: Enable falcon mode
Jagan Teki [Mon, 20 Nov 2017 18:32:18 +0000 (00:02 +0530)]
configs: icore-rqs: Enable falcon mode

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agoengicam: imx6q: Return mmc dev 0 for icore
Jagan Teki [Mon, 20 Nov 2017 18:32:17 +0000 (00:02 +0530)]
engicam: imx6q: Return mmc dev 0 for icore

icorem6 has sd on usdhci1 which is devno 0 so return proper
devno from board_mmc_get_env_dev for icorem6 and icorem_6rqs

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agoi.MX6: engicam: Add imx6q/imx6ul boards for existing boards
Jagan Teki [Mon, 20 Nov 2017 18:32:16 +0000 (00:02 +0530)]
i.MX6: engicam: Add imx6q/imx6ul boards for existing boards

Add new board names for existing board support
imx6q - icore and icore_rqs boards
imx6ul - geam6ul and isiot boards

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agoboard: icore-rqs: Fix mmc get env device
Jagan Teki [Mon, 20 Nov 2017 18:32:15 +0000 (00:02 +0530)]
board: icore-rqs: Fix mmc get env device

As per USDHC boot eFUSE descriptions:
USDHC3 => devno 2
USDHC4 => devno 3

Linux will detect mmc0, mmc1, mmc2 based on the status
"okay" on usdhc so imx6qdl-icore-rqs.dtsi has enabled
usdhc1, usdhc3 and usdhc4.But U-Boot can detect based
on the aliases so add mmc1, mmc2 for usdhc3 and usdhc4
respectively and return the board_mmc_get_env_dev
by subtracting -1

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agoi.MX6UL: icore: Add SPL_OF_CONTROL support
Jagan Teki [Mon, 20 Nov 2017 18:32:14 +0000 (00:02 +0530)]
i.MX6UL: icore: Add SPL_OF_CONTROL support

Add OF_CONTROL support for SPL code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agopinctrl: imx6ul: Fix pinctrl data overlapped with DT area
Jagan Teki [Mon, 20 Nov 2017 18:32:13 +0000 (00:02 +0530)]
pinctrl: imx6ul: Fix pinctrl data overlapped with DT area

before relocation pinctrl data BSS is overlapping DT area,
when .data is using uninitialized global variable,
imx6_pinctrl_soc_info. So assign them flags ZERO_OFFSET_VALID
to prevent BSS overlap

Suggested-by: Lokesh Vutla <lokeshvutla@ti.com>
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agoi.MX6Q: icore: Add SPL_OF_CONTROL support
Jagan Teki [Mon, 20 Nov 2017 18:32:12 +0000 (00:02 +0530)]
i.MX6Q: icore: Add SPL_OF_CONTROL support

Add OF_CONTROL support for SPL code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agoi.MX6Q: icorem6: Move spl load fit to common/spl
Jagan Teki [Mon, 20 Nov 2017 18:32:11 +0000 (00:02 +0530)]
i.MX6Q: icorem6: Move spl load fit to common/spl

Move spl load fit code into common/spl

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agoi.MX6: engicam: Move set_fdt_file to common
Jagan Teki [Mon, 20 Nov 2017 18:32:10 +0000 (00:02 +0530)]
i.MX6: engicam: Move set_fdt_file to common

setenv_fdt_file to common code and set dtb based on
CONFIG_DEFAULT_DEVICE_TREE and cpu_type.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agomx6sxsabresd: Use PARTUUID to specify the rootfs location
Fabio Estevam [Wed, 22 Nov 2017 13:15:28 +0000 (11:15 -0200)]
mx6sxsabresd: Use PARTUUID to specify the rootfs location

mx6sxsabresd can run different kernel versions, such as NXP 4.1 or mainline.

Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the SD
card changes depending on the kernel version.

In order to avoid such issue, use the UUID method to specify the
rootfs location.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
6 years agoimx: Remove boolean parameter from wdog powerdown function
Fabio Estevam [Thu, 23 Nov 2017 12:55:33 +0000 (10:55 -0200)]
imx: Remove boolean parameter from wdog powerdown function

imx_set_wdog_powerdown() is always used to disable the power down
enable bit, so remove the boolean parameter of the function.

It is also a bit strange to write a boolean value into registers,
so this new version makes explicit that we are writing 0.

While at it, rename it to imx_wdog_disable_powerdown().

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
6 years agoimx: Also clear powerdown enable bit for WDOG3 on i.MX6ULL
Fabio Estevam [Thu, 23 Nov 2017 11:18:54 +0000 (09:18 -0200)]
imx: Also clear powerdown enable bit for WDOG3 on i.MX6ULL

Clear powerdown enable bit for WDOG3 on i.MX6ULL to avoid unwanted
kernel reboots.

Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
6 years agomx6ull: Fix WDOG3 base address
Fabio Estevam [Thu, 23 Nov 2017 11:18:53 +0000 (09:18 -0200)]
mx6ull: Fix WDOG3 base address

i.MX6ULL has the same WDOG3 base address as i.MX6UL, so take this
into account in the base address definition.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
6 years agoMerge git://git.denx.de/u-boot-rockchip
Tom Rini [Sun, 26 Nov 2017 23:10:21 +0000 (18:10 -0500)]
Merge git://git.denx.de/u-boot-rockchip

6 years agorockchip: defconfig: puma-rk3399: bypass ADC-based boot_mode check
Philipp Tomsich [Fri, 24 Nov 2017 13:44:59 +0000 (14:44 +0100)]
rockchip: defconfig: puma-rk3399: bypass ADC-based boot_mode check

The boot (and fallback/emergency boot) concept for the RK3399-Q7
differs from Rockchip's reference platforms.

On the RK3399-Q7, some of this functionality is present in the
bootloader itself (and configurable); some is backed in hardware by
the Qseven BIOS_DISABLE signal to invoke the final stages of fallbacks
(i.e. either an external boot bypassing on-module memories or falling
back to the BROM for USB recovery).

In summary: the ADC-based boot_mode check does not apply for the
RK3399-Q7 and we therefore disable it (in this commit) by setting
CONFIG_BOOT_MODE_REG to 0.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: fix turning off boot-mode via Kconfig
Philipp Tomsich [Fri, 24 Nov 2017 13:44:58 +0000 (14:44 +0100)]
rockchip: fix turning off boot-mode via Kconfig

The ROCKCHIP_BOOT_MODE_REG option defaults to a hex value, so 0 will
show as 0x0 if a default is provided and changed via Kconfig.
However, it still will show as 0, if no default is given.

Consequently, the "is set to something other than 0" test in a
Makefile is cumbersome.  Instead this check can easily be performed in
the C-code.

This removes the ifeq-check from mach-rockchip/Makefile, adds a
matching #if-check to boot_mode.c and fixes resulting link issues (if
boot_mode.o was not included due to the Makefile check) by defining a
stub function (in case the functionality is not built in) for
setup_boot_mode in boot_mode.c.

Fixes: e306779 (rockchip: make boot_mode related codes reused across all platforms)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: pinctrl: rk3399: add support for I2C8
Philipp Tomsich [Wed, 22 Nov 2017 18:47:37 +0000 (19:47 +0100)]
rockchip: pinctrl: rk3399: add support for I2C8

The RK3399 has a total of 9 I2C controllers.  To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.

For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
6 years agorockchip: clk: rk3399: change extract_bits to bitfield_extract
Philipp Tomsich [Wed, 22 Nov 2017 18:45:04 +0000 (19:45 +0100)]
rockchip: clk: rk3399: change extract_bits to bitfield_extract

The RK3399 clk driver still has a left-over use of extract_bits, which
can be replaced by using bitfield_extract from include/bitfield.h.
This rewrites the invocation to use the shared function.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agospl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
Philipp Tomsich [Fri, 24 Nov 2017 12:26:03 +0000 (13:26 +0100)]
spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size

A minor code-size increase from the changes for tracking the os-type
of FIT images and from infrastructure for recording the loadables into
the the loaded FDT, broke the builds for sun50i and some OMAP2+ devices.

This change adds a new config option (enabled by default for
MACH_SUN50I, MACH_SUN50I_H5 and ARCH_OMAP2PLUS) that does skips these
processing steps (bringing code size down to below the limit
again). The os-type is not evaluated, but assumed to be IH_OS_UBOOT
(i.e. taking the code-paths intended for backward-compatibility).

Note that enabling this config option precludes any useful downstream
processing, such as utilising a special calling convention for ATF or
OPTEE, based on the os-type of the loadables.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: defconfig: lion-rk3368: sync up with SPL changes for ATF
Philipp Tomsich [Wed, 13 Sep 2017 19:29:43 +0000 (21:29 +0200)]
rockchip: defconfig: lion-rk3368: sync up with SPL changes for ATF

This tracks the SPL changes for ATF for the RK3368-uQ7:
 * renames ATF_SUPPORT to ATF
 * drops CONFIG_SPL_ATF_TEXT_BASE (now dynamically retrieved from
   the .itb file)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agorockchip: defconfig: puma-rk3399: sync up with SPL changes for ATF
Philipp Tomsich [Wed, 13 Sep 2017 19:29:42 +0000 (21:29 +0200)]
rockchip: defconfig: puma-rk3399: sync up with SPL changes for ATF

This defconfig update makes use of the new features:
 * CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is now set to 0, as there is no
   overlap between the M0 firmware and the ATF (we load this to DRAM
   and relocate it to its final location within the ATF)
 * tracks the ATF_SUPPORT -> ATF renaming

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agorockchip: board: lion-rk3368: update .its file
Philipp Tomsich [Wed, 13 Sep 2017 19:29:41 +0000 (21:29 +0200)]
rockchip: board: lion-rk3368: update .its file

For the RK3368-uQ7, we can now update the .its file to mark the
Trusted Firmware as out 'firmware' bootable and annotate both ATF and
U-Boot with an OS-type.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agorockchip: board: puma-rk3399: update .its file to use new features
Philipp Tomsich [Wed, 13 Sep 2017 19:29:40 +0000 (21:29 +0200)]
rockchip: board: puma-rk3399: update .its file to use new features

This commit updates the .its file for the RK3399-Q7 to use the new
features and demonstrates how to use those:
 * it marks the ATF as the 'firmware'
 * it tracks the OS-type for U-Boot and ATF
 * it loads the PMU (M0) firmware to DRAM and records the location
   to /fit-images (where our ATF reads it from)

With the handoff of the next-stage FDT to ATF in place, we can now use
this to pass information about the load addresses and names of each
loadables to ATF: now we can load the M0 firmware into DRAM and avoid
overwriting parts of the SPL stage.  This is achieved by changing our
.its-file to use an available area of DRAM as the load-address.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agorockchip: defconfig: firefly-rk3399: sync up with SPL changes for ATF
Philipp Tomsich [Wed, 13 Sep 2017 19:29:39 +0000 (21:29 +0200)]
rockchip: defconfig: firefly-rk3399: sync up with SPL changes for ATF

This tracks the SPL changes for ATF for the Firefly:
 * renames ATF_SUPPORT to ATF
 * drops CONFIG_SPL_ATF_TEXT_BASE

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: atf: drop the SPL_ATF_TEXT_BASE configuration item
Philipp Tomsich [Wed, 13 Sep 2017 19:29:37 +0000 (21:29 +0200)]
spl: atf: drop the SPL_ATF_TEXT_BASE configuration item

The SPL_ATF_TEXT_BASE configuration item has become obsolete.
Remove it from Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: rename config item SPL_ATF_SUPPORT to SPL_ATF
Philipp Tomsich [Wed, 13 Sep 2017 19:29:36 +0000 (21:29 +0200)]
spl: rename config item SPL_ATF_SUPPORT to SPL_ATF

Having CONFIG_SPL_ATF seems more natural.
Rename it, while it it is easy and there's few boards that use it
(only RK3399 and RK3368 boards).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: atf: introduce spl_invoke_atf and make bl31_entry private
Philipp Tomsich [Wed, 13 Sep 2017 19:29:35 +0000 (21:29 +0200)]
spl: atf: introduce spl_invoke_atf and make bl31_entry private

This adds a new interface spl_invoke_atf() that takes a spl_image_info
argument and then derives the necessary parameters for the ATF entry.
Based on the additional information recorded (into /fit-images) from
the FIT loadables, we can now easily locate the next boot stage.

We now pass a pointer to a FDT as the platform-specific parameter
pointer to ATF (so we don't run into the future headache of every
board/platform defining their own proprietary tag-structure), as
FDT access is already available in ATF.

With the necessary infrastructure in place, we can now update the
support for the ARM Trusted Firmware to dispatch into the
spl_invoke_atf function only if a IH_OS_ARM_TRUSTED_FIRMWARE image is
loaded.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: fit: implement recording of loadables into /fit-images
Philipp Tomsich [Wed, 13 Sep 2017 19:29:34 +0000 (21:29 +0200)]
spl: fit: implement recording of loadables into /fit-images

If a FDT was loaded (e.g. to append it to U-Boot image), we store it's
address and record information for all loadables into this FDT.  This
allows us to easily keep track of images for multiple privilege levels
(e.g. with ATF) or of firmware images preloaded into temporary
locations (e.g. PMU firmware that may overlap the SPL stage).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: fit: implement fdt_record_loadable
Philipp Tomsich [Wed, 13 Sep 2017 19:29:33 +0000 (21:29 +0200)]
spl: fit: implement fdt_record_loadable

During the loading of more complex FIT images (e.g. when the invoked
next stage needs to find additional firmware for a power-management
core... or if there are multiple images for different privilege levels
started in parallel), it is helpful to create a record of what images
are loaded where: if a FDT is loaded for one of the next stages, it
can be used to convey the status and location of loadables.

This adds a fdt_record_loadable() function that can be invoked to
record the status of each loadable below the /fit-images path.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: fit: simplify logic for FDT loading for non-OS boots
Philipp Tomsich [Wed, 13 Sep 2017 19:29:32 +0000 (21:29 +0200)]
spl: fit: simplify logic for FDT loading for non-OS boots

To better support bootin through an ATF or OPTEE, we need to
streamline some of the logic for when the FDT is appended to an image:
depending on the image type, we'd like to append the FDT not at all
(the case for the OS boot), to the 'firmware' image (if it is a
U-Boot) or to one of the loadables (if the 'firmware' is an ATF, an
OPTEE, or some other image-type and U-Boot is listed in the
loadabled).

To achieve this goal, we drop the os_boot flag and track the type of
image loaded.  If it is of type IH_OS_U_BOOT, we append the FDT.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: change load_addr and entry_point to uintptr_t
Philipp Tomsich [Wed, 13 Sep 2017 19:29:31 +0000 (21:29 +0200)]
spl: change load_addr and entry_point to uintptr_t

Mainly a stylistic change: convert the load_addr and entry_point
fields of struct spl_image_info to uintptr_t (from ulong).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: add a fdt_addr field to spl_image_info
Philipp Tomsich [Wed, 13 Sep 2017 19:29:30 +0000 (21:29 +0200)]
spl: add a fdt_addr field to spl_image_info

When loading a full U-Boot with detached device-tree using the SPL FIT
backend, we should store the address of the FDT loaded as part of the
SPL image info: this allows us to fixup the FDT with additional info
we may want to propagate onward.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoimage: add IH_OS_ARM_TRUSTED_FIRMWARE for ARM Trusted Firmware
Philipp Tomsich [Wed, 13 Sep 2017 19:29:29 +0000 (21:29 +0200)]
image: add IH_OS_ARM_TRUSTED_FIRMWARE for ARM Trusted Firmware

To boot on ARMv8 systems with ARM Trusted Firmware, we need to
assemble an ATF-specific parameter structure and also provide the
address of the images started by ATF (e.g. BL3-3, which may be the
full U-Boot).

To allow us to identify an ARM Trusted Firmware contained in a FIT
image, this adds the necessary definitions.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoMerge git://git.denx.de/u-boot-arc
Tom Rini [Fri, 24 Nov 2017 16:45:15 +0000 (11:45 -0500)]
Merge git://git.denx.de/u-boot-arc

6 years agoarc: cache: Add required NOPs after invalidation of instruction cache
Alexey Brodkin [Fri, 17 Nov 2017 13:02:17 +0000 (16:02 +0300)]
arc: cache: Add required NOPs after invalidation of instruction cache

As per ARC HS databook (see chapter 5.3.3.2) it is required to add
3 NOPs after each write to IC_IVIC which we do from now on.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
6 years agoarc: bootm: Move slave cores kick-starting under !fake
Alexey Brodkin [Fri, 17 Nov 2017 12:53:20 +0000 (15:53 +0300)]
arc: bootm: Move slave cores kick-starting under !fake

Currently slave cores will be kick-started even if we want
to dry run bootm which is not what we really want.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
6 years agoARC: HSDK: introduce CREG GPIO driver
Eugeniy Paltsev [Mon, 16 Oct 2017 13:21:32 +0000 (16:21 +0300)]
ARC: HSDK: introduce CREG GPIO driver

The HSDK can manage some pins via CREG registers block.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Fri, 24 Nov 2017 03:48:35 +0000 (22:48 -0500)]
Merge git://git.denx.de/u-boot-dm

6 years agobinman: Return non-zero exit code on test failure
Simon Glass [Mon, 13 Nov 2017 04:52:29 +0000 (21:52 -0700)]
binman: Return non-zero exit code on test failure

Return exit code 1 when test fail so that callers can detect this.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add add test for using an Intel MRC binary
Simon Glass [Mon, 13 Nov 2017 04:52:28 +0000 (21:52 -0700)]
binman: Add add test for using an Intel MRC binary

MRC (Memory Reference Code) is a binary blob used to set up the SDRAM
controller on some Intel boards. Add a test for this feature.

With this test coverage on binman is back up to 100%.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add add test for SPL with a microcode pointer
Simon Glass [Mon, 13 Nov 2017 04:52:27 +0000 (21:52 -0700)]
binman: Add add test for SPL with a microcode pointer

Add a test for this feature. It allows SPL to hold a pointer to the
microcode block. This is used for 64-bit U-Boot on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add a test for x86-start16-spl
Simon Glass [Mon, 13 Nov 2017 04:52:26 +0000 (21:52 -0700)]
binman: Add a test for x86-start16-spl

This allows us to put the 16-bit x86 start-up code in SPL. Add a test for
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add test for u-boot-spl-bss-pad
Simon Glass [Mon, 13 Nov 2017 04:52:25 +0000 (21:52 -0700)]
binman: Add test for u-boot-spl-bss-pad

Add a test that we can pad the BSS with zero bytes.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Check for files missing from test coverage
Simon Glass [Mon, 13 Nov 2017 04:52:24 +0000 (21:52 -0700)]
binman: Check for files missing from test coverage

Files that are never imported are not shown in the test-coverage report.
Detect these and show an error.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Increase test coverage back to 100%
Simon Glass [Mon, 13 Nov 2017 04:52:23 +0000 (21:52 -0700)]
binman: Increase test coverage back to 100%

Make a minor tweak to fix test coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add a main program to the tests
Simon Glass [Mon, 13 Nov 2017 04:52:22 +0000 (21:52 -0700)]
binman: Add a main program to the tests

Add a main program so that the tests can be executed directly, without
going through the main binman program.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add tests for importlib availability
Simon Glass [Mon, 13 Nov 2017 04:52:21 +0000 (21:52 -0700)]
binman: Add tests for importlib availability

Add a test that the 'entry' module works with or without importlib.
The tests are numbered so that they are executed in the correct order.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Set up 'entry' to permit full test coverage
Simon Glass [Mon, 13 Nov 2017 04:52:20 +0000 (21:52 -0700)]
binman: Set up 'entry' to permit full test coverage

There is a little check at the top of entry.py which decides if importlib
is available. At present this has no test coverage. To add this we will
need to import the module twice, once with importlib and once without.
In preparation for allowing a test to control the importing of this
module, remove all global imports of the 'entry' module.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Append to PYTHONPATH when running test coverage
Simon Glass [Mon, 13 Nov 2017 04:52:19 +0000 (21:52 -0700)]
binman: Append to PYTHONPATH when running test coverage

Rather that overwrite this, append to it, in case the caller has already
set up the path correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agodtoc: Fix up tests
Simon Glass [Mon, 13 Nov 2017 04:52:17 +0000 (21:52 -0700)]
dtoc: Fix up tests

The tool has changed slightly since it was originally written. Update the
tests to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobuildman: Fix up tests
Simon Glass [Mon, 13 Nov 2017 04:52:15 +0000 (21:52 -0700)]
buildman: Fix up tests

The tests were broken by two separate commits which adjusted the output
when boards are listed. Fix this by adding back a PowerPC board and
putting the name of each board in the test.

Fixes: b9f7d881 (powerpc, 5xx: remove some "5xx" remains)
Fixes: 8d7523c5 (buildman: Allow showing the list of boards with -n)

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobuildman: Allow skipping of tests which use the network
Simon Glass [Mon, 13 Nov 2017 04:52:14 +0000 (21:52 -0700)]
buildman: Allow skipping of tests which use the network

Accessing the network slows down the test and limits the environment in
which it can be run. Add an option to disable network tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agopatman: Fix up tests to pass with newest checkpatch
Simon Glass [Mon, 13 Nov 2017 04:52:12 +0000 (21:52 -0700)]
patman: Fix up tests to pass with newest checkpatch

The checkpatch tool was updated but the patman tests were not. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agotest/run: Report and return failure
Simon Glass [Mon, 13 Nov 2017 04:52:10 +0000 (21:52 -0700)]
test/run: Report and return failure

This script runs the tests but does not report failure. Also it always
returns an exit code of 0 even on failure.

Fix these problems by checking the result of each test.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Disable the no-unit_address_vs_reg warnings
Simon Glass [Mon, 13 Nov 2017 04:52:09 +0000 (21:52 -0700)]
binman: Disable the no-unit_address_vs_reg warnings

These warnings are not useful for binman tests. Disable them.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Rename tests to ftest
Simon Glass [Mon, 13 Nov 2017 04:52:08 +0000 (21:52 -0700)]
binman: Rename tests to ftest

At present these tests use the same filename as patman. This adds
confusion when running all tests, since error messages look very similar.
In fact binman tries to run the wrong tests at present.

Rename the tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add a Makefile for test-program compilation
Simon Glass [Mon, 13 Nov 2017 04:52:07 +0000 (21:52 -0700)]
binman: Add a Makefile for test-program compilation

These test programs are includedd as binary files in U-Boot to avoid
having to build them (and associated toolchain differences). Instructions
on building are in the files themselves, but it seems better to provide
a Makefile which can be manually run when desired.

Add a Makefile, separate from the normal build system, to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add docs explaining how to enable binman for a board
Simon Glass [Mon, 13 Nov 2017 04:52:06 +0000 (21:52 -0700)]
binman: Add docs explaining how to enable binman for a board

The process is not obvious. Add a little section to explain how to move a
board to use binman.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agobinman: Add better Makefile debugging
Simon Glass [Mon, 13 Nov 2017 04:52:05 +0000 (21:52 -0700)]
binman: Add better Makefile debugging

There is a debugging option in the Makefile to allow people to figure out
which u-boot.dtsi files are used in the build. But is it not easy to use
since it only shows files it finds, not those it is looking for. Update it
and update the mention of it to the docs.

Signed-off-by: Simon Glass <sjg@chromium.org>
6 years agoMerge git://git.denx.de/u-boot-rockchip
Tom Rini [Wed, 22 Nov 2017 12:28:58 +0000 (07:28 -0500)]
Merge git://git.denx.de/u-boot-rockchip

6 years agorockchip: remove duplicate CONFIG_ENV_SIZE definitions
Philipp Tomsich [Tue, 21 Nov 2017 21:35:56 +0000 (22:35 +0100)]
rockchip: remove duplicate CONFIG_ENV_SIZE definitions

A few header files still have a definition of CONFIG_ENV_SIZE, causing
warnings during buildman runs.  This removes the duplicate definitions
from evb_px5.h, geekbox.h and rv1108_common.h.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: check download key before bootup
Andy Yan [Wed, 11 Oct 2017 07:01:31 +0000 (15:01 +0800)]
rockchip: check download key before bootup

Enter download mode if the download key pressed.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Converted printfs in boot_mode.c to debug/pr_err:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: add support for enter to bootrom download mode
Andy Yan [Wed, 11 Oct 2017 07:00:49 +0000 (15:00 +0800)]
rockchip: add support for enter to bootrom download mode

Rockchip bootrom will enter download mode if it returns from
spl/tpl with a non-zero value and couldn't find a valid image
in the backup partition.
This patch provide a method to instruct the system to back to
bootrom download mode by checking the BROM_DOWNLOAD_FLAG register.
As the bootrom download function relys on some modules such as
interrupts, so we need to back to bootrom as early as possbile
before the tpl/spl code override the interrupt configurations.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: make boot_mode related codes reused across all platforms
Andy Yan [Wed, 11 Oct 2017 07:00:16 +0000 (15:00 +0800)]
rockchip: make boot_mode related codes reused across all platforms

setup_boot_mode function use the same logic but different
mode register address across all the rockchip platforms,
so it's better to make this function reused across all the
platforms, and let the mode register address setting from
the config file.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: spi: the symbol for Hertz is Hz
Heinrich Schuchardt [Sun, 12 Nov 2017 19:59:44 +0000 (20:59 +0100)]
rockchip: spi: the symbol for Hertz is Hz

fix typo

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: clock: update sysreset driver binding
Kever Yang [Fri, 3 Nov 2017 07:16:13 +0000 (15:16 +0800)]
rockchip: clock: update sysreset driver binding

Using priv for new sysreset driver binding.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: sysreset: update Makefile to work with merged sysreset driver
Philipp Tomsich [Tue, 21 Nov 2017 21:28:55 +0000 (22:28 +0100)]
rockchip: sysreset: update Makefile to work with merged sysreset driver

After applying the merged sysreset driver, there are build failures
due to an out-of-sync Makefile. This updates drivers/sysreset/Makefile
to address these build failures.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: sysreset: merge into one common driver
Kever Yang [Fri, 3 Nov 2017 07:16:12 +0000 (15:16 +0800)]
rockchip: sysreset: merge into one common driver

Use a common driver for all Rockchip SOC instead of one for each SoC.
Use driver_data for reg offset.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: mkimage: remove unused code-paths (spl_boot0 is now implied)
Philipp Tomsich [Tue, 10 Oct 2017 14:21:18 +0000 (16:21 +0200)]
rockchip: mkimage: remove unused code-paths (spl_boot0 is now implied)

With all targets converted to generate prepadded images, this removes
the spl_boot0 field from our config structure and removes the unused
code-path (for images that are not prepadded): i.e. spl_boot0 is now
implied as 'true' and the code is specialised by removing the other
case.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: rk3188: move CONFIG_SPL_* entries from rk3188_common.h to Kconfig
Philipp Tomsich [Tue, 10 Oct 2017 14:21:17 +0000 (16:21 +0200)]
rockchip: rk3188: move CONFIG_SPL_* entries from rk3188_common.h to Kconfig

There still are a few CONFIG_SPL_* options selected using defines from
rk3188_common.h instead of via Kconfig.  This migrates those over to
Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: back-to-bootrom: allow passing a cmd to the bootrom
Philipp Tomsich [Tue, 10 Oct 2017 14:21:16 +0000 (16:21 +0200)]
rockchip: back-to-bootrom: allow passing a cmd to the bootrom

The BROM supports forcing it to enter download-mode, if an appropriate
result/cmd-word is returned to it.  There already is a series to
support this in review, so this prepares the (newly C-version) of the
back-to-bootrom code to accept a cmd to passed on to the BROM.

All the existing call-sites are adjusted to match the changed function
signature.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
6 years agorockchip: rk3188: use boot0 hook to load up SPL in 2 steps
Philipp Tomsich [Tue, 10 Oct 2017 14:21:15 +0000 (16:21 +0200)]
rockchip: rk3188: use boot0 hook to load up SPL in 2 steps

For the RK3188, the BROM will attempt to load up the first stage
image (SPL for the RK3188) in two steps: first 1KB to offset 0x800
in the SRAM and then the remainder to offset 0xc00 in the SRAM.
It always enters at 0x804, though.

With this changeset, the RK3188 boot removes the TPL (stub) stage and
builds a single SPL binary that utilizes the early back-to-bootrom via
the boot0-hook.

Consequently, the passing of the saved boot params via pmu->os_reg[2]
is also removed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: back-to-bootrom: replace assembly-implementation with C-code
Philipp Tomsich [Tue, 10 Oct 2017 14:21:14 +0000 (16:21 +0200)]
rockchip: back-to-bootrom: replace assembly-implementation with C-code

The back-to-bootrom implementation for Rockchip has always relied on
the stack-pointer being valid on entry, so there was little reason to
have this as an assembly implementation.

This provides a new C-only implementation of save_boot_params and
back_to_bootrom (relying on setjmp/longjmp) and removes the older
assembly-only implementation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
6 years agoarm: provide a PCS-compliant setjmp implementation
Philipp Tomsich [Tue, 10 Oct 2017 14:21:13 +0000 (16:21 +0200)]
arm: provide a PCS-compliant setjmp implementation

The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
versions of) GCC optimised the set of registers.  One critical example
was the removal of 'r9' from the clobber list, if -ffixed-reg9 was
supplied.

To increase robustness and ensure PCS-compliant behaviour, the setjmp
and longjmp implementation are now in assembly and closely match what
one would expect to find in a libc implementation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
6 years agoarm: mark save_boot_params_ret as a function
Philipp Tomsich [Tue, 10 Oct 2017 14:21:12 +0000 (16:21 +0200)]
arm: mark save_boot_params_ret as a function

As no '.type' was set for save_boot_params_ret in start.S, binutils
did not track whether it was emitted as A32 or T32.  By properly
marking save_boot_params_ret as a potential function entry, we can
make sure that the compiler will insert the appropriate instructions
for branching to save_boot_params_ret both for call-sites emitted as
A32 and T32.

Reported-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
6 years agoarm: make save_boot_params_ret prototype visible for AArch64
Philipp Tomsich [Tue, 10 Oct 2017 14:21:11 +0000 (16:21 +0200)]
arm: make save_boot_params_ret prototype visible for AArch64

The save_boot_params_ret() prototype (for those of us, that have a
valid SP on entry and can implement save_boot_params() in C), was
previously only defined for !defined(CONFIG_ARM64).

This moves the declaration to a common block to ensure the prototype
is available to everyone that might need it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
6 years agorockchip: boot0 hook: support early return for RK3188/RK3066-style BROM
Philipp Tomsich [Tue, 10 Oct 2017 14:21:10 +0000 (16:21 +0200)]
rockchip: boot0 hook: support early return for RK3188/RK3066-style BROM

Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data
from NAND into SRAM and executes it. Then, following a return to bootrom, the
BROM loads additional code to SRAM (not overwriting the first block read) and
reenters at the same address as the first time.

To support booting either a TPL (on the RK3066) or SPL (on the RK3188) using
this model of having to count entries, this commit adds code to the boot0
hook to track the number of entries and handle them accordingly.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
6 years agobcm281xx: boot0 hook: adjust to unified boot0 semantics
Philipp Tomsich [Tue, 10 Oct 2017 14:21:09 +0000 (16:21 +0200)]
bcm281xx: boot0 hook: adjust to unified boot0 semantics

This updates the BCM281xx boot0-hook to the updated boot0 semantics
by emitting _start and the vector table before the boot0 hook (as
was the case before).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agobcm235xx: boot0 hook: adjust to unified boot0 semantics
Philipp Tomsich [Tue, 10 Oct 2017 14:21:08 +0000 (16:21 +0200)]
bcm235xx: boot0 hook: adjust to unified boot0 semantics

This updates the BCM235xx boot0-hook to the updated boot0 semantics
by emitting _start and the vector table before the boot0 hook (as
was the case before).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 5
- ran 'whitespace-cleanup'

6 years agosocfpga: boot0 hook: adjust to unified boot0 semantics
Philipp Tomsich [Tue, 10 Oct 2017 14:21:07 +0000 (16:21 +0200)]
socfpga: boot0 hook: adjust to unified boot0 semantics

With the updated boot0 semantics (i.e. giving the boot0-hook control
over when and where the vector table is emitted), the boot0-hook for
the socfpga needs to be adjusted.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: rk3036: use aligned address for SPL_TEXT_BASE
Philipp Tomsich [Tue, 10 Oct 2017 14:21:06 +0000 (16:21 +0200)]
rockchip: rk3036: use aligned address for SPL_TEXT_BASE

With the boot0-hook inserting the additional padding to receive our
SPL magic, the SPL_TEXT_BASE can be aligned again.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: rk3288: use aligned address for SPL_TEXT_BASE
Kever Yang [Tue, 10 Oct 2017 14:21:05 +0000 (16:21 +0200)]
rockchip: rk3288: use aligned address for SPL_TEXT_BASE

After we use boot0 hook, we can use offset '000' instead of '004' as
SPL_TEXT_BASE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[Updated tag in commit summary:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: mkimage: use spl_boot0 for all Rockchip SoCs
Kever Yang [Tue, 10 Oct 2017 14:21:04 +0000 (16:21 +0200)]
rockchip: mkimage: use spl_boot0 for all Rockchip SoCs

Enable the spl_boot0 in SPL and use the pre-padding TAG memory,
the mkimage do not need to pad it but only need to replace the value
with correct TAG value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[Updated:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: enable boot0-hook for all Rockchip SoCs
Philipp Tomsich [Tue, 10 Oct 2017 14:21:03 +0000 (16:21 +0200)]
rockchip: enable boot0-hook for all Rockchip SoCs

Rockchip SoCs bootrom design is like this:
- First 2KB or 4KB internal memory is for bootrom stack and heap;
- Then the first 4-byte suppose to be a TAG like 'RK33';
- The the following memory address end with '0004' is the first
  instruction load and running by bootrom;

Let's use the boot0 hook to reserve the first 4-byte tag for all
the Rockchip SoCs.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Commit message taken from an older patch by:]
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
6 years agorockchip: boot0: align to 0x20 for armv7 '_start'
Kever Yang [Tue, 10 Oct 2017 14:21:02 +0000 (16:21 +0200)]
rockchip: boot0: align to 0x20 for armv7 '_start'

The '_start' is using as vector table base address, and will write
to VBAR register, so it needs to be aligned to 0x20 for armv7.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[Updated to current code base:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>