oweals/u-boot.git
9 years agoARM: tegra: Enable XUSB pad controller on Jetson TK1
Thierry Reding [Wed, 10 Dec 2014 05:25:11 +0000 (22:25 -0700)]
ARM: tegra: Enable XUSB pad controller on Jetson TK1

Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Add XUSB pad controller on Tegra124
Thierry Reding [Wed, 10 Dec 2014 05:25:10 +0000 (22:25 -0700)]
ARM: tegra: Add XUSB pad controller on Tegra124

The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Implement XUSB pad controller
Thierry Reding [Wed, 10 Dec 2014 05:25:09 +0000 (22:25 -0700)]
ARM: tegra: Implement XUSB pad controller

This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Implement powergate support
Thierry Reding [Wed, 10 Dec 2014 05:25:08 +0000 (22:25 -0700)]
ARM: tegra: Implement powergate support

Implement the powergate API that allows various power partitions to be
power up and down.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Provide PCIEXCLK reset ID
Thierry Reding [Wed, 10 Dec 2014 05:25:07 +0000 (22:25 -0700)]
ARM: tegra: Provide PCIEXCLK reset ID

This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Implement tegra_plle_enable()
Thierry Reding [Wed, 10 Dec 2014 05:25:06 +0000 (22:25 -0700)]
ARM: tegra: Implement tegra_plle_enable()

This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agopower: Add AMS AS3722 PMIC support
Thierry Reding [Wed, 10 Dec 2014 05:25:05 +0000 (22:25 -0700)]
power: Add AMS AS3722 PMIC support

The AS3722 provides a number of DC/DC converters and LDOs as well as 8
GPIOs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: colibri_t30: comment style fix
Marcel Ziswiler [Thu, 2 Oct 2014 16:23:11 +0000 (18:23 +0200)]
ARM: tegra: colibri_t30: comment style fix

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Tue, 16 Dec 2014 20:20:02 +0000 (15:20 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Tue, 16 Dec 2014 14:41:00 +0000 (09:41 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

9 years agoarm: socfpga: board: Repair Micrel PHY tuning
Pavel Machek [Thu, 11 Dec 2014 17:06:31 +0000 (18:06 +0100)]
arm: socfpga: board: Repair Micrel PHY tuning

Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Pavel Machek <pavel@denx.de>
9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Mon, 15 Dec 2014 22:13:47 +0000 (17:13 -0500)]
Merge git://git.denx.de/u-boot-x86

9 years agompc85xx/t104xrdb: convert deep sleep to generic board interface
Tang Yuantian [Fri, 21 Nov 2014 03:17:16 +0000 (11:17 +0800)]
mpc85xx/t104xrdb: convert deep sleep to generic board interface

A new interface is introduced to support generic board structure.
Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoqe/deep-sleep: modify qe deep-sleep for generic board
Zhao Qiang [Mon, 15 Dec 2014 07:50:49 +0000 (15:50 +0800)]
qe/deep-sleep: modify qe deep-sleep for generic board

Deep sleep for generic board is supported now, modify qe
deep-sleep code to adapt it.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agop5040ds: changed liodn offsets
Tudor Laurentiu [Tue, 9 Dec 2014 09:00:19 +0000 (11:00 +0200)]
p5040ds: changed liodn offsets

Offsets were overlaping, causing pamu access violations in
hypervised scenarios.

Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agocrypto/fsl: Fix RNG instantiation failure.
gaurav rana [Thu, 4 Dec 2014 07:30:41 +0000 (13:00 +0530)]
crypto/fsl: Fix RNG instantiation failure.

Corrected the order of arguments in memset in run_descriptor
function. Wrong order of argumnets led to improper initialization
of members of struct type result. This resulted in RNG instantiation
error.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/T10xx: Fix number of portals
Jeffrey Ladouceur [Wed, 3 Dec 2014 23:08:43 +0000 (18:08 -0500)]
powerpc/T10xx: Fix number of portals

Following boards has incorrect number of portals defined.
powerpc/T102xQDS
powerpc/T102xRDB
powerpc/T1040QDS
powerpc/T104xRDB

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agompc85xx: inhibit qman and bman portals by default
Jeffrey Ladouceur [Mon, 8 Dec 2014 19:54:01 +0000 (14:54 -0500)]
mpc85xx: inhibit qman and bman portals by default

Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agonet/fm: update ft_fixup_port to differentiate dual-role mac
Shengzhou Liu [Wed, 3 Dec 2014 07:27:03 +0000 (15:27 +0800)]
net/fm: update ft_fixup_port to differentiate dual-role mac

we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: Fix DDR TLB mapping leftover
York Sun [Tue, 2 Dec 2014 19:21:09 +0000 (11:21 -0800)]
powerpc/mpc85xx: Fix DDR TLB mapping leftover

Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
CC: Scott Wood <scottwood@freescale.com>
9 years agodriver/ddr/fsl: Fix MRC_CYC calculation for DDR3
York Sun [Tue, 2 Dec 2014 19:18:09 +0000 (11:18 -0800)]
driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/p2041rdb: enable generic board configs
Shaohui Xie [Mon, 1 Dec 2014 07:39:23 +0000 (15:39 +0800)]
powerpc/p2041rdb: enable generic board configs

Add following configs in header file:
CONFIG_SYS_GENERIC_BOARD
CONFIG_DISPLAY_BOARDINFO

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4240rdb: Convert to use generic board code
Chunhe Lan [Mon, 1 Dec 2014 08:21:01 +0000 (16:21 +0800)]
powerpc/t4240rdb: Convert to use generic board code

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/bsc913x: Convert to use generic board code
harninder rai [Tue, 2 Dec 2014 10:25:47 +0000 (15:55 +0530)]
powerpc/bsc913x: Convert to use generic board code

Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoARM: remove redundant asmlinkage define
Masahiro Yamada [Wed, 3 Dec 2014 08:36:58 +0000 (17:36 +0900)]
ARM: remove redundant asmlinkage define

Use asmlinkage defined in include/linux/linkage.h if necessary.
Actually no ARM board uses asmlinkage, so this commit has no impact.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
9 years agox86: move arch-specific asmlinkage to <asm/linkage.h>
Masahiro Yamada [Wed, 3 Dec 2014 08:36:57 +0000 (17:36 +0900)]
x86: move arch-specific asmlinkage to <asm/linkage.h>

Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.

Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)

The generic asmlinkage is defined in <linux/linkage.h>.  If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a simple command to show FSP HOB information
Bin Meng [Fri, 12 Dec 2014 13:05:32 +0000 (21:05 +0800)]
x86: Add a simple command to show FSP HOB information

FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.

Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Support Intel FSP initialization path in start.S
Bin Meng [Fri, 12 Dec 2014 13:05:31 +0000 (21:05 +0800)]
x86: Support Intel FSP initialization path in start.S

Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add post failure codes for bist and car
Bin Meng [Fri, 12 Dec 2014 13:05:30 +0000 (21:05 +0800)]
x86: Add post failure codes for bist and car

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: queensbay: Adapt FSP support codes
Bin Meng [Fri, 12 Dec 2014 13:05:29 +0000 (21:05 +0800)]
x86: queensbay: Adapt FSP support codes

Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Initial import from Intel FSP release for Queensbay platform
Bin Meng [Fri, 12 Dec 2014 13:05:28 +0000 (21:05 +0800)]
x86: Initial import from Intel FSP release for Queensbay platform

This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.

For more details, check http://www.intel.com/fsp.

Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: ich-spi: Add Intel Tunnel Creek SPI controller support
Bin Meng [Fri, 12 Dec 2014 13:05:27 +0000 (21:05 +0800)]
x86: ich-spi: Add Intel Tunnel Creek SPI controller support

Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add Intel Topcliff PCH device IDs
Bin Meng [Fri, 12 Dec 2014 13:05:26 +0000 (21:05 +0800)]
x86: Add Intel Topcliff PCH device IDs

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a simple superio driver for SMSC LPC47M
Bin Meng [Fri, 12 Dec 2014 13:05:25 +0000 (21:05 +0800)]
x86: Add a simple superio driver for SMSC LPC47M

On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add Intel Crown Bay board dts file
Bin Meng [Fri, 12 Dec 2014 13:05:24 +0000 (21:05 +0800)]
x86: Add Intel Crown Bay board dts file

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ich6-gpio: Move setup_pch_gpios() to board support codes
Bin Meng [Fri, 12 Dec 2014 13:05:23 +0000 (21:05 +0800)]
x86: ich6-gpio: Move setup_pch_gpios() to board support codes

Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Clean up asm-offsets
Bin Meng [Fri, 12 Dec 2014 13:05:22 +0000 (21:05 +0800)]
x86: Clean up asm-offsets

Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Refactor u-boot.rom build rules
Bin Meng [Fri, 12 Dec 2014 13:05:21 +0000 (21:05 +0800)]
x86: Refactor u-boot.rom build rules

Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ifdtool: Separate out filenames for -D and -i
Simon Glass [Sun, 14 Dec 2014 05:25:46 +0000 (22:25 -0700)]
x86: ifdtool: Separate out filenames for -D and -i

To allow these options to be specified together, separate them out.

Change-Id: Ib93f11cd51eb3302127f4c82936ff2b44c88d5a2
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agotools/ifdtool: Support writing multiple files (-w) simultaneously
Bin Meng [Fri, 12 Dec 2014 13:05:20 +0000 (21:05 +0800)]
tools/ifdtool: Support writing multiple files (-w) simultaneously

Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Make ROM_SIZE configurable in Kconfig
Bin Meng [Fri, 12 Dec 2014 13:05:19 +0000 (21:05 +0800)]
x86: Make ROM_SIZE configurable in Kconfig

Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ich-spi: Set the tx operation mode for ich 7
Bin Meng [Fri, 12 Dec 2014 14:06:16 +0000 (19:36 +0530)]
x86: ich-spi: Set the tx operation mode for ich 7

ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agox86: ich-spi: Set the rx operation mode for ich 7
Bin Meng [Fri, 12 Dec 2014 14:06:15 +0000 (19:36 +0530)]
x86: ich-spi: Set the rx operation mode for ich 7

ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agosf: Enable byte program support
Jagannadha Sutradharudu Teki [Fri, 12 Dec 2014 14:06:14 +0000 (19:36 +0530)]
sf: Enable byte program support

Enabled byte program support for sst flashes in sf.

Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agospi: sf: Support byte program for sst spi flash
Bin Meng [Fri, 12 Dec 2014 14:06:13 +0000 (19:36 +0530)]
spi: sf: Support byte program for sst spi flash

Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agospi: Fix flag collision for SST_WP
Simon Glass [Fri, 12 Dec 2014 14:06:12 +0000 (19:36 +0530)]
spi: Fix flag collision for SST_WP

At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.

Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agosf: Fix look for the fastest read command
Jagannadha Sutradharudu Teki [Fri, 12 Dec 2014 14:06:11 +0000 (19:36 +0530)]
sf: Fix look for the fastest read command

Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.

So this fix on sf will correctly handle the slow read supported
controllers.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agobios_emulator: Correct ordering of includes
Simon Glass [Thu, 11 Dec 2014 03:12:01 +0000 (20:12 -0700)]
bios_emulator: Correct ordering of includes

We should include common.h before other includes. This actually causes
a build error on chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agogpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()
Axel Lin [Sun, 7 Dec 2014 04:48:27 +0000 (12:48 +0800)]
gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()

Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
Bin Meng [Wed, 10 Dec 2014 08:35:50 +0000 (16:35 +0800)]
x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address

The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mmc
Tom Rini [Fri, 12 Dec 2014 20:02:00 +0000 (15:02 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mmc

9 years agommc: dw_mmc: Use active DDR mode flag
Andrew Gabbasov [Mon, 1 Dec 2014 12:59:12 +0000 (06:59 -0600)]
mmc: dw_mmc: Use active DDR mode flag

The card_caps bit should denote the card capability to use DDR mode,
but we need the flag indicating that the DDR mode is active.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
9 years agommc: Fix block length for DDR mode
Andrew Gabbasov [Mon, 1 Dec 2014 12:59:11 +0000 (06:59 -0600)]
mmc: Fix block length for DDR mode

Block length for write and read commands is fixed to 512 bytes
when the card is in Dual Data Rate mode. If block length read from CSD
is different, make sure the driver will use correct length
in all further calculations and settings.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
9 years agommc: Fix Dual Data Rate capability recognition
Andrew Gabbasov [Mon, 1 Dec 2014 12:59:10 +0000 (06:59 -0600)]
mmc: Fix Dual Data Rate capability recognition

Since the driver doesn't work in 1.2V or 1.8V signaling level modes,
Dual Data Rate mode can be supported by the driver only if it is supported
by the card in regular 3.3V mode. So, check for a particular single
bit in card type field.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
9 years agommc: Fix handling of bus widths and DDR card capabilities
Andrew Gabbasov [Mon, 1 Dec 2014 12:59:09 +0000 (06:59 -0600)]
mmc: Fix handling of bus widths and DDR card capabilities

If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.

Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.

This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.

Also, some clean up is made with errors handling and code syntax layout.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
9 years agommc: exynos_dw-mmc: change debug message
Jaehoon Chung [Fri, 28 Nov 2014 11:42:33 +0000 (20:42 +0900)]
mmc: exynos_dw-mmc: change debug message

To debug more exactly, add the index for device.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
9 years agoMMC: add MMC_VERSION_5_0
Markus Niebel [Tue, 18 Nov 2014 14:13:53 +0000 (15:13 +0100)]
MMC: add MMC_VERSION_5_0

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
9 years agoMMC: fix user capacity for partitioned eMMC card
Markus Niebel [Tue, 18 Nov 2014 14:11:42 +0000 (15:11 +0100)]
MMC: fix user capacity for partitioned eMMC card

if the card claims to be high capacity and the card
is partitioned the capacity shall still be read from
ext_csd SEC_COUNT even if the resulting capacity is
smaller than 2 GiB

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
9 years agommc: Cosmetic fix for nicer, aligned device list printout
Lubomir Popov [Tue, 11 Nov 2014 10:25:42 +0000 (12:25 +0200)]
mmc: Cosmetic fix for nicer, aligned device list printout

If print_mmc_devices() was called with a '\n' separator (as done
for example by the "mmc list" command), it offset the 2-nd and
all subsequent lines by one space. Fixing this.

Signed-off-by: Lubomir Popov <l-popov@ti.com>
9 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Fri, 12 Dec 2014 01:47:34 +0000 (20:47 -0500)]
Merge git://git.denx.de/u-boot-dm

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Thu, 11 Dec 2014 23:40:49 +0000 (18:40 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

Conflicts:
board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Thu, 11 Dec 2014 23:28:09 +0000 (18:28 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

9 years agoARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7i
Xiubo Li [Thu, 11 Dec 2014 19:15:26 +0000 (11:15 -0800)]
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7i

Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ.
It should be CONFIG_TIMER_CLK_FREQ.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
[York Sun: This is the difference between two patch versions]
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodm: i2c: tegra: Convert to driver model
Simon Glass [Wed, 10 Dec 2014 15:55:57 +0000 (08:55 -0700)]
dm: i2c: tegra: Convert to driver model

This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoARM: tegra: Add support for nyan-big board
Allen Martin [Thu, 4 Dec 2014 13:36:30 +0000 (06:36 -0700)]
ARM: tegra: Add support for nyan-big board

Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.

This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.

The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)

9 years agotegra: dts: Sync tegra124.dtsi with linux kernel
Simon Glass [Thu, 4 Dec 2014 13:36:29 +0000 (06:36 -0700)]
tegra: dts: Sync tegra124.dtsi with linux kernel

Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
9 years agodts: Bring in Chrome OS keyboard device tree definition
Simon Glass [Thu, 4 Dec 2014 13:36:28 +0000 (06:36 -0700)]
dts: Bring in Chrome OS keyboard device tree definition

This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodm: device: Add newline to debug() messages
Simon Glass [Wed, 10 Dec 2014 15:55:56 +0000 (08:55 -0700)]
dm: device: Add newline to debug() messages

Some of these are missing a newline. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodm: i2c: Add tests for I2C
Simon Glass [Wed, 10 Dec 2014 15:55:55 +0000 (08:55 -0700)]
dm: i2c: Add tests for I2C

Add some basic tests to check that the system works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
9 years agodm: Add a simple EEPROM driver
Simon Glass [Wed, 10 Dec 2014 15:55:54 +0000 (08:55 -0700)]
dm: Add a simple EEPROM driver

There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agodm: i2c: dts: Add an I2C bus for sandbox
Simon Glass [Wed, 10 Dec 2014 15:55:53 +0000 (08:55 -0700)]
dm: i2c: dts: Add an I2C bus for sandbox

Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agodm: i2c: config: Enable I2C for sandbox using driver model
Simon Glass [Wed, 10 Dec 2014 15:55:52 +0000 (08:55 -0700)]
dm: i2c: config: Enable I2C for sandbox using driver model

Enable the options to bring up I2C on sandbox. Also enable all the available
I2C commands for testing purposes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
9 years agodm: i2c: Add an I2C EEPROM simulator
Simon Glass [Wed, 10 Dec 2014 15:55:51 +0000 (08:55 -0700)]
dm: i2c: Add an I2C EEPROM simulator

To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agodm: i2c: Add a sandbox I2C driver
Simon Glass [Wed, 10 Dec 2014 15:55:50 +0000 (08:55 -0700)]
dm: i2c: Add a sandbox I2C driver

This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agodm: i2c: Add I2C emulation driver for sandbox
Simon Glass [Wed, 10 Dec 2014 15:55:49 +0000 (08:55 -0700)]
dm: i2c: Add I2C emulation driver for sandbox

In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agodm: i2c: Implement driver model support in the i2c command
Simon Glass [Wed, 10 Dec 2014 15:55:48 +0000 (08:55 -0700)]
dm: i2c: Implement driver model support in the i2c command

The concept of a 'current bus' is now implemented in the command line
rather than in the uclass. Also the address length does not need to
be specified with each command - really we should consider dropping
this from most commands but it works OK for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agodm: i2c: Add a uclass for I2C
Simon Glass [Wed, 10 Dec 2014 15:55:47 +0000 (08:55 -0700)]
dm: i2c: Add a uclass for I2C

The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:

- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions

Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agolib: errno: introduce errno_str(): returns errno related message
Przemyslaw Marczak [Wed, 8 Oct 2014 20:48:37 +0000 (22:48 +0200)]
lib: errno: introduce errno_str(): returns errno related message

The functions error's numbers are standarized - but the error
messages are not.

The errors are often handled with unclear error messages,
so why not use an errno standarized messages.

Advantages:
- This could decrease the binary size.
- Appended with a detailed information,
  the error message will be clear.

This commit introduces new function:
- const char *errno_to_str(int errno)

The functions returns a pointer to the errno corresponding text message:
- if errno is null or positive number - a pointer to "Success" message
- if errno is negative - a pointer to errno related message

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Tom Rini <trini@ti.com>
9 years agodm: rpi: Move serial to driver model
Simon Glass [Tue, 25 Nov 2014 04:36:34 +0000 (21:36 -0700)]
dm: rpi: Move serial to driver model

Adjust the configuration to use the driver model version of the pl01x
serial driver. Add the required platform data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
9 years agodm: serial_pl01x: Add missing private data size
Simon Glass [Tue, 25 Nov 2014 04:36:35 +0000 (21:36 -0700)]
dm: serial_pl01x: Add missing private data size

The private data size is missing from the driver, so we store it at 0,
which causes problems when something overwrites memory at 0.

Fix this.

Change-Id: I6f551ee905b0064ae8343e41e46450c37c8c8c1a
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
9 years agodm_test: improve the appearance shown by "dm tree" command
Masahiro Yamada [Sat, 29 Nov 2014 08:01:56 +0000 (17:01 +0900)]
dm_test: improve the appearance shown by "dm tree" command

The command "dm tree" lists devices in a tree-like format.
This commit makes it look more like what the Unix command "tree"
shows.

=> dm tree
 Class       Probed   Name
----------------------------------------
 root        [ + ]    root_driver
 demo        [   ]    |-- demo_shape_drv
 demo        [   ]    |-- demo_simple_drv
 demo        [   ]    |-- demo_shape_drv
 demo        [   ]    |-- demo_simple_drv
 demo        [   ]    |-- demo_shape_drv
 test        [   ]    |-- test_drv
 test        [   ]    |-- test_drv
 test        [   ]    |-- test_drv
 gpio        [   ]    |-- gpio_sandbox
 serial      [   ]    |-- serial_sandbox
 serial      [ + ]    |-- serial
 demo        [   ]    |-- triangle
 demo        [   ]    |-- square
 demo        [   ]    |-- hexagon
 gpio        [   ]    |-- gpios
 spi         [   ]    |-- spi@0
 spi_emul    [   ]    |   `-- flash@0
 cros_ec     [ + ]    `-- cros-ec@0

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agolib: string: move strlcpy() to a common place
Masahiro Yamada [Thu, 20 Nov 2014 12:20:32 +0000 (21:20 +0900)]
lib: string: move strlcpy() to a common place

Move strlcpy() definition from drivers/usb/gadget/ether.c to
lib/string.c because it is a very useful function.
Let's add the prototype to include/linux/string.h too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agokconfig: ls102xa: Change the prompt messages
Alison Wang [Wed, 3 Dec 2014 08:18:09 +0000 (16:18 +0800)]
kconfig: ls102xa: Change the prompt messages

As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodriver/mtd: Fix IFC compilation warnings
Jaiprakash Singh [Thu, 27 Nov 2014 07:08:12 +0000 (12:38 +0530)]
driver/mtd: Fix IFC compilation warnings

'eccstat' array elements might be used uninitialized

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoARM: ls102xa: Setting device's stream id for SMMUs.
Xiubo Li [Fri, 21 Nov 2014 09:40:59 +0000 (17:40 +0800)]
ARM: ls102xa: Setting device's stream id for SMMUs.

LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoARM: ls102xa: allow all the peripheral access permission as R/W.
Xiubo Li [Fri, 21 Nov 2014 09:40:58 +0000 (17:40 +0800)]
ARM: ls102xa: allow all the peripheral access permission as R/W.

The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agols102xa: changing a few targets' configurations.
Xiubo Li [Fri, 21 Nov 2014 09:40:57 +0000 (17:40 +0800)]
ls102xa: changing a few targets' configurations.

Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agols1021a: adding a secondary core boot address and kick functions
Xiubo Li [Fri, 21 Nov 2014 09:40:56 +0000 (17:40 +0800)]
ls1021a: adding a secondary core boot address and kick functions

Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.

Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
Xiubo Li [Fri, 21 Nov 2014 09:40:55 +0000 (17:40 +0800)]
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.

For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.

This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoARM: HYP/non-sec: add the pen address BE mode support.
Xiubo Li [Fri, 21 Nov 2014 09:40:54 +0000 (17:40 +0800)]
ARM: HYP/non-sec: add the pen address BE mode support.

For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.

This patch adds BE mode support for smp pen address.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agofsl/sleep: updated the deep sleep framework for QorIQ platforms
Tang Yuantian [Fri, 21 Nov 2014 03:17:15 +0000 (11:17 +0800)]
fsl/sleep: updated the deep sleep framework for QorIQ platforms

With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers: usb: fsl: Check USB Erratum A007792 applicability
Nikhil Badola [Thu, 30 Oct 2014 04:41:28 +0000 (10:11 +0530)]
drivers: usb: fsl: Check USB Erratum A007792 applicability

Check USB Erratum A007792 applicability. If applicable, add
corresponding  property in the device tree via device tree fixup

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers: usb: fsl: Add USB device-tree errata framework
Nikhil Badola [Tue, 30 Sep 2014 05:54:07 +0000 (11:24 +0530)]
drivers: usb: fsl: Add USB device-tree errata framework

Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers: usb: Make usb device-tree fixup code architecture independent
Nikhil Badola [Mon, 20 Oct 2014 11:20:49 +0000 (16:50 +0530)]
drivers: usb: Make usb device-tree fixup code architecture independent

move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agols1021aqds: add hwconfig setting to do pin mux
Yao Yuan [Wed, 26 Nov 2014 06:54:33 +0000 (14:54 +0800)]
ls1021aqds: add hwconfig setting to do pin mux

The Freescale LS1021AQDS share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.

The main pin mux IP is:
eSDHC, SAI, IIC2, RGMII, CAN, SAI.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Add NAND boot support for LS1021AQDS board
Alison Wang [Tue, 9 Dec 2014 09:38:14 +0000 (17:38 +0800)]
arm: ls102xa: Add NAND boot support for LS1021AQDS board

This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
Alison Wang [Tue, 9 Dec 2014 09:38:02 +0000 (17:38 +0800)]
arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board

This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE support
Alison Wang [Tue, 9 Dec 2014 09:37:49 +0000 (17:37 +0800)]
arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE support

The SD/NAND/QSPI boot definations are wrong for QE support, this
patch is to fix this error.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT support
Alison Wang [Tue, 9 Dec 2014 09:37:34 +0000 (17:37 +0800)]
arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT support

This patch will fix the bug that the partitions on the SD card could
not be accessed and add the support for the FAT fs.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Add SD boot support for LS1021ATWR board
Alison Wang [Wed, 3 Dec 2014 07:00:48 +0000 (15:00 +0800)]
arm: ls102xa: Add SD boot support for LS1021ATWR board

This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>