oweals/u-boot.git
10 years agozynq-common: Enable verified boot(RSA)
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:28 +0000 (01:48 +0530)]
zynq-common: Enable verified boot(RSA)

CONFIG_FIT_SIGNATURE - signature node support in FIT image
CONFIG_RSA - RSA lib support

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agogpio: zynq: Add dummy gpio routines
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:27 +0000 (01:48 +0530)]
gpio: zynq: Add dummy gpio routines

GPIO dummy routines are required for fdt build, may be removed
these dependencies once the u-boot fdt is fully optimized.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agodts: zynq: Add basic fdt support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:26 +0000 (01:48 +0530)]
dts: zynq: Add basic fdt support

This patch provides a basic fdt support for zynq u-boot.

zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.

u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zed

Enabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq-common: Define CONFIG_ENV_OVERWRITE
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:25 +0000 (01:48 +0530)]
zynq-common: Define CONFIG_ENV_OVERWRITE

Defined CONFIG_ENV_OVERWRITE, which allow to
overwrite serial baudrate and ethaddr.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq-common: Define flash env. partition
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:24 +0000 (01:48 +0530)]
zynq-common: Define flash env. partition

Last 128Kb sector of 1Mb flash is defined as u-boot
environment partition.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq-common: Change Env. Sector size to 128Kb
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:23 +0000 (01:48 +0530)]
zynq-common: Change Env. Sector size to 128Kb

Changed Env. Sector size from 0x10000 to 128Kb

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq-common: Define default environment
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:22 +0000 (01:48 +0530)]
zynq-common: Define default environment

Defined default env. for autoboot FIT image from
respective boot devices.

Default settings:
fit_image=fit.itb
load_addr=0x2000000
fit_size=0x800000
flash_off=0x100000
nor_flash_off=0xE2100000

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add support to find bootmode
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:21 +0000 (01:48 +0530)]
zynq: Add support to find bootmode

Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.

Added this functionality on board_late_init as it's not
needed for normal initializtion part.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add zynq_zc770 xm012 board support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:20 +0000 (01:48 +0530)]
zynq: Add zynq_zc770 xm012 board support

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM012:
- 1GB DDR3
- 64MiB Numonyx NOR flash
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
10 years agozynq: Add zynq_zc770 xm013 board support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:19 +0000 (01:48 +0530)]
zynq: Add zynq_zc770 xm013 board support

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM013:
- 1GB DDR3
- 128 Mb Quad-SPI Flash(dual parallel)
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add zynq_zc770 xm010 board support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:18 +0000 (01:48 +0530)]
zynq: Add zynq_zc770 xm010 board support

ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013

ZC770 XM010:
- 1Gb DDR3
- 1Mb SST SPI flash
- 128 Mb Quad-SPI Flash
- 8 Mb SST SI flash
- Full size SD/MMC card cage
- 10/100/1000 Ethernet
- USB-UART

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add zynq microzed board support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:17 +0000 (01:48 +0530)]
zynq: Add zynq microzed board support

MicroZed is a low-cost development board based on
the Xilinx Zynq-7000 All Programmable SoC.

APSOC:
- XC7Z010-1CLG400C
Memory:
- 1 GB of DDR3 SDRAM
- 128Mb of QSPI flash(S25FL128SAGBHI200)
- Micro SD card interface
Communication:
- 10/100/1000 Ethernet
- USB 2.0
- USB-UART
User I/O:
- 100 User I/O (50 per connector)
- Configurable as up to 48 LVDS pairs or 100 single-ended I/O
Misc:
- Xilinx PC4 JTAG configuration port
- PS JTAG pins accessible via Pmod
- 33.33 MHz oscillator
- User LED and push switch

For more info - http://zedboard.org/product/microzed

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: zc70x: Add Catalyst 24WC08 EEPROM config support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:16 +0000 (01:48 +0530)]
zynq: zc70x: Add Catalyst 24WC08 EEPROM config support

Adds configurations for Catalyst 24WC08 EEPROM, which
is present on the zynq boards.

Enable EEPROM support for zc70x boards.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq-common: Define exact TEXT_BASE
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:15 +0000 (01:48 +0530)]
zynq-common: Define exact TEXT_BASE

Defined TEXT_BASE for u-boot starts from 0x4000000
w.r.t zynq memory-map.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:14 +0000 (01:48 +0530)]
zynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs

CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved
to specific pre-config board files.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add zynq zed board support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:13 +0000 (01:48 +0530)]
zynq: Add zynq zed board support

Zed is a complete development board based on the
Xilinx Zynq-7000 All Programmable SoC.

APSOC:
- XC7Z020-CLG484-1
Memory:
- 512 MB DDR3
- 256 Mb Quad-SPI Flash(
- Full size SD/MMC card cage
Connectivity:
- 10/100/1000 Ethernet
- USB OTG (Device/Host/OTG)
- USB-UART
Expansion:
- FMC (Low Pin Count)
- Pmod. headers (2x6)
Video/Display:
- HDMI output (1080p60 + audio)
- VGA connector
- 128 x 32 OLED
- User LEDs (9)
User inputs:
- Slide switches (8)
- Push button switches (7)
Audio:
- 24-bit stereo audio CODEC
- Stereo line in/out
- Headphone
- Microphone input
Analog:
- Xilinx XADC header
- Supports 4 analog inputs
- 2 Differential / 4 Single-ended
Debug:
- On-board USB JTAG programming port
- ARM Debug Access Port (DAP)

For more info - http://zedboard.org/product/zedboard

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add zynq zc70x board support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:12 +0000 (01:48 +0530)]
zynq: Add zynq zc70x board support

The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded
processing includes ASIC and FPGA design.

ZC702-:

APSOC:
- XC7Z020-CLG484-1
Memory:
- DDR3 Component Memory 1GB
- 16MB Quad SPI Flash
- IIC - 1 KB EEPROM
Connectivity:
- Gigabit Ethernet GMII, RGMII and SGMII.
- USB OTG - Host USB
- IIC Bus Headers/HUB
- 1 CAN with Wake on CAN
- USB-UART
Video/Display:
- HDMI Video OUT
- 8X LEDs
Control & I/O:
- 3 User Push Buttons
- 2 User Switches
- 8 User LEDs

For more info on zc702 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm

ZC706-:

APSOC:
- XC7Z045 FFG900 -2 AP SoC
Memory:
- DDR3 Component Memory 1GB (PS)
- DDR3 SODIM Memory 1GB (PL)
- 2X16MB Quad SPI Flash (dual parallel)
- IIC - 1 KB EEPROM
Connectivity:
- PCIe Gen2x4
- SFP+ and SMA Pairs
- GigE RGMII Ethernet (PS)
- USB OTG 1 (PS) - Host USB
- IIC Bus Headers/HUB (PS)
- 1 CAN with Wake on CAN (PS)
- USB-UART
Video/Display:
- HDMI 8 color RGB 4.4.4 1080P-60 OUT
- HDMI IN 8 color RGB 4.4.4
Control & I/O:
- 2 User Push Buttons/Dip Switch, 2 User LEDs
- IIC access to GPIO
- SDIO (SD Card slot)
- 3 User Push Buttons, 2 User Switches, 8 User LEDs

For more info on zc706 board:
- http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agodoc: zynq: Add information on zynq u-boot
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:11 +0000 (01:48 +0530)]
doc: zynq: Add information on zynq u-boot

Information on zynq u-boot about
- zynq boards
- mainline status
- TODO

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq-common: Rename zynq with zynq-common
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:10 +0000 (01:48 +0530)]
zynq-common: Rename zynq with zynq-common

zynq.h -> zynq-common.h, zynq-common is Common
configuration options for all Zynq boards.

zynq.h is no longer exists hense removed from boards.cfg

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add GEM0, GEM1 configs support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:09 +0000 (01:48 +0530)]
zynq: Add GEM0, GEM1 configs support

Zynq ethernet controller support two GEM's like
CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled
both so-that the respective board will define
these macros based on their usage.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Add UART0, UART1 configs support
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:08 +0000 (01:48 +0530)]
zynq: Add UART0, UART1 configs support

Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Enable cache options
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:07 +0000 (01:48 +0530)]
zynq: Enable cache options

- Enable cache command
- Turn-off L2 cache
- Turn-on D-cache

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Minor config cleanup
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:06 +0000 (01:48 +0530)]
zynq: Minor config cleanup

Cleanups mostly on:
- Add comments
- Re-order configs
- Remove #define CONFIG_ZYNQ_SDHCI

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Cleanup on memory configs
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:05 +0000 (01:48 +0530)]
zynq: Cleanup on memory configs

Cleanup on memory configuration options:
- Add comment
- Re-order configs

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Cleanup on miscellaneous configs
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:04 +0000 (01:48 +0530)]
zynq: Cleanup on miscellaneous configs

Cleanup on miscellaneous configurable options:
- Rename SYS_PROMPT as "zynq-uboot"
- Add comment
- Re-order configs

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Enable Boot FreeBSD/vxWorks
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:03 +0000 (01:48 +0530)]
zynq: Enable Boot FreeBSD/vxWorks

This enabled Boot FreeBSD/vxWorks from an ELF image support

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agozynq: Enable CONFIG_FIT_VERBOSE
Jagannadha Sutradharudu Teki [Wed, 8 Jan 2014 20:18:02 +0000 (01:48 +0530)]
zynq: Enable CONFIG_FIT_VERBOSE

Enabled fit_format_{error,warning}()

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
10 years agoarm: make 'MAKEALL -a' distinguish between arm and aarch64
Albert ARIBAUD [Fri, 10 Jan 2014 09:19:45 +0000 (10:19 +0100)]
arm: make 'MAKEALL -a' distinguish between arm and aarch64

The vexpress_aemv8a is the first aarch64 board in U-Boot.
As it was introduced, it gets built when "MAKEALL -a arm"
is invoked, and fails as this command is run with a 32-bit,
not 64-bit, toolchain as the cross-compiler.

Introduce 'aarch64' as a valid 'MAKEALL -a' argument, treated
as 'arm' for all other intents, and change the architecture
of the vexpress_aemv8a entry in boards.cfg from 'arm' to
'aarch64'.

10 years agoarmv8: Use __aarch64__ rather than CONFIG_ARM64 in some cases
Tom Rini [Thu, 9 Jan 2014 20:11:27 +0000 (15:11 -0500)]
armv8: Use __aarch64__ rather than CONFIG_ARM64 in some cases

The toolchain sets __aarch64__ for both LE and BE.  In the case of
posix_types.h we cannot reliably use config.h as that will lead to
problems.  In the case of byteorder.h it's clearer to check the EB flag
being set in either case instead.

Cc: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Tom Rini <trini@ti.com>
Amended by Albert ARIBAUD <albert.u.boot@aribaud.net> to
actually remove the config.h include from the posix_types.h
files, with permission from Tom Rini.

10 years agoarm64: MAKEALL, filter armv8 boards from LIST_arm
David Feng [Sat, 14 Dec 2013 03:47:38 +0000 (11:47 +0800)]
arm64: MAKEALL, filter armv8 boards from LIST_arm

Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agoarm64: board support of vexpress_aemv8a
David Feng [Sat, 14 Dec 2013 03:47:37 +0000 (11:47 +0800)]
arm64: board support of vexpress_aemv8a

Signed-off-by: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
10 years agoarm64: generic board support
David Feng [Sat, 14 Dec 2013 03:47:36 +0000 (11:47 +0800)]
arm64: generic board support

Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agoarm64: core support
David Feng [Sat, 14 Dec 2013 03:47:35 +0000 (11:47 +0800)]
arm64: core support

Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agoarm64: Make checkarmreloc accept arm64 relocations
Scott Wood [Sat, 14 Dec 2013 03:47:34 +0000 (11:47 +0800)]
arm64: Make checkarmreloc accept arm64 relocations

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agoarm64: Turn u-boot.bin back into an ELF file after relocate-rela
Scott Wood [Sat, 14 Dec 2013 03:47:33 +0000 (11:47 +0800)]
arm64: Turn u-boot.bin back into an ELF file after relocate-rela

While performing relocations on u-boot.bin should be good enough for
booting on real hardware, some simulators insist on booting an ELF file
(and yet don't perform ELF relocations), so convert the relocated
binary back into an ELF file.  This can go away in the future if we
change relocate-rela to operate directly on the ELF file, or if and
when we stop caring about a simulator with this restriction.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agoarm64: Add tool to statically apply RELA relocations
Scott Wood [Sat, 14 Dec 2013 03:47:32 +0000 (11:47 +0800)]
arm64: Add tool to statically apply RELA relocations

ARM64 uses the newer RELA-style relocations rather than the older REL.
RELA relocations have an addend in the relocation struct, rather than
expecting the loader to read a value from the location to be updated.

While this is beneficial for ordinary program loading, it's problematic
for U-Boot because the location to be updated starts out with zero,
rather than a pre-relocation value.  Since we need to be able to run C
code before relocation, we need a tool to apply the relocations at
build time.

In theory this tool is applicable to other newer architectures (mainly
64-bit), but currently the only relocations it supports are for arm64,
and it assumes a 64-bit little-endian target.  If the latter limitation
is ever to be changed, we'll need a way to tell the tool what format
the image is in.  Eventually this may be replaced by a tool that uses
libelf or similar and operates directly on the ELF file.  I've written
some code for such an approach but libelf does not make it easy to poke
addresses by memory address (rather than by section), and I was
hesitant to write code to manually parse the program headers and do the
update outside of libelf (or to iterate over sections) -- especially
since it wouldn't get test coverage on things like binaries with
multiple PT_LOAD segments.  This should be good enough for now to let
the manual relocation stuff be removed from the arm64 patches.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agoadd weak entry definition
David Feng [Sat, 14 Dec 2013 03:47:31 +0000 (11:47 +0800)]
add weak entry definition

Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agocmd_pxe: remove compiling warnings
David Feng [Sat, 14 Dec 2013 03:47:30 +0000 (11:47 +0800)]
cmd_pxe: remove compiling warnings

Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agofdt_support: 64bit initrd start address support
David Feng [Sat, 14 Dec 2013 03:47:29 +0000 (11:47 +0800)]
fdt_support: 64bit initrd start address support

Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agoMerge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Albert ARIBAUD [Wed, 8 Jan 2014 19:48:26 +0000 (20:48 +0100)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

10 years agoARM: dra7_evm: read mac address properly from e-fuse
Mugunthan V N [Tue, 7 Jan 2014 14:27:38 +0000 (19:57 +0530)]
ARM: dra7_evm: read mac address properly from e-fuse

Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is
not working on some boards, modifying the offset to read properly.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
10 years agoarm: omap: cm_t35: enable gpio bank 5 clocks explicitly
Nikita Kiryanov [Tue, 31 Dec 2013 10:55:15 +0000 (12:55 +0200)]
arm: omap: cm_t35: enable gpio bank 5 clocks explicitly

Following commit "arm: omap3: Enable clocks for peripherals only if they are
used" (f33b9bd3984fb11e1d8566a866adc5957b1e1c9d) it is now necessary to enable
clocks for GPIO banks explicitly. On cm_t35, GPIO bank 5 is necessary for
scf0403 lcd support.

Enable GPIO bank 5 clocks.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
10 years agoARM: twister: add missing gpio clock init
Jeroen Hofstee [Sat, 21 Dec 2013 17:06:33 +0000 (18:06 +0100)]
ARM: twister: add missing gpio clock init

Commit f33b9bd3984fb11e1d8566a866adc5957b1e1c9d breaks boards
which do not explicitly enable the gpio clocks. This causes
the twister spl to hang, since it uses the no longer enabled
gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agoARM: tam3517-common: fix nand spl boot
Jeroen Hofstee [Sat, 21 Dec 2013 17:03:09 +0000 (18:03 +0100)]
ARM: tam3517-common: fix nand spl boot

commit f9095aac793aa8917ab9b915c5d449e6dc8d3d30, "mtd: nand:
omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme"
removed CONFIG_SPL_NAND_SOFTECC from the tam3517 common config,
causing the spl nand boot to fail. Add it back, so derived
boards boot again.

Cc: Pekon Gupta <pekon@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Raphael Assenat <raph@8d.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agoTI:omap3: Drop omap3_zoom2
Tom Rini [Fri, 20 Dec 2013 16:19:33 +0000 (11:19 -0500)]
TI:omap3: Drop omap3_zoom2

The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.

Signed-off-by: Tom Rini <trini@ti.com>
10 years agocam_enc_4xx: Set CONFIG_SYS_NAND_MAX_OOBFREE / CONFIG_SYS_NAND_MAX_ECCPOS
Tom Rini [Wed, 18 Dec 2013 19:43:08 +0000 (14:43 -0500)]
cam_enc_4xx: Set CONFIG_SYS_NAND_MAX_OOBFREE / CONFIG_SYS_NAND_MAX_ECCPOS

With the changes to make OOBFREE/ECCPOS configurable but default to
larger, we need to set these config options for the space savings they
provide.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
10 years agoarm/km: fix i2c mux define for km_kirkwood_128m16 target
Holger Brunck [Mon, 7 Oct 2013 13:10:03 +0000 (15:10 +0200)]
arm/km: fix i2c mux define for km_kirkwood_128m16 target

Due to the i2c mux rework in u-boot we now have only to specify the
busnumber and not the whole mux configuration.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
10 years agoarm/km: add support for km_kirkwood_128m16 board
Karlheinz Jerg [Wed, 18 Sep 2013 07:32:48 +0000 (09:32 +0200)]
arm/km: add support for km_kirkwood_128m16 board

The board is similar to the standard km_kirkwood board. From a
u-boot point of view, the only difference is an increased
256 MiB DRAM (128M16). A board based on this design is for
example the SUP12.

Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
10 years agokirkwood: ib62x0: use device tree and update config
Luka Perkov [Thu, 31 Oct 2013 03:05:05 +0000 (04:05 +0100)]
kirkwood: ib62x0: use device tree and update config

Signed-off-by: Luka Perkov <luka@openwrt.org>
CC: Prafulla Wadaskar <prafulla@marvell.com>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
10 years agoMerge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 6 Jan 2014 08:32:42 +0000 (09:32 +0100)]
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

10 years agoMerge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 6 Jan 2014 07:49:58 +0000 (08:49 +0100)]
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

Conflicts:
include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.

10 years agoarm: mx5: Add fuse supply enable in fsl_iim
Sergey Alyoshin [Tue, 17 Dec 2013 19:24:54 +0000 (23:24 +0400)]
arm: mx5: Add fuse supply enable in fsl_iim

Enable fuse supply before fuse programming and disable after.

Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
10 years agoARM: mx6: Allow enablement of FEC Anatop based clock for all MX6
Otavio Salvador [Mon, 16 Dec 2013 22:44:05 +0000 (20:44 -0200)]
ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6

The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agoARM: mx6: Change the FDT loading address to avoid overlaping
Otavio Salvador [Mon, 16 Dec 2013 22:44:04 +0000 (20:44 -0200)]
ARM: mx6: Change the FDT loading address to avoid overlaping

This patch fixes allow for the DeviceTree and initrd relocation fixing
the boot of FSL 3.10.9-1.0.0-alpha kernel.

This changes following boards:

 - mx6sabreauto
 - mx6sabresd
 - wandboard
 - udoo
 - nitrogen6x
 - cgtqmx6eval

The reasoning, as explained by Hui Liu, is:

,----
| The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel
| Boot up, it will decompress the compressed kernel image and place the decompressed
| kernel image at the low end of the DDR memory and start running from it. If the
| decompressed kernel image is bigger for example than 16M, it may over written the
| fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000
|
| To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override
| Since we will not likely have one kernel image larger than 128MB.
`----

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agomx28evk: Extend environment to easy write of NAND system
Otavio Salvador [Mon, 16 Dec 2013 22:44:03 +0000 (20:44 -0200)]
mx28evk: Extend environment to easy write of NAND system

This adds following new targets:

 - update_nand_kernel
 - update_nand_fdt
 - update_nand_filesystem

and to avoid confusion, the 'update_nand_full' has been renamed to
'update_nand_firmware_full'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
10 years agomx28evk: Add 'nandboot' environment command
Otavio Salvador [Mon, 16 Dec 2013 22:44:02 +0000 (20:44 -0200)]
mx28evk: Add 'nandboot' environment command

This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx28evk: Use 512k for fdt partition to align it
Otavio Salvador [Mon, 16 Dec 2013 22:44:01 +0000 (20:44 -0200)]
mx28evk: Use 512k for fdt partition to align it

Using 512k for fdt partition allow it to be aligned with the other
small partitions and 512k erase block size.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agoimx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro
Otavio Salvador [Mon, 16 Dec 2013 22:44:00 +0000 (20:44 -0200)]
imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro

The macro allows easy setting in per-pin, as for example:

,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----

The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.

The following quote from the datasheet:

,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----

This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.

Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio
Estevam <fabio.estevam@freescale.com> and Eric Bénard
<eric@eukrea.com> for helping to properly trace this down.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agomx6: soc: Disable VDDPU regulator
Fabio Estevam [Thu, 26 Dec 2013 16:51:35 +0000 (14:51 -0200)]
mx6: soc: Disable VDDPU regulator

As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: soc: Add the required LDO ramp up delay
Fabio Estevam [Thu, 26 Dec 2013 16:51:34 +0000 (14:51 -0200)]
mx6: soc: Add the required LDO ramp up delay

When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: soc: Introduce set_ldo_voltage()
Fabio Estevam [Thu, 26 Dec 2013 16:51:33 +0000 (14:51 -0200)]
mx6: soc: Introduce set_ldo_voltage()

Introduce set_ldo_voltage() so that all three LDO regulators can be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: soc: Set the VDDSOC at 1.175 V
Fabio Estevam [Thu, 26 Dec 2013 16:51:32 +0000 (14:51 -0200)]
mx6: soc: Set the VDDSOC at 1.175 V

mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages
Fabio Estevam [Thu, 26 Dec 2013 16:51:31 +0000 (14:51 -0200)]
mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages

Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: soc: Staticize set_vddsoc()
Fabio Estevam [Thu, 26 Dec 2013 16:51:30 +0000 (14:51 -0200)]
mx6: soc: Staticize set_vddsoc()

set_vddsoc() is not used anywhere else, so make it static.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6sabre_common.h: Add CONFIG_CMD_FUSE support
Fabio Estevam [Mon, 23 Dec 2013 15:07:18 +0000 (13:07 -0200)]
mx6sabre_common.h: Add CONFIG_CMD_FUSE support

Add CONFIG_CMD_FUSE option, so that the fuse API can be used.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
10 years agodoc: README.fuse: Add an example on how to use the fuse API on mx6q
Fabio Estevam [Mon, 23 Dec 2013 15:07:17 +0000 (13:07 -0200)]
doc: README.fuse: Add an example on how to use the fuse API on mx6q

When using the fuse API in U-boot user must calculate the 'bank' and 'word'
values.

Provide a real example on how to calculate such values for the mx6q.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
10 years agoboard:trats2: fix default partitions and mmc env
Piotr Wilczek [Mon, 30 Dec 2013 08:40:40 +0000 (09:40 +0100)]
board:trats2: fix default partitions and mmc env

This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoboard:trats1:trats2: fix adapter number
Piotr Wilczek [Wed, 18 Dec 2013 14:43:37 +0000 (15:43 +0100)]
board:trats1:trats2: fix adapter number

This fix is necessary after increased by one the number
of adapters in s3c24x0 driver.

Tested on Trats and Trats2.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoSPL: EXYNOS: Prepare for variable size SPL support
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:27 +0000 (09:44 +0530)]
SPL: EXYNOS: Prepare for variable size SPL support

When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.

The enhancements include
- adding a command line option, '--vs' to indicate the need for the
variable size encapsulation
- padding the fixed size encapsulated blob with 0xff instead of random
memory contents
- do not silently truncate the input file, report error instead
- no need to explicitly closing files/freeing memory, this all happens
on exit; removing cleanups it makes code clearer
- profuse commenting
- modify Makefile to allow enabling the new feature per board

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoConfig: Add initial config for SMDK5420
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:26 +0000 (09:44 +0530)]
Config: Add initial config for SMDK5420

Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoDTS: Add dts support for SMDK5420
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:25 +0000 (09:44 +0530)]
DTS: Add dts support for SMDK5420

This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoExynos5420: Add base patch for SMDK5420
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:24 +0000 (09:44 +0530)]
Exynos5420: Add base patch for SMDK5420

Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoExynos5420: Add support for 5420 in pinmux and gpio
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:23 +0000 (09:44 +0530)]
Exynos5420: Add support for 5420 in pinmux and gpio

Adds code in pinmux and gpio framework to support Exynos5420.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoExynos5420: Add DDR3 initialization for 5420
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:22 +0000 (09:44 +0530)]
Exynos5420: Add DDR3 initialization for 5420

This patch intends to add DDR3 initialization code for Exynos5420.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoExynos5420: Add clock initialization for 5420
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:21 +0000 (09:44 +0530)]
Exynos5420: Add clock initialization for 5420

This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoEXYNOS5420: Add dmc and phy_control register structure
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:20 +0000 (09:44 +0530)]
EXYNOS5420: Add dmc and phy_control register structure

Add dmc and phy_control register structure for 5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoEXYNOS5420: Add power register structure.
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:19 +0000 (09:44 +0530)]
EXYNOS5420: Add power register structure.

Add structure for power register for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoExynos5420: Add base addresses for 5420
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:18 +0000 (09:44 +0530)]
Exynos5420: Add base addresses for 5420

Adds base addresses of various IPs and controllers required for
Exynos5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoEXYNOS5: Create a common board file
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:17 +0000 (09:44 +0530)]
EXYNOS5: Create a common board file

Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.

exynos_init function is provided for platform specific code.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agoMX6: fix sata compilation for i.MX6
Stefano Babic [Thu, 19 Dec 2013 10:04:33 +0000 (11:04 +0100)]
MX6: fix sata compilation for i.MX6

Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks
board with SATA support, because sata is not compiled.

Signed-off-by: Stefano Babic <sbabic@denx.de>
10 years agoARM: AM43xx: Add Maintainer
Lokesh Vutla [Tue, 10 Dec 2013 09:32:24 +0000 (15:02 +0530)]
ARM: AM43xx: Add Maintainer

Adding Maintainer for AM43xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: GP_EVM: Add support for DDR3
Lokesh Vutla [Tue, 10 Dec 2013 09:32:23 +0000 (15:02 +0530)]
ARM: AM43xx: GP_EVM: Add support for DDR3

GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: EPOS_EVM: Add support for LPDDR2
Lokesh Vutla [Tue, 10 Dec 2013 09:32:22 +0000 (15:02 +0530)]
ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM33xx+: Update ioregs to pass different values
Lokesh Vutla [Tue, 10 Dec 2013 09:32:21 +0000 (15:02 +0530)]
ARM: AM33xx+: Update ioregs to pass different values

Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>
10 years agoARM: AM43xx: clocks: Update DPLL details
Lokesh Vutla [Tue, 10 Dec 2013 09:32:20 +0000 (15:02 +0530)]
ARM: AM43xx: clocks: Update DPLL details

Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE  VDD_MPU
OPP50 OPP50
OPP50  OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: mux: Update mux data
Lokesh Vutla [Tue, 10 Dec 2013 09:32:19 +0000 (15:02 +0530)]
ARM: AM43xx: mux: Update mux data

Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: Update Current Booting devices list
Lokesh Vutla [Tue, 10 Dec 2013 09:32:18 +0000 (15:02 +0530)]
ARM: AM43xx: Update Current Booting devices list

Current Booting devices list is different from that of AM33xx.
Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: Select clk source for Timer2
Lokesh Vutla [Tue, 10 Dec 2013 09:32:17 +0000 (15:02 +0530)]
ARM: AM43xx: Select clk source for Timer2

Selecting the Master osc clk as Timer2 clock source.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
Sekhar Nori [Tue, 10 Dec 2013 09:32:16 +0000 (15:02 +0530)]
ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support

CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43XX: board: add support for reading onboard EEPROM
Sekhar Nori [Tue, 10 Dec 2013 09:32:15 +0000 (15:02 +0530)]
ARM: AM43XX: board: add support for reading onboard EEPROM

Add support for reading onboard EEPROM to enable
board detection.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: Add extra ENV settings
Lokesh Vutla [Tue, 10 Dec 2013 09:32:14 +0000 (15:02 +0530)]
ARM: AM43xx: Add extra ENV settings

Add Extra env settings.
This is derived from am335x Extra ENV settings.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: Add L2 Support
Lokesh Vutla [Tue, 10 Dec 2013 09:32:13 +0000 (15:02 +0530)]
ARM: AM43xx: Add L2 Support

AM4372 uses PL310 L2 Cache. Enable the configs for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: Adapt to ti_armv7_common.h config file
Lokesh Vutla [Tue, 10 Dec 2013 09:32:12 +0000 (15:02 +0530)]
ARM: AM43xx: Adapt to ti_armv7_common.h config file

Use ti_armv7_common.h config file to inclde the common
configs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoARM: AM43xx: Update the base addresses of modules
Lokesh Vutla [Tue, 10 Dec 2013 09:32:11 +0000 (15:02 +0530)]
ARM: AM43xx: Update the base addresses of modules

PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoarm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled)
Stefan Roese [Tue, 17 Dec 2013 13:14:06 +0000 (14:14 +0100)]
arm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled)

Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Beagleboard. Since some gpio input's are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
10 years agoMerge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'
Albert ARIBAUD [Wed, 18 Dec 2013 21:19:02 +0000 (22:19 +0100)]
Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'

10 years agoMerge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
Albert ARIBAUD [Wed, 18 Dec 2013 20:45:34 +0000 (21:45 +0100)]
Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'

10 years agoARM: pxa: Fix CONFIG_SYS_HZ on PXA
Marek Vasut [Mon, 4 Nov 2013 19:50:21 +0000 (20:50 +0100)]
ARM: pxa: Fix CONFIG_SYS_HZ on PXA

The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across
U-Boot. Fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
10 years agoarm: tegra: Fix the CPU complex reset masks
Alban Bedel [Wed, 20 Nov 2013 16:42:46 +0000 (17:42 +0100)]
arm: tegra: Fix the CPU complex reset masks

The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swrren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: Add the Tamonten™ NG Evaluation Carrier board
Alban Bedel [Thu, 14 Nov 2013 09:58:30 +0000 (10:58 +0100)]
ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board

Add support for the new Tamonten™ NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>