oweals/u-boot.git
13 years agopowerpc/85xx: Add P1021 specific QE and UEC support
Haiying Wang [Fri, 11 Feb 2011 07:25:30 +0000 (01:25 -0600)]
powerpc/85xx: Add P1021 specific QE and UEC support

P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode.  QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.

Also added relevant QE support defines unique to P1021.

The P1021 QE is shared on P1012, P1016, and P1025.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT
Zhao Chenhui [Fri, 28 Jan 2011 09:58:37 +0000 (17:58 +0800)]
powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Tue, 5 Apr 2011 10:24:20 +0000 (12:24 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Conflicts:
drivers/usb/host/ehci-pci.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Wolfgang Denk [Tue, 5 Apr 2011 10:17:38 +0000 (12:17 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

13 years agopowerpc: clean up DIU macro definitions for Freescale reference boards
Timur Tabi [Tue, 15 Feb 2011 23:09:19 +0000 (17:09 -0600)]
powerpc: clean up DIU macro definitions for Freescale reference boards

Clean up the macro defintions used to enable DIU (video) support on the
MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS,
which is newer.  Add software cursor support to all three boards.

Also document the CONFIG_FSL_DIU_FB in the README.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Enable eSDHC boot support on P2020 DS
Jerry Huang [Mon, 24 Jan 2011 17:09:54 +0000 (17:09 +0000)]
powerpc/85xx: Enable eSDHC boot support on P2020 DS

We implement our own mmc_get_env_addr since the environment variables are
written to just after the u-boot image on SDCard, so we must read the MBR
to get the start address and code length of the u-boot image, then
calculate the address of the env.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoenv_mmc: Allow board code to override the environment address
Mingkai Hu [Mon, 24 Jan 2011 17:09:55 +0000 (17:09 +0000)]
env_mmc: Allow board code to override the environment address

On some boards the environment may not be located at a fixed address in
the MMC/SDHC card.  This allows those boards to implement their own
means to report what address the environment is located at.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Fix typo for address hashing message
Kumar Gala [Fri, 18 Mar 2011 16:53:06 +0000 (11:53 -0500)]
powerpc/8xxx: Fix typo for address hashing message

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements
Kyle Moffett [Mon, 28 Mar 2011 15:35:48 +0000 (11:35 -0400)]
mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements

The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header.  This dramatically improves the
readability of the switch statments.

In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC
Kyle Moffett [Tue, 15 Mar 2011 15:23:47 +0000 (11:23 -0400)]
fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC

The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.

Since all of the inputs to this are 32-bit (nanoseconds, clock cycles,
and DDR frequencies), we can easily restructure the computation to use
the "do_div()" function to perform 64-bit/32-bit divide operations.

On 64-bit this change is basically a no-op, because do_div is
implemented as a literal 64-bit divide operation and the instruction
scheduling works out almost the same.

On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is
over 1.1kB of code and thousands of heavily dependent cycles to compute,
all of which is linked from libgcc.  Another 1.2kB of code comes in for
the function __umoddi3.

It should be noted that nothing else in U-Boot or the Linux kernel seems
to require a full 64-bit divide on my 32-bit PowerPC.

Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: York Sun <yorksun@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020
Laurentiu TUDOR [Tue, 15 Mar 2011 14:37:36 +0000 (16:37 +0200)]
powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020

We utilize the compatible string to find the node to add fsl,liodn
property to.  However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.

Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness.  On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.

Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add 36-bit address map support to P1022DS
Jiang Yutang [Mon, 24 Jan 2011 10:21:15 +0000 (18:21 +0800)]
powerpc/85xx: Add 36-bit address map support to P1022DS

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agotsec: add AR8021 PHY support
Li Yang [Thu, 27 Jan 2011 11:02:50 +0000 (19:02 +0800)]
tsec: add AR8021 PHY support

Signed-off-by: Li Yang <leoli@freescale.com>
13 years agopowerpc/85xx: Update timer-frequency prop in ptp_timer node of device tree
bhaskar upadhaya [Wed, 2 Feb 2011 14:44:28 +0000 (14:44 +0000)]
powerpc/85xx: Update timer-frequency prop in ptp_timer node of device tree

Fix up the device tree property associated with the IEEE 1588 timer
source frequency.  Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support).  The eTSEC clock is ccb_clk/2.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Fix determining Fman freq on P1023
Kumar Gala [Thu, 10 Mar 2011 12:09:20 +0000 (06:09 -0600)]
powerpc/85xx: Fix determining Fman freq on P1023

On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2
of it.  Also we only have one Fman so no need for the code to deal with
a second.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Fixup determining PME, FMan freq
Kumar Gala [Wed, 16 Feb 2011 08:03:29 +0000 (02:03 -0600)]
powerpc/85xx: Fixup determining PME, FMan freq

On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.

We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)

On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL.  On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.

On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV.  On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add support for ULI1575 PCI EHCI module on MPC8572DS
Zhao Chenhui [Fri, 4 Mar 2011 08:31:41 +0000 (16:31 +0800)]
powerpc/85xx: Add support for ULI1575 PCI EHCI module on MPC8572DS

MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage
device support using PCI EHCI module.

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Disable ECC in considering performance on MPC8572DS
Zhao Chenhui [Wed, 2 Mar 2011 08:44:52 +0000 (16:44 +0800)]
powerpc/85xx: Disable ECC in considering performance on MPC8572DS

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Replace memctl_intlv_ctl with hwconfig on MPC8572DS
Zhao Chenhui [Wed, 2 Mar 2011 08:44:36 +0000 (16:44 +0800)]
powerpc/85xx: Replace memctl_intlv_ctl with hwconfig on MPC8572DS

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB
Poonam Aggrwal [Wed, 9 Feb 2011 20:05:29 +0000 (20:05 +0000)]
powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB

Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB
Poonam Aggrwal [Mon, 7 Feb 2011 11:47:28 +0000 (17:17 +0530)]
powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB

Changed the following DDR timing parameters for 800Mt/s:
tRRT    BL/2+1 to  BL/2
tWWT    BL/2+1 to  BL/2
tWRT    BL/2+1 to  BL/2
tRWT    BL/2+1 to  BL/2
REFINT  6500ns to  7800ns

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Removed P1/P2 RDB RevB support
Poonam Aggrwal [Wed, 9 Feb 2011 17:54:11 +0000 (23:24 +0530)]
powerpc/85xx: Removed P1/P2 RDB RevB support

RevB boards never really made it outside of Freescale and have been
replaced with RevC & RevD which had various board bug fixes.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Read board switch settings on p1_p2_rdb
Priyanka Jain [Tue, 8 Feb 2011 07:48:34 +0000 (13:18 +0530)]
powerpc/85xx: Read board switch settings on p1_p2_rdb

PCA9557 is parallel I/O expansion device on I2C bus which stores various
board switch settings like NOR Flash-Bank selection, SD Data width.

On board:
switch SW5[6] is to select width for eSDHC
        ON  - 4-bit [Enable eSPI]
        OFF - 8-bit [Disable eSPI]

switch SW4[8] is to select NOR Flash Bank for Booting
        OFF - Primary Bank
        ON  - Secondary Bank

Read board switch settings on p1_p2_rdb and configure corresponding
eSDHC width.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb
Priyanka Jain [Tue, 8 Feb 2011 07:43:15 +0000 (13:13 +0530)]
powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb

Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash
boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
  size of image that could be loaded in SRAM mode and would require three
  stage boot loader (TPL).

Changes done:
 1. CONFIG_SYS_TEXT_BASE to 0x11000000
 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1
Timur Tabi [Wed, 9 Feb 2011 02:00:09 +0000 (02:00 +0000)]
fsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1

The NXID EEPROM format comes in two versions, v0 and v1.  The only
difference is in the number of MAC addresses that can be stored.  NXID v0
supports eight addresses, and NXID v1 supports 23.

Rather than allow a board to choose which version to support, NXID v0 is
now considered deprecated.  The EEPROM code is updated to support only
NXID v1, but it can still read EEPROMs formatted with v0.  In these cases,
the EEPROM data is loaded and the CRC is verified, but the data is stored
into a v1 data structure.  If the EEPROM data is written back, it is
written in v1 format.  This allows existing v0-formatted EEPROMs to
continue providing MAC addresses, but any changes to the data will force
an upgrade to the v1 format, while retaining all data.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE
Kumar Gala [Fri, 4 Feb 2011 06:43:34 +0000 (00:43 -0600)]
powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE

CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in
config_mpc85xx.h for those parts with a Frame Manager.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Corrected sdhc clock value for P1010
Priyanka Jain [Tue, 8 Feb 2011 10:15:25 +0000 (15:45 +0530)]
powerpc/85xx: Corrected sdhc clock value for P1010

SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Adds some P1010/P1014 SoC configuration defines
Poonam Aggrwal [Sun, 6 Feb 2011 06:01:44 +0000 (11:31 +0530)]
powerpc/85xx: Adds some P1010/P1014 SoC configuration defines

Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR
and SDHC erratum.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Support for Freescale P1024/P1025 processor
Kumar Gala [Sat, 5 Feb 2011 19:45:07 +0000 (13:45 -0600)]
powerpc/85xx: Support for Freescale P1024/P1025 processor

Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.

P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.

Added comments in config_mpc85xx.h to denote single core versions of
processors.

Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoechi: add ULI1575 PCI ID
Zhao Chenhui [Sun, 13 Mar 2011 15:00:40 +0000 (10:00 -0500)]
echi: add ULI1575 PCI ID

Add ULI1575 EHCI controller to the list of the supported devices.

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: load ucode from nand flash before qe_init
Haiying Wang [Mon, 7 Feb 2011 21:14:15 +0000 (16:14 -0500)]
powerpc/85xx: load ucode from nand flash before qe_init

In the case the QE's microcode is stored in nand flash, we need to load it from
NAND flash to ddr first then the qe_init can get the ucode correctly.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_ddr: Adds 16 bit DDR Data width option
Poonam Aggrwal [Mon, 7 Feb 2011 09:39:51 +0000 (15:09 +0530)]
fsl_ddr: Adds 16 bit DDR Data width option

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB
Poonam Aggrwal [Mon, 7 Feb 2011 09:38:29 +0000 (15:08 +0530)]
powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Display DIMM model
York Sun [Fri, 4 Feb 2011 21:58:00 +0000 (13:58 -0800)]
powerpc/8xxx: Display DIMM model

Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Update fixed DDR3 timing table for P4080DS
York Sun [Fri, 4 Feb 2011 21:57:59 +0000 (13:57 -0800)]
powerpc/85xx: Update fixed DDR3 timing table for P4080DS

Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Fix LAW init to respect pre-initialized entries
Kumar Gala [Thu, 3 Feb 2011 15:02:13 +0000 (09:02 -0600)]
powerpc/8xxx: Fix LAW init to respect pre-initialized entries

If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.

In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_pci: Add support for FSL PCIe controllers v2.x
Prabhakar Kushwaha [Fri, 4 Feb 2011 03:30:43 +0000 (09:00 +0530)]
fsl_pci: Add support for FSL PCIe controllers v2.x

FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x

Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window

FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register

Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.

To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Refactor Qman/Portal support to be shared between SoCs
Haiying Wang [Thu, 20 Jan 2011 22:26:31 +0000 (22:26 +0000)]
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs

There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.

* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
  (features doesn't exist on P1023/P1017)

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add support for Freescale P1023/P1017 Processors
Roy Zang [Fri, 4 Feb 2011 04:14:19 +0000 (22:14 -0600)]
powerpc/85xx: Add support for Freescale P1023/P1017 Processors

Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
  (fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPL
Kumar Gala [Fri, 4 Feb 2011 02:21:42 +0000 (20:21 -0600)]
powerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPL

Slim down NAND SPL build a bit as we don't need read_tlbcam_entry.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc: Add cpu_secondary_init_r to allow for initialization post env setup
Kumar Gala [Wed, 2 Feb 2011 17:23:50 +0000 (11:23 -0600)]
powerpc: Add cpu_secondary_init_r to allow for initialization post env setup

We can simplify some cpu/SoC level initialization by moving it to be
after the environment and non-volatile storage is setup as there might
be dependancies on such things in various boot configurations.

For example for FSL SoC's with QE if we boot from NAND we need it setup
to extra the ucode image to initialize the QE.  If we always do this
after environment & non-volatile storage is working we can have the code
be the same regardless of NOR, NAND, SPI, MMC boot.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Cleanup some QE related defines
Kumar Gala [Tue, 1 Feb 2011 05:09:25 +0000 (23:09 -0600)]
powerpc/85xx: Cleanup some QE related defines

Move some processor specific QE defines into config_mpc85xx.h and use
QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct.

Also fixed up some comment style issues in immap_qe.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board
Kumar Gala [Tue, 1 Feb 2011 04:18:47 +0000 (22:18 -0600)]
powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board

Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing.  The only variations are in how many
controllers or DIMMs per controller exist.  To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.

We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()
Kumar Gala [Tue, 1 Feb 2011 02:36:02 +0000 (20:36 -0600)]
powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()

Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq().  If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Remove config.mk for nand linker script
Kumar Gala [Mon, 31 Jan 2011 21:57:01 +0000 (15:57 -0600)]
powerpc/85xx: Remove config.mk for nand linker script

Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc: Move cpu specific lmb reserve to arch_lmb_reserve
Kumar Gala [Mon, 31 Jan 2011 21:51:20 +0000 (15:51 -0600)]
powerpc: Move cpu specific lmb reserve to arch_lmb_reserve

We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems.  We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Update P2020DS default env settings
Li Yang [Mon, 24 Jan 2011 17:09:52 +0000 (17:09 +0000)]
powerpc/85xx: Update P2020DS default env settings

Read MAC address from EEPROM. Add hwconfig settings.

Modified the default othbootargs to include the cache-sram-size
parameter. This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.

Also cleanup some of the boot commands.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add eSDHC support on P2020DS
Jerry Huang [Mon, 24 Jan 2011 17:09:53 +0000 (17:09 +0000)]
powerpc/85xx: Add eSDHC support on P2020DS

We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9
respectively).

We enable EXT2, FAT, and parition support for both MMC & USB configs.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add some defines for P2040, P3041, P5010, P5020
Kumar Gala [Tue, 25 Jan 2011 18:42:32 +0000 (12:42 -0600)]
powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020

Specify the number of DDR controllers, number of frame managers, number
of 1g and 10g ports.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"
Pankaj Chauhan [Tue, 25 Jan 2011 09:14:57 +0000 (14:44 +0530)]
powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"

In a manner similar to passing ethernet stashing parameters into device
tree for "gianfar", extend the support to the "fsl,etsec2" as well.

Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>
Kumar Gala [Tue, 25 Jan 2011 07:48:03 +0000 (01:48 -0600)]
powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>

Remove declerations of fsl_ddr_set_memctl_regs in board files with and
place it into a common header.

Based on patch from Poonam Aggrwal.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init
Kumar Gala [Tue, 25 Jan 2011 05:36:17 +0000 (23:36 -0600)]
powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init

Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.

Based on patch from Poonam Aggrwal.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agop1022ds: allow for board-specific ngPIXIS functions
Timur Tabi [Fri, 21 Jan 2011 22:03:57 +0000 (16:03 -0600)]
p1022ds: allow for board-specific ngPIXIS functions

The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC
SOCs.  Although programming the ngPIXIS is mostly standard on all boards that
have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in
"indirect" mode whenever the video display (DIU) is active.

To support indirect mode, and to make it easier to support other quirks on
future reference boards, the low-level ngPIXIS functions are all marked as
weak, so that board-specific code can override any of them.  We take advantage
of this feature on the P1022DS, so that we can properly reset the board when
the DIU is active.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add support for Integrated Flash Controller (IFC)
Dipen Dudhat [Thu, 20 Jan 2011 10:59:35 +0000 (16:29 +0530)]
powerpc/85xx: Add support for Integrated Flash Controller (IFC)

The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
        - Functional muxing of pins between NAND, NOR and GPCM
        - Support memory banks of size 64KByte to 4 GBytes
        - Write protection capability (only for NAND and NOR)
        - Provision of Software Reset
        - Flexible Timing programmability for every chip select
        - NAND Machine
                - x8/ x16 NAND Flash Interface
                - SLC and MLC NAND Flash devices support with
                  configurable
                  page sizes of upto 4KB
                - Internal SRAM of 9KB which is directly mapped and
                  availble at
                  boot time for NAND Boot
                - Configurable block size
                - Boot chip select (CS0) available at system reset
        - NOR Machine
                - Data bus width of 8/16/32
                - Compatible with asynchronous NOR Flash
                - Directly memory mapped
                - Supports address data multiplexed (ADM) NOR device
                - Boot chip select (CS0) available at system reset
        - GPCM Machine (NORMAL GPCM Mode)
                - Support for x8/16/32 bit device
                - Compatible with general purpose addressable device
                  e.g. SRAM, ROM
                - External clock is supported with programmable division
                  ratio
        - GPCM Machine (Generic ASIC Mode)
                - Support for x8/16/32 bit device
                - Address and Data are shared on I/O bus
                - Following Address and Data sequences can be supported
                  on I/O bus
                       - 32 bit I/O: AD
                       - 16 bit I/O: AADD
                       - 8 bit I/O : AAAADDDD
                - Configurable Even/Odd Parity on Address/Data bus
                  supported

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add SERDES support for P1010/P1014
Prabhakar Kushwaha [Thu, 20 Jan 2011 11:04:41 +0000 (16:34 +0530)]
powerpc/85xx: Add SERDES support for P1010/P1014

Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.

Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoMIPS: Au1x00: Move all Au1x00 specific code to separate subdirectory
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:58 +0000 (18:33 +0200)]
MIPS: Au1x00: Move all Au1x00 specific code to separate subdirectory

Au1x00 is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Thomas Lange <thomas@corelatus.se>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
13 years agoMIPS: IncaIP: Move all IncaIP specific code to separate subdirectory
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:57 +0000 (18:33 +0200)]
MIPS: IncaIP: Move all IncaIP specific code to separate subdirectory

IncaIP is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
13 years agoMIPS: Optimize the setup of CPU optimization flags
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:56 +0000 (18:33 +0200)]
MIPS: Optimize the setup of CPU optimization flags

The current MIPS CPU config.mk code always expects a MIPS 4kc
core. This is not appropiate for other CPUs and SoCs.

Replace the current MIPSFLAGS code by cc-option macro and use
-march=mips32r2 as default optimization level for all MIPS32 CPUs.

Note: Since commit f62fb99941c625605aa16a0097b396a5c16d2c88 all
toolchains with binutils prior to v2.16 are not working anymore.
As agreed with Shinya Kuribayashi the support for those toolchains
will be dropped officially with this patch.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
13 years agoMIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:55 +0000 (18:33 +0200)]
MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32

All current CPUs and SoCs are based on MIPS32 arch. The complete
code resides in the global arch/mips/cpu directory. This is not
suitable if other MIPS architectures like MIPS64 or Octeon should
be supported in the future.

To achieve this the current CPU code is moved to its own mips32
subdirectory. All MIPS32 boards have to use mips32 as config switch
in board.cfg.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Cc: Vlad Lungu <vlad.lungu@windriver.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
13 years agoMIPS: Purple: Remove Purple support
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:54 +0000 (18:33 +0200)]
MIPS: Purple: Remove Purple support

The Purple SoC and eval board are not actively maintained since years.
This patch removes the support completely as aggreed with Wolfgang Denk.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
13 years agoehci-pci: Add PCI EHCI controller
Trübenbach, Ralf [Thu, 31 Mar 2011 16:46:47 +0000 (16:46 +0000)]
ehci-pci: Add PCI EHCI controller

This patch adds support for the PI7C9X442SL PCIe EHCI host controller
from Pericom.

Tested at P4080DS eval board from Freescale.

Signed-off-by: Ralf Trübenbach <ralf.truebenbach@men.de>
Cc: Remy Bohmer <linux@bohmer.net>
13 years agofat32 root directory handling
Erik Hansen [Thu, 24 Mar 2011 09:15:37 +0000 (10:15 +0100)]
fat32 root directory handling

Fat directory handling didn't check reaching the end of the root directory. It
relied on a stop condition based on a directory entry with a name starting with
a '\0' character. This check in itself is wrong ('\0' indicates free entry, not
end_of_directory) but outside the scope of this fix. For FAT32, the end of the
rootdir is reached when the end of the cluster chain is reached. The code didn't
check this condition and started to read an incorrect cluster. This caused a
subsequent read request of a sector outside the range of the usb stick in
use. On its turn, the usb stick protested with a stall handshake.

Both FAT32 and non-FAT32 (FAT16/FAT12) end or rootdir checks have been put in.

Signed-off-by: Erik Hansen <erik@makarta.com>
13 years agoRemove unnecessary reset in usb_stor_get_info
Erik Hansen [Thu, 24 Mar 2011 14:06:24 +0000 (15:06 +0100)]
Remove unnecessary reset in usb_stor_get_info

The reset request in usb_stor_get_info is causing issues with some usb
sticks. Some of these sticks vendor_id/product_id have been hardcoded to
not reset but better is to remove the reset altogether. It is not needed.

Signed-off-by: Erik Hansen <erik@makarta.com>
13 years agousb: musb: blackfin: check anomaly workarounds at runtime too
Mike Frysinger [Thu, 17 Mar 2011 21:35:01 +0000 (17:35 -0400)]
usb: musb: blackfin: check anomaly workarounds at runtime too

The anomaly workarounds we need for older silicon might break things
if used on newer versions where the anomalies don't exist.  So check
the silicon rev at runtime too.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agousb: musb: blackfin: make clkin configurable
Mike Frysinger [Thu, 17 Mar 2011 21:35:00 +0000 (17:35 -0400)]
usb: musb: blackfin: make clkin configurable

Not everyone has a 24MHz clkin to the USB, so let board porters override.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoatmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN
michael [Mon, 14 Mar 2011 21:16:38 +0000 (21:16 +0000)]
atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN

If NCE is hooked up to NCS3, we don't need to (and can't)
explicitly set the state of the NCE pin. Instead, the
controller asserts it automatically as part of a
command/data access. Only "CE don't care"-type NAND chips
can be used in this manner.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
13 years agoNAND: add support for reading ONFI page table
Florian Fainelli [Fri, 25 Feb 2011 00:01:34 +0000 (00:01 +0000)]
NAND: add support for reading ONFI page table

This patch adds support for reading an ONFI page parameter from a NAND
device supporting it. If this is the case, struct nand_chip onfi_version
member contains the supported ONFI version, 0 otherwise.

This allows NAND drivers past nand_scan_ident to set the best timings for the
NAND chip.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
13 years agoFix NAND_SPL and ONENAND_IPL in Makefile
Haiying Wang [Thu, 27 Jan 2011 14:44:59 +0000 (09:44 -0500)]
Fix NAND_SPL and ONENAND_IPL in Makefile

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
13 years agoNAND: add more watchdog resets
Scott Wood [Thu, 3 Feb 2011 00:15:57 +0000 (18:15 -0600)]
NAND: add more watchdog resets

Poke the watchdog in a variety of looping constructs, which could take
a long time to complete.

Signed-off-by: Scott Wood <scottwood@freescale.com>
13 years agoPrepare v2011.03 v2011.03
Wolfgang Denk [Thu, 31 Mar 2011 21:45:36 +0000 (23:45 +0200)]
Prepare v2011.03

Signed-off-by: Wolfgang Denk <wd@denx.de>
13 years agoFix build issues cause by LDFLAGS_FINAL changes
Wolfgang Denk [Thu, 31 Mar 2011 21:26:29 +0000 (16:26 -0500)]
Fix build issues cause by LDFLAGS_FINAL changes

Commit 6dc1ece "Introduce a new linker flag LDFLAGS_FINAL" modified a
number of Makefiles in a way that broke out-of-tree builds.  The
problem was that $(nandobj) was used before it got defined.

Fix this.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Thu, 31 Mar 2011 07:01:36 +0000 (09:01 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

13 years agoMerge branch 'master' of git://git.denx.de/u-boot-cfi-flash
Wolfgang Denk [Thu, 31 Mar 2011 06:59:32 +0000 (08:59 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash

13 years agoFix build problems caused by "_end" -> "__bss_end__" rename
Wolfgang Denk [Tue, 29 Mar 2011 12:34:50 +0000 (14:34 +0200)]
Fix build problems caused by "_end" -> "__bss_end__" rename

Commit 44c6e65 "rename _end to __bss_end__ broke building of a large
number of systems (at least all PowerPC?):

libstubs.o: In function `app_startup':
examples/standalone/stubs.c:197: undefined reference to `__bss_end__'

The rename should not be done for the files in the
examples/standalone/ directory, as these are not using the code from
start.S, but do their own BSS clearing, and either use their own
linker scripts or the ones provided by the compilers.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
13 years agopowerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
Prabhakar Kushwaha [Tue, 1 Feb 2011 15:55:58 +0000 (15:55 +0000)]
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs

The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agocfi_flash: fix bug with flash banks with different sector numbers
Martin Krause [Mon, 21 Mar 2011 17:07:56 +0000 (18:07 +0100)]
cfi_flash: fix bug with flash banks with different sector numbers

The function find_sector() does not take into account if the flash bank
has changed since the last call. This could lead to illegal accesses inside
and beyond the flash_info_t info strcture. For example if the current
flash bank has less sectors than the last used flash bank.

This patch adds two cheks. One that insures, that the current sector does
not exceed the allowed maximum (which is always a good idea). And one that
checks if the current access is to the same flash bank as the last access.
If not, the search loop will start with sector 0.

Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Stefan Roese <sr@denx.de>
13 years agopowerpc/85xx: Enable various errata on P1022/P1013 SoCs
Jiang Yutang [Sun, 30 Jan 2011 23:06:20 +0000 (17:06 -0600)]
powerpc/85xx: Enable various errata on P1022/P1013 SoCs

Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on
P1022/P1013 SoCs.

Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoPrepare v v2011.03-rc2
Wolfgang Denk [Sun, 27 Mar 2011 19:50:07 +0000 (21:50 +0200)]
Prepare v

Signed-off-by: Wolfgang Denk <wd@denx.de>
13 years agoCoding Style cleanup: remove trailing empty lines
Wolfgang Denk [Sun, 27 Mar 2011 19:48:08 +0000 (21:48 +0200)]
Coding Style cleanup: remove trailing empty lines

Signed-off-by: Wolfgang Denk <wd@denx.de>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Wolfgang Denk [Sun, 27 Mar 2011 19:20:29 +0000 (21:20 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

13 years agoarm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
Tom Warren [Wed, 23 Feb 2011 09:54:31 +0000 (09:54 +0000)]
arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update

Signed-off-by: Tom Warren <twarren@nvidia.com>
13 years agoS5P: mmc: Resolved interrupt error during mmc_init
Chander Kashyap [Tue, 22 Mar 2011 01:40:50 +0000 (01:40 +0000)]
S5P: mmc: Resolved interrupt error during mmc_init

Blocksize was hardcoded to 512 bytes. But the blocksize varies
depeding on various mmc subsystem commands (between 8 and 512).
This hardcoding was resulting in interrupt error during data
transfer.

It is now calculated based upon the request sent by mmc subsystem.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoARMV7: S5P: Fixed register offset in mmc.h
Chander Kashyap [Tue, 22 Mar 2011 01:29:38 +0000 (01:29 +0000)]
ARMV7: S5P: Fixed register offset in mmc.h

The MMC registers are accessed through struct s5p_mmc member
variables. MMC controller "control4" register offset is set
to 0x8C as per data sheet. The size of struct s5p_mmc is also
corrected.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoS5P: timer: replace bss variable by gd
Minkyu Kang [Wed, 16 Mar 2011 11:09:20 +0000 (20:09 +0900)]
S5P: timer: replace bss variable by gd

Use the global data instead of bss variable, replace as follow.

count_value -> removed
timestamp -> tbl
lastdec -> lastinc

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
13 years agoS5P: universal: Enable the pwm driver
Minkyu Kang [Thu, 10 Mar 2011 11:10:38 +0000 (20:10 +0900)]
S5P: universal: Enable the pwm driver

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoS5P: goni: Enable the pwm driver
Minkyu Kang [Thu, 10 Mar 2011 11:10:19 +0000 (20:10 +0900)]
S5P: goni: Enable the pwm driver

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoS5P: smdkc100: Enable the pwm driver
Minkyu Kang [Thu, 10 Mar 2011 11:09:43 +0000 (20:09 +0900)]
S5P: smdkc100: Enable the pwm driver

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoS5P: timer: Use pwm functions
Minkyu Kang [Thu, 10 Mar 2011 11:05:58 +0000 (20:05 +0900)]
S5P: timer: Use pwm functions

Use pwm functions for timer that is PWM timer 4.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoARM: S5P: pwm driver support
Donghwa Lee [Mon, 7 Mar 2011 21:11:42 +0000 (21:11 +0000)]
ARM: S5P: pwm driver support

This is common pwm driver of S5P.

Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoSMDK6400: Fixup dram_init for relocation support
seedshope [Sat, 22 Jan 2011 10:06:14 +0000 (10:06 +0000)]
SMDK6400: Fixup dram_init for relocation support

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoSMDK6400: Disable LED function in start.s on the nand booting
seedshope [Sat, 22 Jan 2011 10:06:13 +0000 (10:06 +0000)]
SMDK6400: Disable LED function in start.s on the nand booting

Since nand boot have some limit for the first 4KB, We only
disable the LED function to reduce the code space. At the
same time, Fix the compile error for LED function undefined
in the compile time of nand_spl.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoSMDK6400: Add some labels to u-boot.lds to support nand_spl
seedshope [Sat, 22 Jan 2011 10:06:12 +0000 (10:06 +0000)]
SMDK6400: Add some labels to u-boot.lds to support nand_spl

In the nand_spl feature of SMDK6400. Add some relocation symbols to
nand_spl/board/samsung/smdk6400/u-boot.lds to fix the compile error.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoSMDK6400: Fix the mutiple link error
seedshope [Sat, 22 Jan 2011 10:06:11 +0000 (10:06 +0000)]
SMDK6400: Fix the mutiple link error

The first, the cpu_init.o have already been link for cmd_link_o_target
atfer compile, But, The link script re-link the point file. So the link
machine will generate multiple definition error information.

The second, Since the first 4kB of nand boot featue code move to nand_spl,
So It is not necessary to force the cpu_init.o in non-nand boot.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoSMDK6400: Fix some label undefined in build error
seedshope [Sat, 22 Jan 2011 10:06:10 +0000 (10:06 +0000)]
SMDK6400: Fix some label undefined in build error

Modify Makefile for cpu_init.c and Start.s use some label,this defined
u-boot.lds of arch/arm/cpu/arm1176. But SMDK6400 use the link script
board/samsung/smdk6400/u-boot-nand.lds. So add some label form u-boot.lds
to u-boot-nand.lds

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoSMDK6400: Fix CONFIG_SYS_INIT_SP_ADDR undefined
seedshope [Sat, 22 Jan 2011 10:06:09 +0000 (10:06 +0000)]
SMDK6400: Fix CONFIG_SYS_INIT_SP_ADDR undefined

Fix CONFIG_SYS_INIT_SP_ADDR undefined issue.

Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
13 years agoarm: fix incorrect monitor protection region in FLASH
Po-Yu Chuang [Tue, 1 Mar 2011 23:02:04 +0000 (23:02 +0000)]
arm: fix incorrect monitor protection region in FLASH

Monitor protection region in FLASH did not cover .rel.dyn
and .dynsym sections, because it uses __bss_start to compute
monitor_flash_len. Use _end instead.

Add _end to linker scripts for end of u-boot image
Add _end_ofs to all the start.S.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
13 years agorename _end to __bss_end__
Po-Yu Chuang [Tue, 1 Mar 2011 22:59:59 +0000 (22:59 +0000)]
rename _end to __bss_end__

Currently, _end is used for end of BSS section.  We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.

Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
13 years agopowerpc/85xx: Fix PCI memory map setup on P1_P2_RDB
Prabhakar Kushwaha [Wed, 23 Mar 2011 09:21:13 +0000 (04:21 -0500)]
powerpc/85xx: Fix PCI memory map setup on P1_P2_RDB

Update the PCIe address map to match standard FSL memory map.
Additionally, fix the TLBs so the cover the PCIe address space properly
so cards plugged in like an e1000 work correctly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134
York Sun [Thu, 17 Mar 2011 18:18:13 +0000 (11:18 -0700)]
powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134

The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/mpc8xxx: disable rcw_en bit for non-DDR3
York Sun [Thu, 17 Mar 2011 18:18:12 +0000 (11:18 -0700)]
powerpc/mpc8xxx: disable rcw_en bit for non-DDR3

rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>