oweals/u-boot.git
9 years agoMerge git://git.denx.de/u-boot-pxa
Tom Rini [Mon, 2 Mar 2015 12:24:15 +0000 (07:24 -0500)]
Merge git://git.denx.de/u-boot-pxa

9 years agopxa: colibri_pxa270: integrate latest validated register settings
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:19 +0000 (00:53 +0100)]
pxa: colibri_pxa270: integrate latest validated register settings

Integrate latest validated register settings from Toradex WinCE BSP
4.2 working accross all module versions from early V1.x, V1.2D, V2.2B
to V2.4A.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: colibri_pxa270: remove CONFIG_ENV_ADDR_REDUND
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:18 +0000 (00:53 +0100)]
pxa: colibri_pxa270: remove CONFIG_ENV_ADDR_REDUND

Usually not required for NOR flash.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: colibri_pxa270: fix wrong comment about voipac ethernet chip
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:17 +0000 (00:53 +0100)]
pxa: colibri_pxa270: fix wrong comment about voipac ethernet chip

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: colibri_pax270: fix CONFIG_BOOTCOMMAND
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:16 +0000 (00:53 +0100)]
pxa: colibri_pax270: fix CONFIG_BOOTCOMMAND

While 'mmc init' is no longer required the address to bootm the kernel
from NOR flash was wrong.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: colibri_pxa270: avoid overwriting factory configuration block
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:15 +0000 (00:53 +0100)]
pxa: colibri_pxa270: avoid overwriting factory configuration block

Specify a CONFIG_BOARD_SIZE_LIMIT of 256 KB in order to avoid
overwriting the factory configuration block located at offset 0x40000
in NOR flash.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: colibri_pxa270: disable loadb/s commands and long help
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:14 +0000 (00:53 +0100)]
pxa: colibri_pxa270: disable loadb/s commands and long help

To save more than 20 KB of precious space in NOR flash get rid of the
following configuration options:

CONFIG_CMD_LOADB
CONFIG_CMD_LOADS
CONFIG_SYS_LONGHELP

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: colibri_pxa270: migrate to generic board
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:13 +0000 (00:53 +0100)]
pxa: colibri_pxa270: migrate to generic board

Migrate Toradex Colibri PXA270 to use CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agopxa: balloon3/colibri_pxa270: fix environment optionally being nowhere
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:12 +0000 (00:53 +0100)]
pxa: balloon3/colibri_pxa270: fix environment optionally being nowhere

I couldn't quite figure out whether or not CONFIG_SYS_ENV_IS_NOWHERE
actually ever worked but nowadays this is called CONFIG_ENV_IS_NOWHERE.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: balloon3: fix comment about sdram banks
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:11 +0000 (00:53 +0100)]
pxa: balloon3: fix comment about sdram banks

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agopxa: balloon3: remove nowhere used symbol CONFIG_SYS_MEM_BUF_IMP
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:10 +0000 (00:53 +0100)]
pxa: balloon3: remove nowhere used symbol CONFIG_SYS_MEM_BUF_IMP

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agoremove nowhere used symbol CONFIG_SYS_CLKS_IN_HZ
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:09 +0000 (00:53 +0100)]
remove nowhere used symbol CONFIG_SYS_CLKS_IN_HZ

Basically finish what the following commit started a long time ago:

488f5d8790c451fc527fe5d2ef218f2a5e40ea17

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
For mx35pdk/woodburn:

Acked-by: Stefano Babic <sbabic@denx.de>
9 years agopxa: fix wrong comment about vpac270 being the arch number
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:08 +0000 (00:53 +0100)]
pxa: fix wrong comment about vpac270 being the arch number

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-samsung
Tom Rini [Mon, 2 Mar 2015 03:05:54 +0000 (22:05 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-samsung

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-uniphier
Tom Rini [Mon, 2 Mar 2015 02:07:53 +0000 (21:07 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier

9 years agoMerge branch 'rmobile' of git://git.denx.de/u-boot-sh
Tom Rini [Mon, 2 Mar 2015 02:06:47 +0000 (21:06 -0500)]
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Mon, 2 Mar 2015 02:06:33 +0000 (21:06 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

9 years agoARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros
Masahiro Yamada [Thu, 26 Feb 2015 17:27:06 +0000 (02:27 +0900)]
ARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros

Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs.  The line
size is still 128 byte.  Thus, the way size is 32KB/64KB for old/new
SoCs.

To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB.  It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initialization
Masahiro Yamada [Thu, 26 Feb 2015 17:27:05 +0000 (02:27 +0900)]
ARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initialization

This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: consolidate MEMCONF setting code
Masahiro Yamada [Thu, 26 Feb 2015 17:27:04 +0000 (02:27 +0900)]
ARM: UniPhier: consolidate MEMCONF setting code

This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.

The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: switch to 1CS support card
Masahiro Yamada [Thu, 26 Feb 2015 17:27:03 +0000 (02:27 +0900)]
ARM: UniPhier: switch to 1CS support card

The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority.  Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: support 1CS support card for all the UniPhier SoCs
Masahiro Yamada [Thu, 26 Feb 2015 17:27:02 +0000 (02:27 +0900)]
ARM: UniPhier: support 1CS support card for all the UniPhier SoCs

Two support card variants are used with UniPhier reference boards:
 - 1 chip select support card (original CPLD)
 - 3 chip selects support card (ARIMA-compatible CPLD)

Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: switch to xHCI for PH1-Pro4
Masahiro Yamada [Thu, 26 Feb 2015 17:27:01 +0000 (02:27 +0900)]
ARM: UniPhier: switch to xHCI for PH1-Pro4

PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously.  Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agousb: UniPhier: add UniPhier on-chip xHCI host driver support
Masahiro Yamada [Thu, 26 Feb 2015 17:27:00 +0000 (02:27 +0900)]
usb: UniPhier: add UniPhier on-chip xHCI host driver support

Support xHCI host driver used on Panasonic UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree
Masahiro Yamada [Thu, 26 Feb 2015 17:26:59 +0000 (02:26 +0900)]
ARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree

Each USB port corresponds to the following IP core:
 port0: xHCI (0x65a00000) SS+HS
 port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
 port2: EHCI (0x5a800100) HS
 port3: EHCI (0x5a810100) HS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4
Masahiro Yamada [Thu, 26 Feb 2015 17:26:58 +0000 (02:26 +0900)]
ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4

This is necessary to use the USB 3.0 host controllers on PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4
Masahiro Yamada [Thu, 26 Feb 2015 17:26:57 +0000 (02:26 +0900)]
ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4

This is necessary to use the xHCI cores for PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: replace "usb-ehci" with "generic-ehci"
Masahiro Yamada [Thu, 26 Feb 2015 17:26:56 +0000 (02:26 +0900)]
ARM: UniPhier: replace "usb-ehci" with "generic-ehci"

EHCI host controllers have a common register interface.
We may wish to implement a generic EHCI driver someday.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: move uniphier_ehci_reset() function
Masahiro Yamada [Thu, 26 Feb 2015 17:26:55 +0000 (02:26 +0900)]
ARM: UniPhier: move uniphier_ehci_reset() function

Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: UniPhier: remove EHCI platform devices
Masahiro Yamada [Thu, 26 Feb 2015 17:26:54 +0000 (02:26 +0900)]
ARM: UniPhier: remove EHCI platform devices

Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig).  Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers.  We still keep UART platform devices because they might
be useful for SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: UniPhier: enable STDMAC for EHCI
Masahiro Yamada [Thu, 26 Feb 2015 17:26:53 +0000 (02:26 +0900)]
ARM: UniPhier: enable STDMAC for EHCI

Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: reset NAND core in SPL for non-NAND boot mode
Masahiro Yamada [Thu, 26 Feb 2015 17:26:52 +0000 (02:26 +0900)]
ARM: UniPhier: reset NAND core in SPL for non-NAND boot mode

For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)

This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the power-on
reset except the NAND boot mode.  As a result, the NAND controller
begins automatic device scanning with wrong I/O pins and finally
hangs up.

Actually, U-Boot dies after printing "NAND:" on the console unless
the boot mode latch detected the NAND boot mode.

To work around this problem, reset the NAND core in SPL for non-NAND
boot modes.  If CONFIG_NAND_DENALI is enabled, the reset signal is
deasserted again in U-Boot proper.  At this time, I/O pins have been
correctly set up, the device scanning should succeed.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: split clkrst_init() into two functions
Masahiro Yamada [Thu, 26 Feb 2015 17:26:51 +0000 (02:26 +0900)]
ARM: UniPhier: split clkrst_init() into two functions

Split the current clkrst_init() into two functions:

 - early_clkrst_init(): called from SPL
  Deassert the reset signals of the memory controller and some other
  basic cores.

 - clkrst_init(): called from main U-boot
  Deassert the reset signals that are necessary for the access to
  peripherals etc.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*
Masahiro Yamada [Thu, 26 Feb 2015 17:26:50 +0000 (02:26 +0900)]
ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*

Follow the register macros in the LSI specification book.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: fix SBC init code
Masahiro Yamada [Thu, 26 Feb 2015 17:26:49 +0000 (02:26 +0900)]
ARM: UniPhier: fix SBC init code

Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: fix comments in PH1-Pro4 SBC code
Masahiro Yamada [Thu, 26 Feb 2015 17:26:48 +0000 (02:26 +0900)]
ARM: UniPhier: fix comments in PH1-Pro4 SBC code

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoserial: UniPhier: move LCR register setting to probe function
Masahiro Yamada [Thu, 26 Feb 2015 17:26:47 +0000 (02:26 +0900)]
serial: UniPhier: move LCR register setting to probe function

We do not have to set the LCR register every time we change the
baud-rate.  We just need to set it up once in the probe function.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoserial: UniPhier: use 32 bit register access
Masahiro Yamada [Thu, 26 Feb 2015 17:26:46 +0000 (02:26 +0900)]
serial: UniPhier: use 32 bit register access

For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11)
is not working correctly.  As a side effect, it also modifies MCR
register (offset = 0x10) and results in unexpected behavior.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: update defconfigs using savedefconfig
Masahiro Yamada [Thu, 26 Feb 2015 17:26:45 +0000 (02:26 +0900)]
ARM: UniPhier: update defconfigs using savedefconfig

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>
Masahiro Yamada [Thu, 26 Feb 2015 17:26:44 +0000 (02:26 +0900)]
ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>

Since commit 0e7368c6c426 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: move SoC headers to mach-uniphier/include/mach
Masahiro Yamada [Thu, 26 Feb 2015 17:26:43 +0000 (02:26 +0900)]
ARM: UniPhier: move SoC headers to mach-uniphier/include/mach

Move arch/arm/include/asm/arch-uniphier/*
  -> arch/arm/mach-uniphier/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: move SoC sources to mach-uniphier
Masahiro Yamada [Thu, 26 Feb 2015 17:26:42 +0000 (02:26 +0900)]
ARM: UniPhier: move SoC sources to mach-uniphier

Move
arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoExynos: Fix L2 cache timings on Exynos5420 and Exynos5800
Doug Anderson [Fri, 20 Feb 2015 07:57:20 +0000 (13:27 +0530)]
Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800

It was found that the L2 cache timings that we had before could cause
freezes and hangs.  We should make things more robust with better
timings.  Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).

This also provides a big cleanup of the L2 cache init code avoiding
some duplication.  The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
  time) and left resident in iRAM for the kernel to use when bringing
  up additional CPUs.  It used configure_l2_ctlr() and
  configure_l2_actlr() when it detected it was on an A15.  This was
  needed (despite the L2 cache registers being shared among all A15s)
  because we might have been the first man in after the whole A15
  cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
  time.  Strangely this called configure_l2_ctlr() but not
  configure_l2_actlr() which was almost certainly wrong.  Given that
  we'll call both (see next bullet) later in the boot process it
  didn't matter for normal boot, but I guess this is how L2 cache
  settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
  This should happen at boot time (normally in the SPL except for USB
  boot where it happens in main U-Boot).

Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time.  For resume time we'd get it
anyway when the 2nd A15 core came up.

Let's make this a whole lot simpler.  Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.

Intended net effects of this change (other than cleanup):
* Timings go from before:
    data: 0 cycle setup, 3 cycles (0x2) latency
    tag:  0 cycle setup, 3 cycles (0x2) latency
  after:
    data: 1 cycle setup, 4 cycles (0x3) latency
    tag:  1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.

One note is that we're still relying on luck to keep low_power_start()
working.  The compiler is being nice and not storing anything on the
stack.

Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL.  The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
  (after it has turned the L2 cache off).  This is why the functions
  are in a header file instead of lowlevel_init.c.

* Have the kernel save the L2 cache settings of the boot CPU and apply
  them to all other CPUs.  We get a little lucky here because the old
  code was using "|=" to modify the registers and all of the bits that
  it's setting are also present in the new settings (!).  That means
  that when the 2nd CPU in the A15 cluster comes up it doesn't
  actually mess up the settings of the 1st CPU in the A15 cluster.  An
  alternative option is to have the kernel write its own
  low_power_start() code.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: Make A7s boot with thumb-mode U-Boot on warm reset
Akshay Saraswat [Fri, 20 Feb 2015 07:57:19 +0000 (13:27 +0530)]
Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset

On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.

The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.

This issue is fixed by replacing the "mov pc" instruction with a "bx"
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: Fix secondary core booting for thumb
Akshay Saraswat [Fri, 20 Feb 2015 07:57:18 +0000 (13:27 +0530)]
Exynos542x: Fix secondary core booting for thumb

When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: add L2 control register configuration
Akshay Saraswat [Fri, 20 Feb 2015 07:57:17 +0000 (13:27 +0530)]
Exynos542x: add L2 control register configuration

This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
   0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
   We need to restore this here due to switching.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: cache: Disable clean/evict push to external
Akshay Saraswat [Fri, 20 Feb 2015 07:57:16 +0000 (13:27 +0530)]
Exynos542x: cache: Disable clean/evict push to external

L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: Add workaround for exynos iROM errata
Akshay Saraswat [Fri, 20 Feb 2015 07:57:15 +0000 (13:27 +0530)]
Exynos542x: Add workaround for exynos iROM errata

iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.

Logic of the workaround:

Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: Add workaround for ARM errata 799270
Akshay Saraswat [Fri, 20 Feb 2015 07:57:14 +0000 (13:27 +0530)]
Exynos542x: Add workaround for ARM errata 799270

This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: Add workaround for ARM errata 798870
Akshay Saraswat [Fri, 20 Feb 2015 07:57:13 +0000 (13:27 +0530)]
Exynos542x: Add workaround for ARM errata 798870

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: CPU: Power down all secondary cores
Akshay Saraswat [Fri, 20 Feb 2015 07:57:12 +0000 (13:27 +0530)]
Exynos542x: CPU: Power down all secondary cores

This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.

Secondary core power down happens in following steps:

Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoExynos542x: Config: Add various configs
Akshay Saraswat [Fri, 20 Feb 2015 07:57:11 +0000 (13:27 +0530)]
Exynos542x: Config: Add various configs

This patch adds "iRAM, CPU state and low power" configs
which are the addresses acting as flag registers.

iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
to CONFIG_LOWPOWER_EN then it jumps to the address (0x02020000+CPUID*4).
This is a part of iROM logic. Rest other flags are being used at
various places during kernel switching and reset.
They are nowhere documented because they are part programming.
These configs are serving as flags for us because they are
representing the addresses in iRAM which we are using for
storing and extracting CPU Status and GIC status.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoMAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibility
Lukasz Majewski [Thu, 26 Feb 2015 12:23:49 +0000 (13:23 +0100)]
MAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibility

After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.

Such patch formalizes current development status.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Wed, 25 Feb 2015 23:14:18 +0000 (18:14 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

9 years agocrypto/fsl - Add progressive hashing support using hardware acceleration.
gaurav rana [Fri, 20 Feb 2015 07:21:46 +0000 (12:51 +0530)]
crypto/fsl - Add progressive hashing support using hardware acceleration.

Currently only normal hashing is supported using hardware acceleration.
Added support for progressive hashing using hardware.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agocrypto/fsl: Make function names consistent for blob encapsulation/decapsulation.
gaurav rana [Wed, 25 Feb 2015 04:07:09 +0000 (09:37 +0530)]
crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.

This patch does the following:

1. The function names for encapsulation and decapsulation
were inconsitent in freescale's implementation and cmd_blob file.
This patch corrects the issues.
2. The function protopye is also modified to change the length parameter
from u8 to u32 to allow encapsulation and decapsulation of larger images.
3. Modified the description of km paramter in the command usage for better
readability.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: rmobile: silk: Add support SDHI
Vladimir Barinov [Tue, 24 Feb 2015 16:55:46 +0000 (18:55 +0200)]
arm: rmobile: silk: Add support SDHI

This adds GPIO configuration and initialization function of SDHI on Silk board

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: silk: fix typo in device declaration
Vladimir Barinov [Tue, 24 Feb 2015 16:54:48 +0000 (18:54 +0200)]
arm: rmobile: silk: fix typo in device declaration

Fix typo in device declaration

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: silk: Disable ethernet pins pull-up
Vladimir Barinov [Tue, 24 Feb 2015 16:54:31 +0000 (18:54 +0200)]
arm: rmobile: silk: Disable ethernet pins pull-up

Disable pull-ups on ethrenet lines

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: silk: Fix GPIO4_31 initialization
Vladimir Barinov [Tue, 24 Feb 2015 16:54:18 +0000 (18:54 +0200)]
arm: rmobile: silk: Fix GPIO4_31 initialization

Use gpio_direction_output instead of gpio_set_value
since the latter does not set output GPIO direction.

Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: Add Porter board support
Vladimir Barinov [Fri, 13 Feb 2015 22:06:13 +0000 (01:06 +0300)]
arm: rmobile: Add Porter board support

Porter is an entry level development board based on R-Car M2 SoC (R8A7791)

This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, SD, USB Host

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agosh: enable CONFIG_USE_PRIVATE_LIBGCC by default
Masahiro Yamada [Tue, 10 Feb 2015 12:37:02 +0000 (21:37 +0900)]
sh: enable CONFIG_USE_PRIVATE_LIBGCC by default

Now this feature works.  Let's turn it on by default so we do not
depend on specific tool-chains.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agosh: import missing private libraries from Linux 3.19
Masahiro Yamada [Tue, 10 Feb 2015 12:37:01 +0000 (21:37 +0900)]
sh: import missing private libraries from Linux 3.19

SuperH is supposed to support the Private Library feature, but it is
actually not working.

If CONFIG_USE_PRIVATE_LIBGCC is enabled, the build fails for the
undefined references to '__sdivsi3_i4i' and '__udivsi3_i4i'.

To fix this error, import missing libraries from Linux 3.19
and adjust them for U-Boot:
  - Remove "#include <linux/module.h>" and "EXPORT_SYMBOL(...)"
  - Use SPDX-License-Identifier
  - Remove white space

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agosh: rename some private libraries
Masahiro Yamada [Tue, 10 Feb 2015 12:37:00 +0000 (21:37 +0900)]
sh: rename some private libraries

Rename two files to the corresponding file names in Linux.
This helps us find missing libraries in the next commit.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoserial: sh: fix internal clock source on SCIF
Vladimir Barinov [Fri, 13 Feb 2015 22:05:18 +0000 (01:05 +0300)]
serial: sh: fix internal clock source on SCIF

The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows:

BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1,
the prescaler is 0 due to SCSMR settings, hence n=0

Also SCSCR must be set to use internal or external clock source.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoserial: sh: Remove invalid UTF-8 character
Nobuhiro Iwamatsu [Wed, 10 Dec 2014 05:42:05 +0000 (14:42 +0900)]
serial: sh: Remove invalid UTF-8 character

serial_sh.c contains invalid UTF-8 character.
This deletes the character.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: lager: Add support SDHI
Nobuhiro Iwamatsu [Fri, 21 Nov 2014 01:19:32 +0000 (10:19 +0900)]
arm: rmobile: lager: Add support SDHI

Lager board has two SDHI port as SDHI0 and SDHI2.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: gose: Add support SDHI
Nobuhiro Iwamatsu [Wed, 12 Nov 2014 02:29:39 +0000 (11:29 +0900)]
arm: rmobile: gose: Add support SDHI

Gose board has three SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: koelsch: Add support SDHI
Nobuhiro Iwamatsu [Wed, 12 Nov 2014 04:03:54 +0000 (13:03 +0900)]
arm: rmobile: koelsch: Add support SDHI

Koelsch board has three SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: alt: Add support SDHI
Nobuhiro Iwamatsu [Wed, 19 Nov 2014 05:26:33 +0000 (14:26 +0900)]
arm: rmobile: alt: Add support SDHI

Alt board has two SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: silk: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 07:20:04 +0000 (16:20 +0900)]
arm: rmobile: silk: Migrate serial driver to drivers model

This adds drivers model support of serial port to Silk board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: alt: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 07:20:04 +0000 (16:20 +0900)]
arm: rmobile: alt: Migrate serial driver to drivers model

This adds drivers model support of serial port to Alt board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: lager: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 07:20:04 +0000 (16:20 +0900)]
arm: rmobile: lager: Migrate serial driver to drivers model

This adds drivers model support of serial port to Lager board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: gose: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 02:24:01 +0000 (11:24 +0900)]
arm: rmobile: gose: Migrate serial driver to drivers model

This adds drivers model support of serial port to Gose board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoarm: rmobile: koelsch: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 02:24:01 +0000 (11:24 +0900)]
arm: rmobile: koelsch: Migrate serial driver to drivers model

This adds drivers model support of serial port to Koelsch board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agozmx25: Convert to generic board
Fabio Estevam [Mon, 23 Feb 2015 11:51:38 +0000 (08:51 -0300)]
zmx25: Convert to generic board

Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal
from the project.

Cc: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoimx31_phycore: Convert to generic board
Fabio Estevam [Mon, 23 Feb 2015 11:51:37 +0000 (08:51 -0300)]
imx31_phycore: Convert to generic board

Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal
from the project.

Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agomx31ads: Convert to generic board
Fabio Estevam [Mon, 23 Feb 2015 11:51:36 +0000 (08:51 -0300)]
mx31ads: Convert to generic board

Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal
from the project.

Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoARM: davinci: remove hawkboard support
Masahiro Yamada [Tue, 24 Feb 2015 02:45:10 +0000 (11:45 +0900)]
ARM: davinci: remove hawkboard support

This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: remove tnetv107x board support
Masahiro Yamada [Tue, 24 Feb 2015 02:45:09 +0000 (11:45 +0900)]
ARM: remove tnetv107x board support

This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chan-Taek Park <c-park@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: remove a320evb board support
Masahiro Yamada [Tue, 24 Feb 2015 02:45:08 +0000 (11:45 +0900)]
ARM: remove a320evb board support

This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Po-Yu Chuang <ratbert@faraday-tech.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: remove cm4008 and cm41xx board support
Masahiro Yamada [Tue, 24 Feb 2015 02:45:07 +0000 (11:45 +0900)]
ARM: remove cm4008 and cm41xx board support

These are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: remove dkb board support
Masahiro Yamada [Tue, 24 Feb 2015 02:45:06 +0000 (11:45 +0900)]
ARM: remove dkb board support

This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Lei Wen <leiwen@marvell.com>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoARM: remove jadecpu board support
Masahiro Yamada [Tue, 24 Feb 2015 02:45:05 +0000 (11:45 +0900)]
ARM: remove jadecpu board support

This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Matthias Weisser <weisserm@arcor.de>
Acked-by: Marek Vasut <marex@denx.de>
9 years agokconfig: remove unneeded dependency on !SPL_BUILD
Masahiro Yamada [Tue, 24 Feb 2015 13:26:21 +0000 (22:26 +0900)]
kconfig: remove unneeded dependency on !SPL_BUILD

Now CONFIG_SPL_BUILD is not defined in Kconfig, so
"!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agokconfig: switch to single .config configuration
Masahiro Yamada [Tue, 24 Feb 2015 13:26:20 +0000 (22:26 +0900)]
kconfig: switch to single .config configuration

When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL).  There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.config", "tpl/.config" for Normal,
SPL, TPL, respectively.

It is true that the "multiple .config" strategy provided us the
maximum flexibility and helped to avoid duplicating CONFIGs among
Normal, SPL, TPL, but I have noticed some fatal problems:

[1] It is impossible to share CONFIG options across the images.
  If you change the configuration of Main image, you often have to
  adjust some SPL configurations correspondingly.  Currently, we
  cannot handle the dependencies between them.  It means one of the
  biggest advantages of Kconfig is lost.

[2] It is too painful to change both ".config" and "spl/.config".
  Sunxi guys started to work around this problem by creating a new
  configuration target.  Commit cbdd9a9737cc (sunxi: kconfig: Add
  %_felconfig rule to enable FEL build of sunxi platforms.) added
  "make *_felconfig" to enable CONFIG_SPL_FEL on both images.
  Changing the configuration of multiple images in one command is a
  generic demand.  The current implementation cannot propose any
  good solution about this.

[3] Kconfig files are getting ugly and difficult to understand.
  Commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to
  Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files.

[4] The build system got more complicated than it should be.
  To adjust Linux-originated Kconfig to U-Boot, the helper script
  "scripts/multiconfig.sh" was introduced.  Writing a complicated
  text processor is a shell script sometimes caused problems.

Now I believe the "single .config" will serve us better.  With it,
all the problems above would go away.  Instead, we will have to add
some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM,
but we will not have much.  Anyway, this is what we do now in
scripts/Makefile.spl.

I admit my mistake with my apology and this commit switches to the
single .config configuration.

It is not so difficult to do that:

 - Remove unnecessary processings from scripts/multiconfig.sh
  This file will remain for a while to support the current defconfig
  format.  It will be removed after more cleanups are done.

 - Adjust some makefiles and Kconfigs

 - Add some entries to include/config_uncmd_spl.h and the new file
   scripts/Makefile.uncmd_spl.  Some CONFIG options that are not
   supported on SPL must be disabled because one .config is shared
   between SPL and U-Boot proper going forward.  I know this is not
   a beautiful solution and I think we can do better, but let's see
   how much we will have to describe them.

 - update doc/README.kconfig

More cleaning up patches will follow this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agokconfig: Adjust ordering so that defaults work as expected
Simon Glass [Tue, 24 Feb 2015 13:26:19 +0000 (22:26 +0900)]
kconfig: Adjust ordering so that defaults work as expected

At present defaults in arch-specific Kconfig files are ignored if the
top-level item comes ahead of it in include order. This means that it is
not possible to have a U-Boot default that architectures and boards can
override. This does not seem very useful.

Move the include earlier to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value
Masahiro Yamada [Tue, 24 Feb 2015 13:26:18 +0000 (22:26 +0900)]
ARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value

It is true that malloc is necessary for Driver Model before
relocation, but there is no good reason to reserve the malloc
space more than enough.  The default value 0x400 works well.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agoOMAP3: igep0032: Fix regression due commit f3b4bc45.
Enric Balletbo i Serra [Tue, 24 Feb 2015 18:27:15 +0000 (19:27 +0100)]
OMAP3: igep0032: Fix regression due commit f3b4bc45.

Commit referenced in subject breaks IGEP0032 build with the following
error:

  drivers/misc/status_led.c:30:7: error: 'RED_LED_GPIO' undeclared here (not in a function)
  scripts/Makefile.build:275: recipe for target 'drivers/misc/status_led.o' failed
  make[2]: *** [drivers/misc/status_led.o] Error 1
  scripts/Makefile.build:420: recipe for target 'drivers/misc' failed
  make[1]: *** [drivers/misc] Error 2
  Makefile:1093: recipe for target 'drivers' failed
  make: *** [drivers] Error 2

Fix this by skipping the status led on IGEP0032 machine as is not available
and throw an error for future machines if the status led is not configured
to avoid build breakage.

Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
9 years agommc: fsl_esdhc: Add support for DDR mode
Volodymyr Riazantsev [Tue, 20 Jan 2015 15:16:44 +0000 (10:16 -0500)]
mmc: fsl_esdhc: Add support for DDR mode

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls1021x: Add support for initializing CAAM's stream id
Alison Wang [Fri, 16 Jan 2015 09:21:34 +0000 (17:21 +0800)]
arm: ls1021x: Add support for initializing CAAM's stream id

There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: workaround for cache coherency problem
chenhui zhao [Fri, 23 Jan 2015 07:53:53 +0000 (15:53 +0800)]
arm: ls102xa: workaround for cache coherency problem

The RCPM FSM may not be reset after power-on, for example,
in the cases of cold boot and wakeup from deep sleep.
It causes cache coherency problem and may block deep sleep.
Therefore, reset them if they are not be reset.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodriver/pci: add Layerscape PCIe driver
Minghuan Lian [Wed, 21 Jan 2015 09:29:20 +0000 (17:29 +0800)]
driver/pci: add Layerscape PCIe driver

The patch adds Freescale Layerscape PCIe driver and provides
up to 4 controllers support.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm/ls1021a: add PCIe settings
Minghuan Lian [Wed, 21 Jan 2015 09:29:19 +0000 (17:29 +0800)]
arm/ls1021a: add PCIe settings

The patch enables and adds PCIe settings for boards LS1021AQDS
and LS1021ATWR.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm/ls102xa: use a array to define pexmscportsr
Minghuan Lian [Wed, 21 Jan 2015 09:29:18 +0000 (17:29 +0800)]
arm/ls102xa: use a array to define pexmscportsr

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm/ls102xa: create TLB to map PCIe region
Minghuan Lian [Wed, 21 Jan 2015 09:29:17 +0000 (17:29 +0800)]
arm/ls102xa: create TLB to map PCIe region

LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins
0x48_00000000. In order to access PCIe device, we must create
TLB to map the 40bit physical address to 32bit virtual address.
This patch will enable MMU after DDR is available and creates MMU
table in DRAM to map all 4G space; then, re-use the reserved space
to map PCIe region. The following the mapping layout.

VA mapping:
    -------  <---- 0GB
   |       |
   |       |
   |-------| <---- 0x24000000
   |///////|  ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
   |-------| <---- 0x300000000
   |       |
   |-------| <---- 0x34000000
   |///////|  ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
   |-------| <---- 0x40000000
   |       |
   |-------| <---- 0x80000000 DDR0 space start
   |\\\\\\\|
   |\\\\\\\|  ===> 2GB VA map for 2GB DDR0 Memory space
   |\\\\\\\|
   -------  <---- 4GB DDR0 space end

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Define default values for some CCSR macros
Alison Wang [Fri, 16 Jan 2015 09:23:04 +0000 (17:23 +0800)]
arm: ls102xa: Define default values for some CCSR macros

This patch is to define default values for some CCSR macros
to make header files cleaner.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers/mc: Migrated MC Flibs to 0.5.2
J. German Rivera [Tue, 6 Jan 2015 21:19:02 +0000 (13:19 -0800)]
drivers/mc: Migrated MC Flibs to 0.5.2

Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv8/ls2085a_emu: Enable sync of refresh
York Sun [Tue, 6 Jan 2015 21:19:01 +0000 (13:19 -0800)]
armv8/ls2085a_emu: Enable sync of refresh

Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers
stay in sync. DP-DDR has only one controller so it does no harm.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agoarmv8/fsl-lsch3: Enable erratum workround for A008514
York Sun [Tue, 6 Jan 2015 21:19:00 +0000 (13:19 -0800)]
armv8/fsl-lsch3: Enable erratum workround for A008514

Erratum A008514 appleis to ls2085a.

Signed-off-by: York Sun <yorksun@freescale.com>