Simon Glass [Sun, 17 Jan 2016 23:11:31 +0000 (16:11 -0700)]
x86: ivybridge: Move northbridge and PCH init into drivers
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:30 +0000 (16:11 -0700)]
x86: Bring up northbridge, pch and lpc after the CPUs
These devices currently need to be inited early in boot. Once we have the
init in the right places (with each device doing its own init and no
problems with ordering) we should be able to remove this. For now it is
needed to keep things working.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:29 +0000 (16:11 -0700)]
x86: Don't show an error when the MRC cache is up to date
When the final MRC cache record is the same as the one we want to write, we
skip writing since there is no point. This is normal behaviour.
Avoiding printing an error when this happens.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:28 +0000 (16:11 -0700)]
x86: Make x86_init_cpus() static
There are no other implementations of this function, and boards that need it
can implement a CPU driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:27 +0000 (16:11 -0700)]
x86: ivybridge: Move early init code into northbridge.c
This code is now part of the northbridge driver, so move it into the same
place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:26 +0000 (16:11 -0700)]
x86: ivybridge: Drop the dead MTRR code
This is not used and MTRRs are set up elsewhere now. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:25 +0000 (16:11 -0700)]
x86: ivybridge: Set up the thermal target correctly
This uses a non-existent node at present. It should use the first CPU node.
The referenced property does not exist (the correct value is the default of
0), but this allows the follow-on init to complete.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:24 +0000 (16:11 -0700)]
x86: ivybridge: Move CPU init code into the driver
Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:23 +0000 (16:11 -0700)]
x86: ivybridge: Use common CPU init code
The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs are set up. Also enable the 'cpu' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:22 +0000 (16:11 -0700)]
x86: ivybridge: Move GPIO init to the LPC init() method
This init can happen in the driver also. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:21 +0000 (16:11 -0700)]
x86: ivybridge: Move sandybridge init to the lpc probe() method
The watchdog can be reset later when probing the LPC after relocation.
Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:20 +0000 (16:11 -0700)]
x86: ivybridge: Move graphics init much later
We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:19 +0000 (16:11 -0700)]
x86: ivybridge: Probe the LPC in CPU init
We can drop the explicit probe of the PCH since the LPC is a child device
and this will happen automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:18 +0000 (16:11 -0700)]
x86: ivybridge: Rename lpc_init() to lpc_init_extra()
In preparation for adding an init() method to the LPC uclass, rename this
existing function so that it will not conflict.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:17 +0000 (16:11 -0700)]
x86: ivybridge: Move LPC and PCH init into northbridge probe()
Move more code into the northbridge probe() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:16 +0000 (16:11 -0700)]
x86: ivybridge: Move northbridge init into the probe() method
Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:15 +0000 (16:11 -0700)]
x86: ivybridge: Add a driver for the bd82x6x northbridge
Add a driver with an empty probe function where we can move init code in
follow-on patches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:14 +0000 (16:11 -0700)]
dm: x86: Add a northbridge uclass
Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:13 +0000 (16:11 -0700)]
x86: ivybridge: Rename bd82x6x_init()
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:12 +0000 (16:11 -0700)]
x86: ivybridge: Move more init to the probe() function
Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:11 +0000 (16:11 -0700)]
x86: ivybridge: Move lpc_early_init() to probe()
Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:10 +0000 (16:11 -0700)]
x86: ivybridge: Set up the LPC device using driver model
Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:09 +0000 (16:11 -0700)]
dm: pci: Convert bios_emu to use the driver model PCI API
At present this BIOS emulator uses a bus/device/function number. Change
it to use a device if CONFIG_DM_PCI is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:08 +0000 (16:11 -0700)]
dm: syscon: Allow finding devices by driver data
We have a way to find a regmap by its syscon driver data value. Add the same
for syscon itself.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:07 +0000 (16:11 -0700)]
dm: usb: Add a compatible string for PCI EHCI controller
Add a compatible string to allow this to be specified in the device tree
if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Jan 2016 23:11:06 +0000 (16:11 -0700)]
dm: core: Display the error number when driver binding fails
This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not
compiled in. Display the error number to make this easier to spot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:32 +0000 (21:32 -0700)]
dm: x86: Drop the weak cpu_irq_init() function
There are no callers now. Platforms which need to set up interrupts their
own way can implement an interrupt driver. Drop this function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:31 +0000 (21:32 -0700)]
dm: x86: queensbay: Add an interrupt driver
Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:30 +0000 (21:32 -0700)]
dm: x86: quark: Add an interrupt driver
Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:29 +0000 (21:32 -0700)]
x86: Drop the irq router compatible string
We use driver model for this now, so we don't need this string.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:28 +0000 (21:32 -0700)]
x86: Use the IRQ device when setting up the mptable
Instead of searching for the device tree node, use the IRQ device which has
a record of it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:27 +0000 (21:32 -0700)]
dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:26 +0000 (21:32 -0700)]
dm: x86: Set up interrupt routing from interrupt_init()
At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().
This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.
Drop pirq_init() since it is no-longer used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 20 Jan 2016 04:32:25 +0000 (21:32 -0700)]
dm: x86: Create a driver for x86 interrupts
It seems likely that at some point we will want a generic interrupt uclass.
But this is a big undertaking as it involves unifying code across multiple
architectures.
As a first step, create a simple IRQ uclass and a driver for x86. This can
be generalised later as required.
Adjust pirq_init() to probe this driver, which has the effect of creating
routing tables and setting up the interrupt routing. This is a start
towards making interrupts fit better with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:21 +0000 (20:19 -0700)]
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:20 +0000 (20:19 -0700)]
spi: ich: Separate out the read/write trace from normal debugging
The trace is seldom useful for basic debugging. Allow it to be enabled
separately so that it is easier to see the more important init and error
debug messages.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:19 +0000 (20:19 -0700)]
dm: x86: Add a driver for Intel PCH9
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:18 +0000 (20:19 -0700)]
dm: x86: Add a driver for Intel PCH7
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:17 +0000 (20:19 -0700)]
dm: Expand the uclass for Platform Controller Hubs (PCH)
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.
We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:16 +0000 (20:19 -0700)]
dm: pci: Avoid using pci_bus_to_hose() in the uclass
This function is only available for compatibility with old code. Avoid
using it in the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:15 +0000 (20:19 -0700)]
dm: pci: Add a function to write a BAR
Add a driver-model version of the pci_write_bar32 function so that this is
supported in the new API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 19 Jan 2016 03:19:14 +0000 (20:19 -0700)]
dm: pci: Move pci_bus_to_hose() to compatibility
This function should not be used by driver-model code, so move it to the
compatibility portion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Fri, 22 Jan 2016 22:01:22 +0000 (17:01 -0500)]
Merge git://git.denx.de/u-boot-fdt
Thomas Chou [Wed, 6 Jan 2016 01:49:24 +0000 (09:49 +0800)]
devicetree: use wildcard to clean arch subdir
Use wildcard to clean arch subdirectories, as it is cleaner than
listing all the arch which builds dtb.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 22 Jan 2016 02:45:25 +0000 (19:45 -0700)]
rockchip: Update the README
GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC.
There is an implementation to run the CPU at full speed although it does
not seem to make much difference.
Update the README to cover recent developments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:24 +0000 (19:45 -0700)]
rockchip: Add support for Raxda Rock 2
This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.
So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.
Thanks to Tom Cubie for sending me a board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:23 +0000 (19:45 -0700)]
rockchip: rock2: dts: Make changes for U-Boot
Add the required pre-relocation tags and SDRAM init information for U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:22 +0000 (19:45 -0700)]
rockchip: rock2: Bring in device tree files from Linux
Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:21 +0000 (19:45 -0700)]
rockchip: dts: Sync up SPDIF node with Linux
This has been added and we have references to it in the rock2 board. Add
this node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:20 +0000 (19:45 -0700)]
rockchip: firefly-rk3288: Enable HDMI output
Enable HDMI output and a console on firefly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:19 +0000 (19:45 -0700)]
rockchip: jerry: Enable EDP and HDMI video output
Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:18 +0000 (19:45 -0700)]
rockchip: jerry: Add support for timing SPI flash speed
Add the 'time' and 'sf test' commands so that we can test SPI flash
performance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:17 +0000 (19:45 -0700)]
rockchip: spl: Support full-speed CPU in SPL
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:16 +0000 (19:45 -0700)]
rockchip: rk3288: pinctrl: Fix HDMI pinctrl
Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:15 +0000 (19:45 -0700)]
rockchip: rk3288: clock: Fix various minor errors
Fix a number of small errors which were found in reviewing the clock code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:14 +0000 (19:45 -0700)]
rockchip: jerry: Fix the SDRAM timing
There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:13 +0000 (19:45 -0700)]
rockchip: spl: Drop MMC support code when not needed
When the board does not use MMC SPL this code is a waste of space. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:12 +0000 (19:45 -0700)]
rockchip: Tidy up the register-access macros
These work reasonable well, but there are a few errors:
- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:11 +0000 (19:45 -0700)]
rockchip: sdram: Use syscon_get_first_range() where possible
This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:10 +0000 (19:45 -0700)]
rockchip: sdram: Tidy up a few comments
Fix spaces in two comments in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:09 +0000 (19:45 -0700)]
rockchip: config: Enable the 'gpio' command
Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:08 +0000 (19:45 -0700)]
rockchip: Add a script to parse datasheets
This script has proved useful for parsing datasheets and creating register
shift/mask values for use in header files. Include it in case it is useful
for others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:07 +0000 (19:45 -0700)]
rockchip: Add a simple 'clock' command
Add a command that displays the PLLs and their current rate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:06 +0000 (19:45 -0700)]
rockchip: Don't skip low-level init
At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:05 +0000 (19:45 -0700)]
rockchip: video: Add a video-output driver
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:04 +0000 (19:45 -0700)]
rockchip: video: Add a display driver for rockchip eDP
Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:03 +0000 (19:45 -0700)]
rockchip: video: Add a display driver for rockchip HDMI
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.
Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:02 +0000 (19:45 -0700)]
rockchip: clk: Add support for clocks needed by the displays
The displays need to use NPLL and also select some new peripheral clocks.
Add support for these to the clock driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:01 +0000 (19:45 -0700)]
rockchip: Rename the CRU_MODE_CON fields
These should match the datasheet naming. Adjust them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:45:00 +0000 (19:45 -0700)]
dm: video: Repurpose the 'displayport' uclass to 'display'
The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.
Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.
Also update nyan-big which is affected by this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:59 +0000 (19:44 -0700)]
video: panel: Add a simple panel driver
Most panels are very simple - they just have a power supply and a backlight.
Add a driver which supports this and implements the enable_backlight()
method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:58 +0000 (19:44 -0700)]
dm: panel: Add a panel uclass
LCD panels can usefully be modelled as their own uclass. They can be probed
(which powers them up ready for use). If they have a backlight, this can be
enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:57 +0000 (19:44 -0700)]
dm: backlight: Add a driver for a PWM backlight
Many backlights need to use a PWM to control the brightness. Add a driver
for this. It understands the standard device tree binding.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:56 +0000 (19:44 -0700)]
dm: backlight: Add a backlight uclass
LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:55 +0000 (19:44 -0700)]
pwm: rockchip: Add a PWM driver for Rockchip SoCs
Add a simple driver which implements the standard PWM uclass interface.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:54 +0000 (19:44 -0700)]
dm: pwm: Add a PWM uclass
Add a uclass that supports Pulse Width Modulation (PWM) devices. It
provides methods to enable/disable and configure the device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:53 +0000 (19:44 -0700)]
video: bridge: Allow GPIOs to be optional
Some video bridges will not have GPIOs to control reset, etc. Allow these
to be optional.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:52 +0000 (19:44 -0700)]
video: Add a function to control cache flushing
Allow the cache-flushing function of a video device to be controlled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:51 +0000 (19:44 -0700)]
video: Name consoles by their number
We must use the console name in the 'stdout' variable to select the one
we want. At present the name is formed from the driver name with a suffix
indicating the rotation value.
It seems better to name them sequentially since this can be controlled by
driver order. So adjust the code to use 'vidconsole' for the first,
'vidconsole1' for the second, etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:50 +0000 (19:44 -0700)]
gpio: Warn about invalid GPIOs used with the 'gpio' command
At present there is no indication that an invalid GPIO is used except that
the GPIO status is not displayed. Make the error more explicit to avoid
confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:49 +0000 (19:44 -0700)]
stdio: Correct a build error with driver model
When driver model is used for video but not for the keyboard, a compiler
warnings is produced. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:13 +0000 (19:44 -0700)]
rockchip: jerry: Enable the Chrome OS EC
Turn on the EC and enable the keyboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:12 +0000 (19:44 -0700)]
rockchip: spi: Remove the explicit pinctrl setting
The correct pinctrl is handled automatically so we don't need to do it in
the driver. The exception is when we want to use a different chip select
(other than 0). But this isn't used at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:11 +0000 (19:44 -0700)]
rockchip: spi: Correct chip-enable code
At present there is an incorrect call to rkspi_enable_chip(). It should
be disabling the chip, not enabling it. Correct this and ensure that the
chip is disabled when releasing the bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:10 +0000 (19:44 -0700)]
rockchip: spi: Implement the delays
Some devices need delays before and after activiation. Implement these
features in the SPI driver so that we will be able to enable the Chrome
OS EC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:09 +0000 (19:44 -0700)]
rockchip: gpio: Implement the get_function() method
Provide this method so that 'gpio status' works fully. It now shows
whether a pin is used for input, output or some other function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:08 +0000 (19:44 -0700)]
rockchip: gpio: Read the GPIO value correctly
This function should return 0 or 1, not a mask. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:07 +0000 (19:44 -0700)]
rockchip: pinctrl: Implement the get_gpio_mux() method
Implement this so that the GPIO command will be able to report whether a
GPIO is used for input or output.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:06 +0000 (19:44 -0700)]
rockchip: pinctrl: Reduce the size for SPL
This file has many features that are not needed by SPL. Use #ifdef to
remove the unused features and reduce the code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:05 +0000 (19:44 -0700)]
rockchip: clk: Make rkclk_get_clk() SoC-specific
The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.
Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:04 +0000 (19:44 -0700)]
rockchip: spi: Correct the bus init code
Two of the init values are created locally so cannot be out of range.
The masking is unnecessary and in one case is incorrect. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:03 +0000 (19:44 -0700)]
rockchip: spi: Remember the last speed to avoid re-setting it
Rather than changing the clock to the same value on every transaction,
remember the last value and don't adjust the clock unless it is necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:02 +0000 (19:44 -0700)]
rockchip: reset: Use the rk_clr/setreg() interface
Use this function in preference to the macro.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:01 +0000 (19:44 -0700)]
rockchip: sdram: Use the rk_clr/setreg() interface
Use this function in preference to the macro.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:44:00 +0000 (19:44 -0700)]
dm: clk: Add a simple version of clk_get_by_index()
This function adds quite a bit of code to SPL and we probably don't need
all the features in SPL. Add a simple version (for SPL only) to save space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:43:59 +0000 (19:43 -0700)]
dm: power: Allow regulators to not implement all operations
Some regulators will not implement any operations (e.g. fixed regulators).
This is not an error, so allow the autoset process to continue when one
of these regulators is found.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:43:58 +0000 (19:43 -0700)]
dm: power: Tidy up debugging output and return values
The currect PMIC debugging is a little confusing. Adjust it so that it is
clear whether the operation succeeded or failed. Also, avoid creating a new
error return value when a perfectly good one is already available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:43:57 +0000 (19:43 -0700)]
dm: core: Export uclass_find_device_by_of_offset()
It is sometimes useful to be able to find a device before probing it,
perhaps to set up some platform data for it. Allow finding by of_offset
also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:43:56 +0000 (19:43 -0700)]
dm: pinctrl: Add a way for a GPIO driver to obtain a pin function
GPIO drivers want to be able to show if a pin is enabled for input, output,
or is being used by another function. Some drivers can easily find this
and the code is included in the driver. For some SoCs this is more complex.
Conceptually this should be handled by pinctrl rather than GPIO. Most
pinctrl drivers will have this feature anyway.
Add a method by which a GPIO driver can obtain the pin mux value given a
GPIO reference. This avoids repeating the code in two places.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 22 Jan 2016 02:43:55 +0000 (19:43 -0700)]
dm: power: Allow regulators to be omitted from SPL
For some boards the pmic interface is useful but the regulator interface
(which comes with it) is too large. Allow them to be separated such that
SPL can decide which it needs.
Signed-off-by: Simon Glass <sjg@chromium.org>