oweals/u-boot.git
5 years agopico-imx7d: Add LCD support
Fabio Estevam [Tue, 11 Dec 2018 18:40:38 +0000 (16:40 -0200)]
pico-imx7d: Add LCD support

Add support for the VXT VL050-8048NT-C01 panel connected through
the 24 bit parallel LCDIF interface.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
5 years agomx7: Do not call lcdif_power_down() in the SPL case
Fabio Estevam [Tue, 11 Dec 2018 18:40:37 +0000 (16:40 -0200)]
mx7: Do not call lcdif_power_down() in the SPL case

Like it was done on imx6 in commit 9236269de57d ("imx: mx6: Fix
implementantion reset_misc")

Do not call lcdif_power_down() in the SPL case to fix the following
build error:

  LD      spl/u-boot-spl
  MKIMAGE u-boot.img
arch/arm/mach-imx/built-in.o: In function `reset_misc':
/home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372: undefined reference to `lcdif_power_down'
scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoimx: Add PHYTEC phyBOARD-i.MX6UL-Segin
Martyn Welch [Tue, 11 Dec 2018 11:34:46 +0000 (11:34 +0000)]
imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
5 years agoEnable FEC driver to retrieve PHY address from device tree
Martyn Welch [Tue, 11 Dec 2018 11:34:45 +0000 (11:34 +0000)]
Enable FEC driver to retrieve PHY address from device tree

Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
5 years agoimx: hab: Convert non-NULL IVT DCD pointer warning to an error
Breno Matheus Lima [Fri, 7 Dec 2018 22:31:49 +0000 (22:31 +0000)]
imx: hab: Convert non-NULL IVT DCD pointer warning to an error

The following NXP application notes and manual recommend to ensure the
IVT DCD pointer is Null prior to calling HAB API authenticate_image()
function:

- AN12263: HABv4 RVT Guidelines and Recommendations
- AN4581: Secure Boot on i.MX50, i.MX53, i.MX 6 and i.MX7 Series using
  HABv4
- CST docs: High Assurance Boot Version 4 Application Programming
  Interface Reference Manual

Commit ca89df7dd46f ("imx: hab: Convert DCD non-NULL error to warning")
converted DCD non-NULL error to warning due to the lack of documentation
at the time of first patch submission. We have warned U-Boot users since
v2018.03, and it makes sense now to follow the NXP recommendation to
ensure the IVT DCD pointer is Null.

DCD commands should only be present in the initial boot image loaded by
the SoC ROM. Starting in HAB v4.3.7 the HAB code  will generate an error
if a DCD pointer is present in an image being authenticated by calling the
HAB RVT API. Older versions of HAB will process and run DCD if it is
present, and this could lead to an incorrect authentication boot flow.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sunxi
Tom Rini [Thu, 24 Jan 2019 20:30:48 +0000 (15:30 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-sunxi

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-net
Tom Rini [Thu, 24 Jan 2019 20:30:06 +0000 (15:30 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-net

5 years agoMerge tag 'mpc85xx-for-v2019.04-rc1' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Thu, 24 Jan 2019 20:29:45 +0000 (15:29 -0500)]
Merge tag 'mpc85xx-for-v2019.04-rc1' of git://git.denx.de/u-boot-mpc85xx

mpc85xx config.mk: Add support for -msingle-pic-base

5 years agonet: phy: aquantia: Print information on config
Valentin-catalin Neacsu [Tue, 6 Nov 2018 12:16:54 +0000 (12:16 +0000)]
net: phy: aquantia: Print information on config

Print information about Aquantia system interface and firmware loaded
on the phy.

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: phy: aquantia: Enable autoneg when on USXGMII
Valentin-catalin Neacsu [Tue, 30 Oct 2018 09:54:46 +0000 (09:54 +0000)]
net: phy: aquantia: Enable autoneg when on USXGMII

If System Interface protocol is USXGMII then enable USXGMII autoneg

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: remove CONFIG_MCAST_TFTP
Chris Packham [Mon, 26 Nov 2018 08:00:29 +0000 (21:00 +1300)]
net: remove CONFIG_MCAST_TFTP

No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).

Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: move ether_crc to tsec driver
Chris Packham [Mon, 26 Nov 2018 08:00:28 +0000 (21:00 +1300)]
net: move ether_crc to tsec driver

ether_crc was added to the core net code in commit 53a5c424bf86
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: phy: realtek: Add functions to read PHY's extended registers
Carlo Caione [Wed, 16 Jan 2019 11:34:50 +0000 (11:34 +0000)]
net: phy: realtek: Add functions to read PHY's extended registers

According to the datasheet to access the extended registers we have to:

1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
   Standard Registers)

Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: macb: fix mapping of registers
Ramon Fried [Thu, 27 Dec 2018 17:58:42 +0000 (19:58 +0200)]
net: macb: fix mapping of registers

Some architectures (MIPS) needs mapping to access IOMEM.
Fix that.

Fixes: f1dcc19b213d ("net: macb: Convert to driver model")

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: mvneta: Add GPIO configuration support
Aditya Prayoga [Tue, 4 Dec 2018 16:39:23 +0000 (00:39 +0800)]
net: mvneta: Add GPIO configuration support

This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.

Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]

Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Tested-by: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: mvgbe: fallback phy-mode to GMII
Chris Packham [Tue, 4 Dec 2018 06:54:30 +0000 (19:54 +1300)]
net: mvgbe: fallback phy-mode to GMII

Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: phy: micrel: fix KSZ9031 clock skew for values greater 0ps
Andreas Pretzsch [Thu, 29 Nov 2018 19:04:53 +0000 (20:04 +0100)]
net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps

For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.

The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.

Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.

Fix the check by using the bit width instead of hardcoded value(s).

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: fix env flags for eth10addr and above
Simon Goldschmidt [Thu, 22 Nov 2018 16:06:39 +0000 (17:06 +0100)]
net: fix env flags for eth10addr and above

With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10
interfaces (0..9) as the number can only have one digit.

On boards with more than 10 interfaces, this leads to the protection
and format checks being absent for eth10addr and above.

Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow
more than one digit.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: remove duplicate definition of ETHADDR_WILDCARD
Simon Goldschmidt [Thu, 22 Nov 2018 15:58:32 +0000 (16:58 +0100)]
net: remove duplicate definition of ETHADDR_WILDCARD

ETHADDR_WILDCARD is defined as the same value in both env_flags.h
and env_callback.h

As env_callback.h includes env_flags.h, remove the duplicate definition
from env_callback.h

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: explicitly assign errno to return code in case of network failure
Thomas RIENOESSL [Wed, 21 Nov 2018 14:56:07 +0000 (15:56 +0100)]
net: explicitly assign errno to return code in case of network failure

When dealing with two ethernet ports and having "netretry" set
to "once", it could occur that the connection (e.g. an ARP
request) failed, hence the status of the netloop was
"NETLOOP_FAIL". Due to the setting of "netretry", the network
logic would then switch to the other network interface,
assigning "ret" with the return value of "net_start_again()".
If this call succeeded we would return 0 (i.e. success) to
the caller when in reality the network action failed.

Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: mvpp2: mdio device per port
Baruch Siach [Wed, 21 Nov 2018 11:05:34 +0000 (13:05 +0200)]
net: mvpp2: mdio device per port

Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: mvpp2: fix lookup of mdio registers base address
Baruch Siach [Wed, 21 Nov 2018 11:05:33 +0000 (13:05 +0200)]
net: mvpp2: fix lookup of mdio registers base address

Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: designware: clear padding bytes
Simon Goldschmidt [Sat, 17 Nov 2018 09:24:42 +0000 (10:24 +0100)]
net: designware: clear padding bytes

Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.

Fix the padding code to zero out the padded bytes at the end.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: designware: fix tx packet length
Simon Goldschmidt [Sat, 17 Nov 2018 09:24:41 +0000 (10:24 +0100)]
net: designware: fix tx packet length

The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.

This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.

Fix this by correctly clearing the size mask before setting the new
length.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
5 years agonet: phy: Add clause 45 identifier to phy_device
Pankaj Bansal [Fri, 16 Nov 2018 06:26:18 +0000 (06:26 +0000)]
net: phy: Add clause 45 identifier to phy_device

The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agoMerge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblaze
Tom Rini [Thu, 24 Jan 2019 15:47:05 +0000 (10:47 -0500)]
Merge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.04

tools:
- Fix zynqmpimage generation

zynq:
- Some configs/Kconfig/DT updates
- Enable REMAKE_ELF and OF_SEPARATE
- Topic boards update
- i2c cleanups and conversion to DM_I2C

zynqmp:
- Some configs/Kconfig/DT updates
- Board config cleanup
- Move arch folder to mach-zynqmp

versal:
- Enable DM_I2C, CMD_DM

zynq-gem:
- Fix driver cache handling

i2c:
- Live tree simple update

phy:
- Fixed phy cleanup

travis:
- Wire Versal SoC

5 years agoARM: zynq: Convert Topic Miami to DM_I2C
Michal Simek [Tue, 22 Jan 2019 14:47:52 +0000 (15:47 +0100)]
ARM: zynq: Convert Topic Miami to DM_I2C

Both boards have only controllers enabled that's why move to DM_I2C is
easy.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoARM: zynq: Disable i2c for Zybo/Zybo Z7
Michal Simek [Tue, 22 Jan 2019 13:04:20 +0000 (14:04 +0100)]
ARM: zynq: Disable i2c for Zybo/Zybo Z7

There is no i2c connected in base DT that's why disable I2C commands.
Also remove zynq_zybo which is not needed now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoARM: zynq: Remove unused GEM addresses
Michal Simek [Tue, 22 Jan 2019 12:15:46 +0000 (13:15 +0100)]
ARM: zynq: Remove unused GEM addresses

With DM in place there is no need to have GEM addresses in headers. None
is using them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Remove unused GEM addresses
Michal Simek [Tue, 22 Jan 2019 12:15:01 +0000 (13:15 +0100)]
arm64: zynqmp: Remove unused GEM addresses

With DM in place there is no need to have GEM addresses in headers. None
is using them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agozynq: Kconfig: extend the bootstrap malloc() pool
Anton Gerasimov [Mon, 24 Dec 2018 01:29:04 +0000 (02:29 +0100)]
zynq: Kconfig: extend the bootstrap malloc() pool

Most of the memory is being consumed by device binding code,
more space needed for other data structures.

Z-turn board has already hit the limit, others may follow soon.

Measuring only the memory consumed in device_bind_common, I've got
the following results (in decimal):

  root_driver:               108
  mod_exp_sw:                108
  amba:                      120
  serial@e0000000 aka uart0: 112
  serial@e0001000 aka uart1: 88
  spi@e000d000 aka qspi:     120
  sdhci@e0100000 aka mmc0:   455
  sdhci@e0100000.blk:        208
  slcr@f8000000:             96
  clkc@100:                  72
  (total)                    1487 = 0x5cf of 0x600

Signed-off-by: Anton Gerasimov <tossel@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoboard: topic-miamiplus: Run IO PLL at 1000 MHz
Mike Looijmans [Fri, 18 Jan 2019 08:02:48 +0000 (09:02 +0100)]
board: topic-miamiplus: Run IO PLL at 1000 MHz

The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX
clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so
change it to run at 1000 and adjust the divisors accordingly. Also set the
GEM0 clock source to MIO instead of EMIO.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agotopic-miamiplus: Run CPU at 800MHz for speedgrade-2
Mike Looijmans [Fri, 18 Jan 2019 08:02:47 +0000 (09:02 +0100)]
topic-miamiplus: Run CPU at 800MHz for speedgrade-2

The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz.
Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoi2c: cdns: Convert to livetree function
Michal Simek [Fri, 18 Jan 2019 09:43:39 +0000 (10:43 +0100)]
i2c: cdns: Convert to livetree function

Update cadence i2c driver to support livetree
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695afa794ac018a09e79a48120d322b60d)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: versal: Enable dm command
Michal Simek [Wed, 16 Jan 2019 15:52:19 +0000 (16:52 +0100)]
arm64: versal: Enable dm command

It is useful to have this command enable to see which devices are
bind/probed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: versal: Enable i2c cadence controller and i2c command
Michal Simek [Wed, 16 Jan 2019 15:50:17 +0000 (16:50 +0100)]
arm64: versal: Enable i2c cadence controller and i2c command

Enable communication over i2c.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Move SoC sources to mach-zynqmp
Michal Simek [Thu, 17 Jan 2019 07:22:43 +0000 (08:22 +0100)]
arm64: zynqmp: Move SoC sources to mach-zynqmp

Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.

Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.

Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoARM: zynq: Convert all boards to OF_SEPARATE
Michal Simek [Tue, 15 Jan 2019 13:02:32 +0000 (14:02 +0100)]
ARM: zynq: Convert all boards to OF_SEPARATE

Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4e993476fa87d8933db0cd58d3c2d41)

Zynq mini configurations are not moved yet and it is questionable if
make sense to move them too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm: zynq: Enable CONFIG_REMAKE_ELF
Siva Durga Prasad Paladugu [Tue, 22 Jan 2019 09:04:12 +0000 (14:34 +0530)]
arm: zynq: Enable CONFIG_REMAKE_ELF

This patch enables CONFIG_REMAKE_ELF for Zynq platform
so that it generates u-boot.elf from binary which works
for all Zynq boards with OF_SEPARATE option enabled.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Convert all reference boards to OF_SEPARATE
Michal Simek [Fri, 14 Dec 2018 10:13:11 +0000 (11:13 +0100)]
arm64: zynqmp: Convert all reference boards to OF_SEPARATE

Build warning was added by:
"fdt: Add warning about CONFIG_OF_EMBED"
(sha1: 841d5fbae4e993476fa87d8933db0cd58d3c2d41)

ZynqMP mini configurations are not moved yet and it is questionable if
make sense to move them too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Align u-boot-spl.bin for boot.bin creation
Michal Simek [Wed, 16 Jan 2019 11:14:00 +0000 (12:14 +0100)]
arm64: zynqmp: Align u-boot-spl.bin for boot.bin creation

Bootrom is not capable to work with non align bootloader partition
that's why it is necessary to align it before boot.bin creation.
The patch is creating new spl/u-boot-spl-align.bin which is used only
for boot.bin.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agotools: zynqmpimage: Align image_size/image_stored_size
Michal Simek [Fri, 14 Dec 2018 09:53:54 +0000 (10:53 +0100)]
tools: zynqmpimage: Align image_size/image_stored_size

Bootrom is not capable to work with non aligned bootloader sizes.
SPL with OF_SEPARATE generates non-align images quite often that's
why this change is required before OF_SEPARATE enableding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agotravis: Wire Xilinx Versal Virt platform
Michal Simek [Thu, 20 Dec 2018 07:40:25 +0000 (08:40 +0100)]
travis: Wire Xilinx Versal Virt platform

Test Xilinx Versal Virt platform running on the v3.1.0 Qemu.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Disable MMC for for zc12xx_revA boards
Michal Simek [Tue, 15 Jan 2019 11:00:52 +0000 (12:00 +0100)]
arm64: zynqmp: Disable MMC for for zc12xx_revA boards

All these boards have no SD enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Enable FPGA_LOAD_SECURE command
Michal Simek [Tue, 15 Jan 2019 10:01:54 +0000 (11:01 +0100)]
arm64: zynqmp: Enable FPGA_LOAD_SECURE command

Enable fpga load secure feature for xilinx platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Enable ISSI flash for some platforms
Michal Simek [Tue, 15 Jan 2019 09:45:41 +0000 (10:45 +0100)]
arm64: zynqmp: Enable ISSI flash for some platforms

Enable ISSI flash for platforms. Xilinx reference boards are also used
internally with different flash part to increase coverage that's why
enable also ISSI parts for all these boards even if that board is
released only with one part.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Enable SPI on several boards
Michal Simek [Tue, 15 Jan 2019 08:30:38 +0000 (09:30 +0100)]
arm64: zynqmp: Enable SPI on several boards

Enable GQSPI driver, SF command and SPL support for some platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Setup proper SPI dependency
Michal Simek [Tue, 15 Jan 2019 09:50:39 +0000 (10:50 +0100)]
arm64: zynqmp: Setup proper SPI dependency

Select DM_SPI/DM_SPI_FLASH for the whole SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabled
Michal Simek [Tue, 15 Jan 2019 08:06:46 +0000 (09:06 +0100)]
ARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabled

Setup proper ETH/MMC dependency for the whole platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Enable net configs for zc1275
Siva Durga Prasad Paladugu [Fri, 12 Oct 2018 11:25:37 +0000 (16:55 +0530)]
arm64: zynqmp: Enable net configs for zc1275

This patch enable net configs for zc1275 board.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabled
Michal Simek [Tue, 15 Jan 2019 07:52:51 +0000 (08:52 +0100)]
arm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabled

Setup proper ETH/MMC dependency for the whole platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: versal: Setup DM_ETH/MMC if NET/MMC is enabled
Michal Simek [Tue, 15 Jan 2019 07:52:46 +0000 (08:52 +0100)]
arm64: versal: Setup DM_ETH/MMC if NET/MMC is enabled

Setup proper ETH/MMC dependency for the whole platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofpga: zynqmp: show an error message when FPGA programming fails
Luca Ceresoli [Fri, 11 Jan 2019 16:09:45 +0000 (17:09 +0100)]
fpga: zynqmp: show an error message when FPGA programming fails

When FPGA programming fails, it does so silently, unless debugging
code is enabled. This makes it hard to detect problems in production
environments.

Print the error message unconditionally so the error doesn't go
unnoticed.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Fix tcminit help text alignment
Michal Simek [Wed, 21 Nov 2018 06:49:18 +0000 (07:49 +0100)]
arm64: zynqmp: Fix tcminit help text alignment

Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: phy: Move fixed link code to separate routine
Siva Durga Prasad Paladugu [Tue, 27 Nov 2018 06:19:10 +0000 (11:49 +0530)]
net: phy: Move fixed link code to separate routine

This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agoarm64: zynqmp: Fix mmc node names to be in sync with kernel
Siva Durga Prasad Paladugu [Thu, 3 Jan 2019 10:14:24 +0000 (15:44 +0530)]
arm64: zynqmp: Fix mmc node names to be in sync with kernel

This patches renames sd nodes in dts to be in line with
kernel. This patch also modifies the references for the same
in code.
It checks mmc first to have no time penalty for new DT node names based
on left-to-right expression evaluation.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agozynq-gem: Use appropriate cache flush/invalidate for RX and TX
Stefan Theil [Mon, 17 Dec 2018 08:12:30 +0000 (09:12 +0100)]
zynq-gem: Use appropriate cache flush/invalidate for RX and TX

The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
handed to the receive handler with old contents in cache. This
only happens when a lot of packets are received without sending
packages every now and then. Also flushing the receive buffers
in the transmit function makes no sense and can be removed.

Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Protect board_late_init function
Michal Simek [Thu, 20 Dec 2018 08:33:38 +0000 (09:33 +0100)]
arm64: zynqmp: Protect board_late_init function

Function should be compiled only when CONFIG_BOARD_LATE_INIT is defined.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Do not protect zynqmp_pmufw_version()
Michal Simek [Thu, 20 Dec 2018 08:41:12 +0000 (09:41 +0100)]
arm64: zynqmp: Do not protect zynqmp_pmufw_version()

There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version()
but also FPGA code is calling this function which is possible to use
without actual CLK_ZYNQMP firmware driver to be enabled.
This patch enables the case where only fixed-clock CLK setup is used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agommc: zynq: Remove unused pwrseq variable
Michal Simek [Wed, 5 Dec 2018 11:40:55 +0000 (12:40 +0100)]
mmc: zynq: Remove unused pwrseq variable

This variable was incorrectly added by:
"mmc: zynq_sdhci: Add support for SD3.0"
(sha1: d1f4e39d58db32a4fd1a1b4085e0ede498bd773f)
which had nothing to do with MMC power sequence provider.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Enable 2 NAND chips for zc1751 dc2
Michal Simek [Mon, 3 Dec 2018 15:24:45 +0000 (16:24 +0100)]
arm64: zynqmp: Enable 2 NAND chips for zc1751 dc2

This board contains 2 nand chips that's why enable this feature.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomtd: nand: arasan_nfc: Add support for nand multi chip select
T Karthik Reddy [Mon, 3 Dec 2018 10:41:58 +0000 (16:11 +0530)]
mtd: nand: arasan_nfc: Add support for nand multi chip select

This patch adds support for nand multi chip select.
Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number
of nand chips.

Signed-off-by: Tummala Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agotools: zynqmpimage: round up partition size
Michael Tretter [Mon, 3 Dec 2018 15:37:53 +0000 (16:37 +0100)]
tools: zynqmpimage: round up partition size

The FSBL copies "Total Partition Word Length" * 4 bytes from the boot.bin,
which implies that the partition size is 4 byte aligned. When writing the
partition, mkimage calculates "Total Partition Word Length" by dividing
the size by 4. This implicitly cuts unaligned bytes at the end of the
added binary.

Instead of rounding down, the size must be round up to 4 bytes and the
binary padded accordingly.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoMerge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 23 Jan 2019 22:24:31 +0000 (17:24 -0500)]
Merge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mips

- MIPS: mscc: ocelot: add ethernet switch and network support
- MIPS: mscc: add support for ServalT SoC family
- MIPS: mscc: add support for Serval SoC family

5 years agompc85xx: Add support for -msingle-pic-base
Joakim Tjernlund [Thu, 6 Dec 2018 16:20:53 +0000 (17:20 +0100)]
mpc85xx: Add support for -msingle-pic-base

-msingle-pic-base is a new gcc(from 4.6) option for ppc and
it reduces the size of my u-boot with about 4-5 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.

e5500 core:
size u-boot.bef
   text    data     bss     dec     hex filename
 473043   23772  307104  803919   c444f u-boot.bef
size u-boot.aft
   text    data     bss     dec     hex filename
 453195   23772  307104  784071   bf6c7 u-boot.aft

e500 core:
size u-boot.bef
   text    data     bss     dec     hex filename
 292998   17868   24968  335834   51fda u-boot.bef
size u-boot.aft
   text    data     bss     dec     hex filename
 288002   17868   24968  330838   50c56 u-boot.aft

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>
5 years agoMSCC: Add board support for Serval SoC family.
Horatiu Vultur [Wed, 23 Jan 2019 15:39:45 +0000 (16:39 +0100)]
MSCC: Add board support for Serval SoC family.

Add board support and configuration for Jaguar2 SoC family.
The detection of the board type is based on the phy ids.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agoMSCC: Add device tree for Serval pcb106 board
Horatiu Vultur [Wed, 23 Jan 2019 15:39:44 +0000 (16:39 +0100)]
MSCC: Add device tree for Serval pcb106 board

Add device tree based on evaluation board pcb106.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
5 years agoMSCC: add device tree for Serval pcb105 board
Horatiu Vultur [Wed, 23 Jan 2019 15:39:43 +0000 (16:39 +0100)]
MSCC: add device tree for Serval pcb105 board

Add device tree based on evaluation board pcb105.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
5 years agoMSCC: Add support for Serval SoC family.
Horatiu Vultur [Wed, 23 Jan 2019 15:39:42 +0000 (16:39 +0100)]
MSCC: Add support for Serval SoC family.

As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agopinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
Horatiu Vultur [Wed, 23 Jan 2019 15:39:41 +0000 (16:39 +0100)]
pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.

The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agoMSCC: Add board support for Servalt SoC family
Horatiu Vultur [Thu, 17 Jan 2019 14:33:28 +0000 (15:33 +0100)]
MSCC: Add board support for Servalt SoC family

Add board support, configuration and DTS for Servalt SoC
family. Currently there is one board in this family.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
5 years agoMSCC: Add support for Servalt SoC family.
Horatiu Vultur [Thu, 17 Jan 2019 14:33:27 +0000 (15:33 +0100)]
MSCC: Add support for Servalt SoC family.

As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
5 years agopinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.
Horatiu Vultur [Thu, 17 Jan 2019 14:33:26 +0000 (15:33 +0100)]
pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.

The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
5 years agoconfigs: mscc_ocelot: add network support
Gregory CLEMENT [Thu, 17 Jan 2019 16:07:15 +0000 (17:07 +0100)]
configs: mscc_ocelot: add network support

Now that network support is added for the ocelot platform, let's add it
in the default configuration.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMIPS: mscc: ocelot: add switch reset support
Gregory CLEMENT [Thu, 17 Jan 2019 16:07:14 +0000 (17:07 +0100)]
MIPS: mscc: ocelot: add switch reset support

On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agonet: add MSCC Ocelot switch support
Gregory CLEMENT [Thu, 17 Jan 2019 16:07:13 +0000 (17:07 +0100)]
net: add MSCC Ocelot switch support

This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agoMIPS: mscc: ocelot: Add ethernet nodes for Ocelot
Gregory CLEMENT [Thu, 17 Jan 2019 16:07:12 +0000 (17:07 +0100)]
MIPS: mscc: ocelot: Add ethernet nodes for Ocelot

Import Ethernet related nodes from Linux

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMerge git://git.denx.de/u-boot-nds32
Tom Rini [Wed, 23 Jan 2019 03:00:20 +0000 (22:00 -0500)]
Merge git://git.denx.de/u-boot-nds32

- Support nds32 prebuilt toolchain.
- Fix some compile issues.
- Fix dts mmc node compatible string.

5 years agonds32: dts: Fix mmc node compatible string
Rick Chen [Tue, 15 Jan 2019 05:30:35 +0000 (13:30 +0800)]
nds32: dts: Fix mmc node compatible string

In the two commits:
cf3922dddc44a968685b535f2af195f1e51f4a7b
mmc: ftsdc010_mci: Sync compatible with DT mmc node

c14e90e8445e7b1c3531b4bdeb778c47bd6570eb
riscv: dts: Sync DT with Linux Kernel

ftsdc010_mci's compatible has been modified as
"andestech,atfsdc010" for RISC-V synchronization.
But ae3xx.dts and ag101p.dts which are used for
nds32 adp-ae3xx and adp-ag101p platforms did not
be modified correctly at that time. It will cause
mmc detection failure. Fix it here.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agonds32: Fix boot fail issue when build with elf-mculib.
Rick Chen [Tue, 15 Jan 2019 03:07:54 +0000 (11:07 +0800)]
nds32: Fix boot fail issue when build with elf-mculib.

Add -mcmodel=large can let elf-mculib have
the same default behavior just like linux-glibc.
And it help to pass U-Boot booting sequence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agonds32: Generate SW fpu instruction.
Rick Chen [Tue, 15 Jan 2019 02:41:20 +0000 (10:41 +0800)]
nds32: Generate SW fpu instruction.

Force it to generate SW fup instruction.
It help to avoid bugs when running on no-HW-fpu board, but
compile with v3f which support HW fpu instruction.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agonds32: Remove gcc unused option
Rick Chen [Thu, 10 Jan 2019 03:22:43 +0000 (11:22 +0800)]
nds32: Remove gcc unused option

-G0 is an old option, not support now,
So remove it.
It can help to fix compile error when
build with nds32 pre-build toolchain.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years ago.travis.yml: Support nds32 prebuilt toolchain
Rick Chen [Mon, 14 Jan 2019 05:36:15 +0000 (13:36 +0800)]
.travis.yml: Support nds32 prebuilt toolchain

Download nds32 prebuild toolchain from github
which is base on gcc 8.0.1 version for regression.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Mon, 21 Jan 2019 16:59:21 +0000 (11:59 -0500)]
Merge git://git.denx.de/u-boot-marvell

- Sync Armada-38x dts with Linux 4.20 from Chris
- Misc changes and enhancements to Turris Mox (v4) from Marek
- Reserve PSCI area for Armada 8k from Heinrich
- New Allied Telesis x530 board (Armada-385) from Chris
- Misc minor changes (defconfig etc)

5 years agoMerge git://git.denx.de/u-boot-mpc83xx
Tom Rini [Mon, 21 Jan 2019 16:59:00 +0000 (11:59 -0500)]
Merge git://git.denx.de/u-boot-mpc83xx

5 years agoRevert "env: sf: fix environment in SPI NOR"
Tom Rini [Mon, 21 Jan 2019 16:57:58 +0000 (11:57 -0500)]
Revert "env: sf: fix environment in SPI NOR"

Per Heiko the original changes were correct and something is misbehaving
on his hardware.

This reverts commit 3d5931e5986a49c44cdab845c6751d845812e8d8.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig
Derald D. Woods [Sat, 15 Dec 2018 07:36:46 +0000 (01:36 -0600)]
ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig

This commit converts the following items to Kconfig:

CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap

[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html

Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: Daniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoARM: mvebu: add support for Allied Telesis x530
Chris Packham [Thu, 10 Jan 2019 08:01:00 +0000 (21:01 +1300)]
ARM: mvebu: add support for Allied Telesis x530

This is a range of stackable network switches. The SoC is Armada-385 and
there are a number of variants with differing network port
configurations. The DP variants are intended for a harsher operating
environment so they use a different i2c mux and fit industrial-temp
parts.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoboard: mvebu: drop unused ETH_PHY macro definitions
Baruch Siach [Wed, 2 Jan 2019 16:26:42 +0000 (18:26 +0200)]
board: mvebu: drop unused ETH_PHY macro definitions

These macros are not used anywhere in the boards code.

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm64: mvebu: defconfig: enable CONFIG_CMD_NVME
Heinrich Schuchardt [Wed, 26 Dec 2018 09:37:55 +0000 (10:37 +0100)]
arm64: mvebu: defconfig: enable CONFIG_CMD_NVME

An NVME drive may be installed on the MACCHIATObin board using the PCIe
slot or on the Clearfog Pro using mini a PCI-e slot. With the configuration
change it becomes usable.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm64: dts: marvell: armada-ap806: reserve PSCI area
Heinrich Schuchardt [Fri, 21 Dec 2018 16:30:46 +0000 (17:30 +0100)]
arm64: dts: marvell: armada-ap806: reserve PSCI area

The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any
attempt to access it from U-Boot leads to an immediate crash.

So let's make the same memory reservation as the vendor device tree.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: configs: turris_mox: Add 64 MiB of boot memory
Marek Behún [Mon, 17 Dec 2018 15:10:10 +0000 (16:10 +0100)]
arm: mvebu: configs: turris_mox: Add 64 MiB of boot memory

This is needed for some scenarios, such as booting large FIT image.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: turris_mox: Support 1 GB version of Turris Mox
Marek Behún [Mon, 17 Dec 2018 15:10:09 +0000 (16:10 +0100)]
arm: mvebu: turris_mox: Support 1 GB version of Turris Mox

Use get_ram_size to determine if the RAM size on Turris Mox is 512 MiB
or 1 GiB.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: turris_mox: Read info (and ethaddrs) from OTP
Marek Behún [Mon, 17 Dec 2018 15:10:08 +0000 (16:10 +0100)]
arm: mvebu: turris_mox: Read info (and ethaddrs) from OTP

Add support for reading One-Time Programmable memory via mailbox, which
communicates with CZ.NIC's firmware on the Secure Processor (Cortex-M3)
of Armada 3720.

Display product serial number and additional info, and also set MAC
addresses.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoMAINTAINERS: Add entry for CZ.NIC's Turris project
Marek Behún [Mon, 17 Dec 2018 15:10:07 +0000 (16:10 +0100)]
MAINTAINERS: Add entry for CZ.NIC's Turris project

Add myself as the maintainer of CZ.NIC's Turris Omnia and Turris Mox
projects.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agowatchdog: armada_37xx: Fix compliance with kernel's driver
Marek Behún [Mon, 17 Dec 2018 15:10:06 +0000 (16:10 +0100)]
watchdog: armada_37xx: Fix compliance with kernel's driver

The Armada 37xx watchdog driver was recently accepted for mainline
kernel by watchdog subsystem maintainer, but the driver works a little
different than the one in U-Boot. This patch fixes this.

In the previous implementation there was a tiny period of time when the
watchdog was disabled and the system was vulnerables - this was during
pinging, which was done by disabling, setting, and enabling the counter.

Now pinging is done without disabling the watchdog. We use 2 counters:
Counter 1 is the watchdog counter - on expiry, the system is reset.
Counter 0 is used to reset Counter 1 to start counting from the set
timeout again. So Counter 1 is set to be reset on Counter 0 expiry event
event and pinging is done by forcing an immediate expiry event on
Counter 0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: turris_mox: Update defconfig
Marek Behún [Mon, 17 Dec 2018 15:10:05 +0000 (16:10 +0100)]
arm: mvebu: turris_mox: Update defconfig

Add gpio command to defconfig - this can be used to detect whether the
button is pressed or light LEDs.
Add DS1307 RTC driver and the date command.
Add CONFIG_WATCHDOG, so that U-Boot calls watchdog_reset.
Add CONFIG_MISC_INIT_R so that ethernet addresses are read from OTP
before network controller is initialized.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: dts: Fix Turris Mox device tree
Marek Behún [Mon, 17 Dec 2018 15:10:04 +0000 (16:10 +0100)]
arm: mvebu: dts: Fix Turris Mox device tree

DTC issues a warning because #address-cells and #size-cells properties
are not set in the mdio node.
Also add ethernet1 alias.
Also add RTC node.
Also fix USB3 regulator startup delay time.
Also fix PCI Express SERDES speed to 5 GHz (this is only cosmetic, the
speed value is not used byt the comphy driver for PCI Express, but
should be 5 GHz nonetheless).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: turris_mox: Check and configure modules
Marek Behún [Mon, 17 Dec 2018 15:10:03 +0000 (16:10 +0100)]
arm: mvebu: turris_mox: Check and configure modules

Check if Mox modules are connected in supported mode, then configure
the MDIO addresses of switch modules.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: turris_mox: Change SERDES map depending on module topology
Marek Behún [Mon, 17 Dec 2018 15:10:02 +0000 (16:10 +0100)]
arm: mvebu: turris_mox: Change SERDES map depending on module topology

When SFP module is connected directly to CPU module we want the SGMII
lane speed at 1.25 Gbps.

This is a temporary solution till there is a comphy driver in the kernel
capable of changing SGMII speed at runtime.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>