oweals/u-boot.git
8 years agoarmv8: ls1012a: Add support of ls1012aqds board
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:34 +0000 (18:41 +0530)]
armv8: ls1012a: Add support of ls1012aqds board

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: freescale: common: Add flag for LBMAP brdcfg reg offset
Abhimanyu Saini [Fri, 3 Jun 2016 13:11:33 +0000 (18:41 +0530)]
board: freescale: common: Add flag for LBMAP brdcfg reg offset

Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: freescale: common: Conditionally compile IFC QXIS func
Abhimanyu Saini [Fri, 3 Jun 2016 13:11:32 +0000 (18:41 +0530)]
board: freescale: common: Conditionally compile IFC QXIS func

Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:31 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.

This patch add support of LS1012A SoC along with
 - Update platform & DDR clock read logic as per SVR
 - Define MMDC controller register set.
 - Update LUT base address for PCIe
 - Avoid L3 platform cache compilation
 - Update USB address, errata
 - SerDes table
 - Added CSU IDs for SDHC2, SAI-1 to SAI-4

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Organize SoC overview at common location
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:30 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Organize SoC overview at common location

SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc

Also move README.lsch2 and README.lsch3 in same folder.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: fix compile warning "rcw_tmp"
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:29 +0000 (18:41 +0530)]
armv8: fsl-layerscape: fix compile warning "rcw_tmp"

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ‘rcw_tmp’ [-Wunused-variable]
  u32 rcw_tmp;

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: mtd: spi: Adding support for QSPI flash
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:28 +0000 (18:41 +0530)]
driver: mtd: spi: Adding support for QSPI flash

Serial number, vendor id and page size are added for QSPI flash
common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Avoid LS1043A specifc defines
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:27 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Avoid LS1043A specifc defines

Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Put SMMU config code in SMMU_BASE
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:26 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE

It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.

So put SMMU configuration code under SMMU_BASE.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls1043aqds: fix usb PWRFAULT setting
Shaohui Xie [Mon, 30 May 2016 06:26:55 +0000 (14:26 +0800)]
armv8: ls1043aqds: fix usb PWRFAULT setting

SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should
be used for USB 3 & 2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver/ddr/fsl: Check condition for erratum A-009803
Shengzhou Liu [Wed, 25 May 2016 08:15:00 +0000 (16:15 +0800)]
driver/ddr/fsl: Check condition for erratum A-009803

Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/ddr/fsl: Disabling data init if ECC is not enabled
York Sun [Thu, 26 May 2016 19:19:03 +0000 (12:19 -0700)]
drivers/ddr/fsl: Disabling data init if ECC is not enabled

If ECC is not enabled, data init can be disabled to speed up booting.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoboard: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined
York Sun [Thu, 26 May 2016 20:59:03 +0000 (13:59 -0700)]
board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined

U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agopcie/layerscape: fix bug in bus number computation when setting msi-map
Bogdan Purcareata [Tue, 17 May 2016 07:18:40 +0000 (07:18 +0000)]
pcie/layerscape: fix bug in bus number computation when setting msi-map

When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in
computing the bus number.

The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A
given bus number is relative to hose->first_busno, so that has to be
subtracted from the PCI device id.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Acked-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/ddr/fsl: Fix timing_cfg_2 register
York Sun [Thu, 19 May 2016 04:11:19 +0000 (21:11 -0700)]
drivers/ddr/fsl: Fix timing_cfg_2 register

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoboard: ls102xa: Fix ICID setup
Vincent Siles [Wed, 18 May 2016 12:41:14 +0000 (14:41 +0200)]
board: ls102xa: Fix ICID setup

LS102A ref manual dictates that ICID have to be written to the MSB
of the ICID register, not to the LSB.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
8 years agommc: fsl_esdhc: fix check_and_invalidate_dcache_range function
Yangbo Lu [Thu, 12 May 2016 11:12:58 +0000 (19:12 +0800)]
mmc: fsl_esdhc: fix check_and_invalidate_dcache_range function

In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard/freescale: Update ddr clk_adjust
Shengzhou Liu [Wed, 4 May 2016 02:20:22 +0000 (10:20 +0800)]
board/freescale: Update ddr clk_adjust

This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
Shengzhou Liu [Wed, 4 May 2016 02:20:21 +0000 (10:20 +0800)]
drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agospl: fit: Fix load address of fit header
Lokesh Vutla [Wed, 1 Jun 2016 04:58:31 +0000 (10:28 +0530)]
spl: fit: Fix load address of fit header

When loading fit header, it should be loaded to a previous address
aligned to ARCH_DMA_MINALIGN and not 8. Fixing the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Tue, 31 May 2016 14:26:14 +0000 (10:26 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

8 years agoMerge git://www.denx.de/git/u-boot-marvell
Tom Rini [Tue, 31 May 2016 14:26:02 +0000 (10:26 -0400)]
Merge git://www.denx.de/git/u-boot-marvell

8 years agotools/env: allow to pass NULL for environment options
Andreas Fenkart [Tue, 31 May 2016 07:21:56 +0000 (09:21 +0200)]
tools/env: allow to pass NULL for environment options

If users of the library are happy with the default, e.g. config file
name. They can pass NULL as the opts pointer. This simplifies the
transition of existing library users.
FIXES a compile error. since common_args has been removed by
a previous patch

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
8 years agoRevert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."
Masahiro Yamada [Tue, 31 May 2016 11:41:54 +0000 (20:41 +0900)]
Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."

This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3.

Since commit 56adbb387273 ("image.h: Tighten up content using handy
CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux
because the commit changed the logic of macros it touched.  Now,
IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all
the boards.

As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and
IS_ENABLED() as well) can only take a macro that is either defined
as 1 or undefined.  This is met for boolean options defined in
Kconfig.  On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and
CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in
arch/*/include/asm/config.h .  This kind of clean-up is welcome,
but the options should be moved to Kconfig beforehand.

Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird.
It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or
IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT).  But, I see no define for
CONFIG_SPL_CRC32_SUPPORT anywhere.  Likewise for the other three.

The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were
also changed for SPL.  This can be a problem for boards defining
CONFIG_SPL_OF_LIBFDT.  I guess it should have been changed to
IS_ENABLED(CONFIG_OF_BOARD_SETUP).

In the first place, if we replace the references in C code,
the macros IMAGE_* will go away.

  if (IS_ENABLED(CONFIG_OF_BOARD_SETUP) {
          ...
  }

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agomips: ath79: ap143: Reset ethernet on boot
Wills Wang [Mon, 30 May 2016 14:54:55 +0000 (22:54 +0800)]
mips: ath79: ap143: Reset ethernet on boot

This patch reset the ethernet controller for ap143 board

Signed-off-by: Wills Wang <wills.wang@live.com>
8 years agomips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define
Wills Wang [Mon, 30 May 2016 14:54:54 +0000 (22:54 +0800)]
mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang <wills.wang@live.com>
8 years agomips: ath79: Add support for ungating USB and ethernet on qca953x
Wills Wang [Mon, 30 May 2016 14:54:53 +0000 (22:54 +0800)]
mips: ath79: Add support for ungating USB and ethernet on qca953x

Add code to ungate USB and ethernet controller on qca953x

Signed-off-by: Wills Wang <wills.wang@live.com>
8 years agomips: ath79: Use 8MB flash profile for mtd partition by default
Wills Wang [Mon, 30 May 2016 14:54:52 +0000 (22:54 +0800)]
mips: ath79: Use 8MB flash profile for mtd partition by default

Change bootm flash address and mtd partition table for 8MB flash profile.

Signed-off-by: Wills Wang <wills.wang@live.com>
8 years agomips: ath79: ap121: Enable ethernet
Wills Wang [Mon, 30 May 2016 14:54:51 +0000 (22:54 +0800)]
mips: ath79: ap121: Enable ethernet

This patch enable network function for ap121 board.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
8 years agomips: ath79: Rename get_bootstrap into ath79_get_bootstrap
Wills Wang [Mon, 30 May 2016 14:54:50 +0000 (22:54 +0800)]
mips: ath79: Rename get_bootstrap into ath79_get_bootstrap

Add a platform prefix for function name in order to make more readable,
and move it into ath79.h

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
8 years agoMIPS: malta: add defconfigs for MIPS64
Daniel Schwierzeck [Mon, 30 May 2016 11:00:21 +0000 (13:00 +0200)]
MIPS: malta: add defconfigs for MIPS64

Add defconfigs for recently introduced MIPS64 support on
Malta boards to get more build coverage for MIPS64.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoMIPS: Abstract cache op loops with a macro
Paul Burton [Fri, 27 May 2016 13:28:06 +0000 (14:28 +0100)]
MIPS: Abstract cache op loops with a macro

The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code & will allow for not adding
further duplication when introducing L2 cache support.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Split I & D cache line size config
Paul Burton [Fri, 27 May 2016 13:28:05 +0000 (14:28 +0100)]
MIPS: Split I & D cache line size config

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoMIPS: Move cache sizes to Kconfig
Paul Burton [Fri, 27 May 2016 13:28:04 +0000 (14:28 +0100)]
MIPS: Move cache sizes to Kconfig

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: remove dead code from asm/u-boot-mips.h
Daniel Schwierzeck [Fri, 27 May 2016 13:31:34 +0000 (15:31 +0200)]
MIPS: remove dead code from asm/u-boot-mips.h

Those wrappers for linker symbols were once used in the MIPS
specific board.c implementation. Since the migration to generic
board.c, those wrappers are dead code and can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agonet: Add ag7xxx driver for Atheros MIPS
Marek Vasut [Tue, 24 May 2016 21:29:09 +0000 (23:29 +0200)]
net: Add ag7xxx driver for Atheros MIPS

Add ethernet driver for the AR933x and AR934x Atheros MIPS machines.
The driver could be easily extended to other WiSoCs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Wills Wang <wills.wang@live.com>
[fixed Kconfig dependency]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoMIPS: add tune for MIPS 34kc
Daniel Schwierzeck [Fri, 27 May 2016 13:39:39 +0000 (15:39 +0200)]
MIPS: add tune for MIPS 34kc

Add tune Kconfig option for MIPS 34kc.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoMIPS: provide a default u-boot-spl.lds
Daniel Schwierzeck [Thu, 26 May 2016 13:28:38 +0000 (15:28 +0200)]
MIPS: provide a default u-boot-spl.lds

Provide a default linker script for SPL binaries. Start address
and size of text section and BSS section are configurable. All
sections are arranged in a way that only relevant sections are
kept in the code section for maximum size reduction. All other
sections are kept but moved outside the code section to help
with debugging.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
8 years agomalta: Allow MIPS64 builds
Paul Burton [Thu, 26 May 2016 13:49:36 +0000 (14:49 +0100)]
malta: Allow MIPS64 builds

Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agonet: pcnet: Fix init on big endian 64 bit
Paul Burton [Thu, 26 May 2016 16:32:29 +0000 (17:32 +0100)]
net: pcnet: Fix init on big endian 64 bit

If dev->iobase is 64 bits wide then writing the value of the BAR into a
pointer to iobase will not work on big endian systems, where the BAR
value will incorrectly get written to the upper 32 bits of the 64 bit
variable. Fix this by reading the BAR into a u32, matching the type
expected by pci_read_config_dword.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agonet: pcnet: Make 64 bit safe
Paul Burton [Thu, 26 May 2016 13:49:35 +0000 (14:49 +0100)]
net: pcnet: Make 64 bit safe

Fix the pcnet driver to build safely on 64 bit platforms, in preparation
for allowing MIPS64 builds for Malta boards.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: pcnet: Stop converting kseg1->kseg0 addresses
Paul Burton [Thu, 26 May 2016 13:49:34 +0000 (14:49 +0100)]
net: pcnet: Stop converting kseg1->kseg0 addresses

Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop
manually converting addresses to their kseg0 equivalents in the pcnet
driver.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Use CPHYSADDR to implement mips32 virt_to_phys
Paul Burton [Thu, 26 May 2016 13:49:33 +0000 (14:49 +0100)]
MIPS: Use CPHYSADDR to implement mips32 virt_to_phys

Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.

This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:

    https://patchwork.linux-mips.org/patch/12564/

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoarm: spear: x600: Remove EFI support to reduce image size
Stefan Roese [Wed, 27 Apr 2016 07:10:43 +0000 (09:10 +0200)]
arm: spear: x600: Remove EFI support to reduce image size

EFI is not needed on x600. So lets remove the EFI support to make it fit
into the 0x60000 image size limit again.

Signed-off-by: Stefan Roese <sr@denx.de>
8 years agoarm: spear: x600: Add support for Micrel KSZ9031 PHY
Stefan Roese [Wed, 27 Apr 2016 07:10:42 +0000 (09:10 +0200)]
arm: spear: x600: Add support for Micrel KSZ9031 PHY

As the old ethernet PHY is not available any more, the x600 board has
been redesigned with the Micrel KSZ9031 PHY. This patch adds support
to autodetect the PHY and configure the Micrel PHY correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
8 years agoclearfog: add HUSH parser
Peter Robinson [Thu, 26 May 2016 08:48:24 +0000 (09:48 +0100)]
clearfog: add HUSH parser

In the big move of CONFIG_HUSH_PARSER to config files the clearfog
somehow missed out.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Mon, 30 May 2016 17:56:26 +0000 (13:56 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-x86

8 years agox86: baytrail: acpi: Fix I/O APIC ID in the MADT table
Bin Meng [Thu, 26 May 2016 02:19:13 +0000 (19:19 -0700)]
x86: baytrail: acpi: Fix I/O APIC ID in the MADT table

So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: galileo: Enable ACPI table generation
Bin Meng [Thu, 26 May 2016 02:19:12 +0000 (19:19 -0700)]
x86: galileo: Enable ACPI table generation

Enable ACPI table generation by creating a DSDT table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: quark: Generate ACPI FADT/MADT tables
Bin Meng [Thu, 26 May 2016 02:19:11 +0000 (19:19 -0700)]
x86: quark: Generate ACPI FADT/MADT tables

Generate quark platform-specific FADT/MADT tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: quark: Add platform ASL files
Bin Meng [Thu, 26 May 2016 02:19:10 +0000 (19:19 -0700)]
x86: quark: Add platform ASL files

This adds basic quark platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: quark: Prepare device.h for inclusion by ASL
Bin Meng [Thu, 26 May 2016 02:19:09 +0000 (19:19 -0700)]
x86: quark: Prepare device.h for inclusion by ASL

There is a device.h for quark on-chip devices, mainly for definitions
of internal PCI device numbers, but it's not ready to be included by
ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoacpi: Pass -D__ASSEMBLY__ when compiling ASL files
Bin Meng [Thu, 26 May 2016 02:19:08 +0000 (19:19 -0700)]
acpi: Pass -D__ASSEMBLY__ when compiling ASL files

ASL files may include various U-Boot header files, but IASL compiler
does not understand any C language embedded in these header files.
To reuse those header files for ASL compiling, use __ASSEMBLY__ in
the header files to exclude everything that is not liked by IASL.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: acpi: Make irqroute.asl common
Bin Meng [Thu, 26 May 2016 02:19:07 +0000 (19:19 -0700)]
x86: acpi: Make irqroute.asl common

The irqroute.asl file is already common enough to all x86 platforms.
Platform ASL files need only provide a irqroute.h to describe how
internal PCI devices and PCIe downstream port devices' INTx pins are
routed to which PIRQ pin.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: acpi: Create a common irqlinks ASL file
Bin Meng [Thu, 26 May 2016 02:19:06 +0000 (19:19 -0700)]
x86: acpi: Create a common irqlinks ASL file

Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Fri, 27 May 2016 19:49:43 +0000 (15:49 -0400)]
Merge git://git.denx.de/u-boot-dm

For odroid-c2 (arch-meson) for now disable designware eth as meson
now needs to do some harder GPIO work.

Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
lib/efi_loader/efi_disk.c

Modified:
configs/odroid-c2_defconfig

8 years agoMerge git://git.denx.de/u-boot-rockchip
Tom Rini [Fri, 27 May 2016 19:48:53 +0000 (15:48 -0400)]
Merge git://git.denx.de/u-boot-rockchip

8 years agoARM: OMAP4+: Fix DPLL programming sequence
Lokesh Vutla [Mon, 23 May 2016 08:01:19 +0000 (13:31 +0530)]
ARM: OMAP4+: Fix DPLL programming sequence

All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
8 years agotools: Add entry for generated tools/bin2header to tools/.gitignore
Robert P. J. Day [Sun, 22 May 2016 09:46:05 +0000 (05:46 -0400)]
tools: Add entry for generated tools/bin2header to tools/.gitignore

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
8 years agotools/genboardscfg.py: remove bogus import subprocess
Masahiro Yamada [Sun, 22 May 2016 06:16:47 +0000 (15:16 +0900)]
tools/genboardscfg.py: remove bogus import subprocess

Since f6c8f38ec601 ("tools/genboardscfg.py: improve performance more
with Kconfiglib"), this tool does not use the subprocess module.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoimage.h: Tighten up content using handy CONFIG_IS_ENABLED() macro.
Robert P. J. Day [Sat, 21 May 2016 09:06:31 +0000 (05:06 -0400)]
image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro.

In order for CONFIG_IS_ENABLED(FOO) to work we need to move the changes
that CONFIG_FIT_DISABLE_SHA256 makes to be prior to the evaluation by
CONFIG_IS_ENABLED(foo)

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Move CONFIG_FIT_DISABLE_SHA256 parts to fix build breakage]
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoarm64: rename __asm_flush_dcache_level to __asm_dcache_level
Masahiro Yamada [Tue, 17 May 2016 07:38:08 +0000 (16:38 +0900)]
arm64: rename __asm_flush_dcache_level to __asm_dcache_level

Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation.  So, it is better to not include "flush" in
this routine name.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoarm64: fix comment "flush & invalidate"
Masahiro Yamada [Tue, 17 May 2016 07:38:07 +0000 (16:38 +0900)]
arm64: fix comment "flush & invalidate"

We should say "clean & invalidate", or simply "flush".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoarm64: optimize __asm_{flush, invalidate}_dcache_all
Masahiro Yamada [Tue, 17 May 2016 07:38:06 +0000 (16:38 +0900)]
arm64: optimize __asm_{flush, invalidate}_dcache_all

__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.

We do not have to waste x16 register here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: am335x: Allow to choose serial device dynamically
Lokesh Vutla [Mon, 16 May 2016 06:17:29 +0000 (11:47 +0530)]
board: am335x: Allow to choose serial device dynamically

Different AM335x based platforms have different serial consoles. As serial
console is Kconfig option a separate defconfig has to be created for each
platform. So pass the serial device dynamically.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: dts: AM335x-ICEv2: Add minimal dts support
Lokesh Vutla [Mon, 16 May 2016 06:17:28 +0000 (11:47 +0530)]
ARM: dts: AM335x-ICEv2: Add minimal dts support

Add minimal dts support for AM335x-ICEv2 board

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
8 years agoconfig: env: Set AM335x-ICEv2 board specific env
Lokesh Vutla [Mon, 16 May 2016 06:17:27 +0000 (11:47 +0530)]
config: env: Set AM335x-ICEv2 board specific env

Populate the right dtb file and console for AM335x-ICEv2 board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoboard: AM335x-ICEv2: Add cpsw support
Lokesh Vutla [Mon, 16 May 2016 06:17:26 +0000 (11:47 +0530)]
board: AM335x-ICEv2: Add cpsw support

In order to enable cpsw on AM335x ICEv2 board, the following needs to be done:

1)There are few on board jumper settings which gives a choice between
cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting
this, there are few GPIOs which control these muxes that needs to be held high.

2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected
via I2C. This needs to properly programmed and locked for PHY operation.
And PHY needs to be reset before before being used, which is also held by
a GPIO.

3) RMII mode needs to be selected.

[1] http://www.ti.com/lit/zip/tidr336
[2] http://www.ti.com/lit/ds/symlink/cdce913.pdf

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: AM33xx: Add support for Clock Synthesizer
Lokesh Vutla [Mon, 16 May 2016 06:17:25 +0000 (11:47 +0530)]
ARM: AM33xx: Add support for Clock Synthesizer

The CDCE913 and CDCEL913 devices are modular PLL-based, low cost,
high performance , programmable clock synthesizers. They generate
upto 3 output clocks from a single input frequency. Each output can
be programmed for any clock-frequency.

Adding support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoboard: AM335x-ICEv2: Add DDR data
Lokesh Vutla [Mon, 16 May 2016 06:17:24 +0000 (11:47 +0530)]
board: AM335x-ICEv2: Add DDR data

AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125),
capable of running at 400MHz. Adding this specific DDR configuration
details running at 400MHz.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoboard: AM335x-ICEv2: Add pinmux support
Lokesh Vutla [Mon, 16 May 2016 06:17:23 +0000 (11:47 +0530)]
board: AM335x-ICEv2: Add pinmux support

Add necessary pinmux support for AM335x ICEv2 board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoboard: AM335x-ICEv2: Add epprom support
Lokesh Vutla [Mon, 16 May 2016 06:17:22 +0000 (11:47 +0530)]
board: AM335x-ICEv2: Add epprom support

Similar to other TI's AM335x platforms, AM335x ICEv2 also has an
eeprom populated for its unique identification. Adding this info
so that AM335x ICEv2 specific initialization can be done.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoconfigs: am335x_evm: Switch to env on FAT SD by default
Tom Rini [Mon, 16 May 2016 06:02:49 +0000 (11:32 +0530)]
configs: am335x_evm: Switch to env on FAT SD by default

Re-org env sections so that we can fall back to env is in FAT on SD
card, for broader board compatibility

Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: dts: AM335x-BBG: Add initial support
Lokesh Vutla [Mon, 16 May 2016 05:54:29 +0000 (11:24 +0530)]
ARM: dts: AM335x-BBG: Add initial support

Add initial DTS support for AM335x-BBG

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: dts: AM335x-evmsk: Add initial support
Lokesh Vutla [Mon, 16 May 2016 05:54:28 +0000 (11:24 +0530)]
ARM: dts: AM335x-evmsk: Add initial support

Add initial DTS support for AM335x-evm sk.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: dts: am335x: fix cd-gpios definition as per hardware design and dt binding docs
Mugunthan V N [Mon, 16 May 2016 05:54:27 +0000 (11:24 +0530)]
ARM: dts: am335x: fix cd-gpios definition as per hardware design and dt binding docs

As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.

In AM335x the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agoARM: AM335x: Enable FIT
Lokesh Vutla [Mon, 16 May 2016 05:54:26 +0000 (11:24 +0530)]
ARM: AM335x: Enable FIT

Use a single defconfig for all AM335x platforms by enabling FIT

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: dts: am335x-bone: Enable uart and timer
Lokesh Vutla [Mon, 16 May 2016 05:54:25 +0000 (11:24 +0530)]
ARM: dts: am335x-bone: Enable uart and timer

Allow am335x-bone.dts to be built and enable uart and timer
for all beaglebones.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoboard: am33xx: fit: add support for selecting dtb dynamically
Lokesh Vutla [Mon, 16 May 2016 05:54:24 +0000 (11:24 +0530)]
board: am33xx: fit: add support for selecting dtb dynamically

FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: AM43xx: configs: Update usb host boot defconfig
Lokesh Vutla [Mon, 16 May 2016 05:41:19 +0000 (11:11 +0530)]
ARM: AM43xx: configs: Update usb host boot defconfig

Convert usb host boot defconfig to use DM, DT. Also enable FIT
support.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: dts: AM437x-IDK Initial Support
Lokesh Vutla [Mon, 16 May 2016 05:41:18 +0000 (11:11 +0530)]
ARM: dts: AM437x-IDK Initial Support

Add initial DTS support for AM437x-IDK evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: dts: AM43x-EPOS Initial Support
Lokesh Vutla [Mon, 16 May 2016 05:41:17 +0000 (11:11 +0530)]
ARM: dts: AM43x-EPOS Initial Support

Add initial DTS support for AM43-EPOS evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: AM43xx: Enable FIT
Lokesh Vutla [Mon, 16 May 2016 05:41:16 +0000 (11:11 +0530)]
ARM: AM43xx: Enable FIT

Use a single defconfig for all AM43xx platforms by enabling FIT and delete
the platform specific defconfigs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoboard: AM43xx: fit: add support for selecting dtb dynamically
Lokesh Vutla [Mon, 16 May 2016 05:41:15 +0000 (11:11 +0530)]
board: AM43xx: fit: add support for selecting dtb dynamically

FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: DRA7: configs: Remove obsolete configs
Lokesh Vutla [Mon, 16 May 2016 05:21:25 +0000 (10:51 +0530)]
ARM: DRA7: configs: Remove obsolete configs

Removing:
uart3_defconfig:
Now uart3 can be selected using menuconfig, removing separate
config for uart mode. Doing uart boot is not straight forward as ROM uses
uart3 as default serial console. In order to boot to prompt, concole in both
u-boot and kernel needs to be changed.

qspiboot_defconfig:
The only advantage of enabling QSPI_BOOT is selecting env in QSPI.
Eventually env needs to be selected by menuconfig so removing
qspiboot_defconfig. qspiboot can be done using dra7xx_evm_defconfig.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: DRA7: Enable FIT
Lokesh Vutla [Mon, 16 May 2016 05:21:24 +0000 (10:51 +0530)]
ARM: DRA7: Enable FIT

Use a single defconfig for all DRA7 platforms by enabling FIT and delete
the platform specific defconfigs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoboard: dra7: fit: add support for selecting dtb dynamically
Lokesh Vutla [Mon, 16 May 2016 05:21:23 +0000 (10:51 +0530)]
board: dra7: fit: add support for selecting dtb dynamically

FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoRemove unused BOOTFLAG definitions
Chris Packham [Fri, 13 May 2016 01:08:56 +0000 (13:08 +1200)]
Remove unused BOOTFLAG definitions

This follows on from commit d98b052 ("powerpc: Cleanup BOOTFLAG_*
references") and commit fc3d297 ("Drop bogus BOOTFLAG_* definitions").
Remove the definitions that have crept in since.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
8 years agospl: Add an option to load a FIT containing U-Boot from UART
Lokesh Vutla [Tue, 24 May 2016 05:04:44 +0000 (10:34 +0530)]
spl: Add an option to load a FIT containing U-Boot from UART

This provides a way to load a FIT containing U-Boot and a selection of device
tree files from UART.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agospl: fit: Do not print selected dtb during fit load
Lokesh Vutla [Tue, 24 May 2016 05:04:43 +0000 (10:34 +0530)]
spl: fit: Do not print selected dtb during fit load

No prints should be allowed during UART load.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agospl: Support loading a FIT from NAND
Lokesh Vutla [Tue, 24 May 2016 05:04:42 +0000 (10:34 +0530)]
spl: Support loading a FIT from NAND

Detect a FIT when loading from NAND and handle it using the
new FIT SPL support.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Make sure we continue to use (void *)(unsigned long) for
load_addr].
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agomtd: nand: am335x: spl: Fix copying of image
Lokesh Vutla [Tue, 24 May 2016 05:04:41 +0000 (10:34 +0530)]
mtd: nand: am335x: spl: Fix copying of image

When offset is not aligned to page address, it is possible that extra offset
will be read from nand. Adjust the image such that first byte of the image
is at load address after the first page is read.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agospl: Support loading a FIT from SPI
Lokesh Vutla [Tue, 24 May 2016 05:04:40 +0000 (10:34 +0530)]
spl: Support loading a FIT from SPI

Detect a FIT when loading from SPI and handle it using the
new FIT SPL support.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agospl: Support loading a FIT from FAT FS
Lokesh Vutla [Tue, 24 May 2016 05:04:39 +0000 (10:34 +0530)]
spl: Support loading a FIT from FAT FS

Detect a FIT when loading from a FAT File system and handle it using the
new FIT SPL support.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agospl: Allow to load a FIT containing U-Boot from FS
Lokesh Vutla [Tue, 24 May 2016 05:04:38 +0000 (10:34 +0530)]
spl: Allow to load a FIT containing U-Boot from FS

This provides a way to load a FIT containing U-Boot and a selection of device
tree files from a File system. Making sure that all the reads and writes
are aligned to their respective needs.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Make this still apply with Michal's alignment change for 'fit']
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agospl: fit: Fix the number of bytes read when reading fdt from fit
Lokesh Vutla [Tue, 24 May 2016 05:04:37 +0000 (10:34 +0530)]
spl: fit: Fix the number of bytes read when reading fdt from fit

sectors field is not being updated when reading fdt from fit image. Because of
this size_of(u-boot.bin) is being read when reading fdt. Fixing it by updating
the sectors field properly.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agodefconfig: ti: Add configs for OMAP5-class secure parts
Daniel Allred [Fri, 20 May 2016 00:10:55 +0000 (19:10 -0500)]
defconfig: ti: Add configs for OMAP5-class secure parts

Adds new defconfig files for DRA7xx and AM57xx secure devices.
These are the same as the non-secure parts, but with the addition
of the CONFIG_TI_SECURE_DEVICE option set to 'y'.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: omap5: add ft_board_setup for dra7xx/am57xx
Daniel Allred [Fri, 20 May 2016 00:10:54 +0000 (19:10 -0500)]
ARM: omap5: add ft_board_setup for dra7xx/am57xx

Adds the board specific ft_board_setup() functions that
are called when CONFIG_OF_BOARD_SETUP is defined. These functions
will currently just call the ft_cpu_setup() function.

Adds CONFIG_OF_BOARD_SETUP to the defconfig files
for dra72_evm, dra74_evm, and am57xx_evm.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: omap5: add hooks for cpu/SoC fdt fixups
Daniel Allred [Fri, 20 May 2016 00:10:53 +0000 (19:10 -0500)]
ARM: omap5: add hooks for cpu/SoC fdt fixups

Adds an fdt.c file in that defines the ft_cpu_setup() function,
which should be called from a board-specific ft_board_setup()).
This ft_cpu_setup() will currently do nothing for non-secure (GP)
devices but contains pertinent updates for booting on secure (HS)
devices.

Update the omap5 Makefile to include the fdt.c in the build.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: omap-common: Add device type to CPU string
Daniel Allred [Fri, 20 May 2016 00:10:52 +0000 (19:10 -0500)]
ARM: omap-common: Add device type to CPU string

Update the CPU string output so that the device
type is now included as part of the CPU string that
is printed as the SPL or u-boot comes up. This update
adds a suffix of the form "-GP" or "-HS" for production
devices, so that general purpose (GP) and high security
(HS) can be distiguished. Applies to all OMAP5 variants.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>