oweals/u-boot.git
8 years agocmd/bdinfo: extract print_eth_ip_addr
Max Filippov [Thu, 28 Jul 2016 00:57:22 +0000 (03:57 +0300)]
cmd/bdinfo: extract print_eth_ip_addr

print_eth_ip_addr outputs eth configurations for up to 6 interfaces and
configured IP address.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agocmd/bdinfo: extract print_bi_flash
Max Filippov [Thu, 28 Jul 2016 00:57:21 +0000 (03:57 +0300)]
cmd/bdinfo: extract print_bi_flash

print_bi_flash outputs flashstart, flashsize and flashoffset lines.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agocmd/bdinfo: extract print_bi_dram
Max Filippov [Thu, 28 Jul 2016 00:57:20 +0000 (03:57 +0300)]
cmd/bdinfo: extract print_bi_dram

print_bi_dram outputs start address and size for each DRAM bank.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agocmd/bdinfo: extract print_bi_mem
Max Filippov [Thu, 28 Jul 2016 00:57:19 +0000 (03:57 +0300)]
cmd/bdinfo: extract print_bi_mem

print_bi_mem outputs memstart and memsize lines.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agocmd/bdinfo: extract print_bi_boot_params
Max Filippov [Thu, 28 Jul 2016 00:57:18 +0000 (03:57 +0300)]
cmd/bdinfo: extract print_bi_boot_params

print_bi_boot_params outputs boot parameters structure location.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agotreewide: move CONFIG_PHYS_64BIT to Kconfig
Masahiro Yamada [Mon, 25 Jul 2016 10:56:03 +0000 (19:56 +0900)]
treewide: move CONFIG_PHYS_64BIT to Kconfig

We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system.  Otherwise we can run
into cases where we have inconsistent sizes of certain attributes.

Ravi Babu reported offset mismatch of struct dwc3 across files since
commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t").
Since the commit, resource_addr_t points to phys_addr_t, whose size
is dependent on CONFIG_PHYS_64BIT for ARM architecture.

I tried my best to use "select" where possible (for example, ARMv8
architecture) because I think this kind of option is generally user-
unconfigurable.  However, I see some of PowerPC boards have 36BIT
defconfigs as well as 32BIT ones.  I moved CONFIG_PHYS_64BIT to the
defconfigs for such boards.

CONFIG_36BIT is no longer referenced, so all of the defines were
removed from CONFIG_SYS_EXTRA_OPTIONS.

Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Ravi Babu <ravibabu@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agotools: moveconfig: support CONFIG_SYS_EXTRA_OPTIONS cleaning
Masahiro Yamada [Mon, 25 Jul 2016 10:15:29 +0000 (19:15 +0900)]
tools: moveconfig: support CONFIG_SYS_EXTRA_OPTIONS cleaning

We mostly move config options from board header files to Kconfig,
but sometimes config defines come from CONFIG_SYS_EXTRA_OPTIONS.

Historically, CONFIG_SYS_EXTRA_OPTIONS originates in boards.cfg,
which was used as a central database of configuration prior to the
Kconfig conversion.

Now, we want to migrate to primary entries in Kconfig rather than
option list in CONFIG_SYS_EXTRA_OPTIONS, so it should be helpful to
have the tool to cleanup CONFIG_SYS_EXTRA_OPTIONS automatically.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agotools: moveconfig: make getting all defconfigs into helper function
Masahiro Yamada [Mon, 25 Jul 2016 10:15:28 +0000 (19:15 +0900)]
tools: moveconfig: make getting all defconfigs into helper function

I want to reuse this routine in the next commit.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agotools: moveconfig: fix cleanup of defines across multiple lines
Masahiro Yamada [Mon, 25 Jul 2016 10:15:27 +0000 (19:15 +0900)]
tools: moveconfig: fix cleanup of defines across multiple lines

Correct the clean-up of such defines that continue across multiple
lines, like follows:

  #define CONFIG_FOO "this continues to the next line " \
          "this line should be removed too" \
          "this line should be removed as well"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agotools: moveconfig: show diffs of cleaned headers in color
Masahiro Yamada [Mon, 25 Jul 2016 10:15:26 +0000 (19:15 +0900)]
tools: moveconfig: show diffs of cleaned headers in color

Show code diff in color if --color option is given.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agotools: moveconfig: show result of header cleaning in unified diff
Masahiro Yamada [Mon, 25 Jul 2016 10:15:25 +0000 (19:15 +0900)]
tools: moveconfig: show result of header cleaning in unified diff

The header cleanup feature of this tool now removes empty ifdef's,
successive blank lines as well as moved option defines.  So, we
want to see a little more context to check which lines were deleted.

It is true that we can see it by "git diff", but it would not work
in the --dry-run mode.  So, here, this commit.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agotools: moveconfig: trim garbage lines after header cleanups
Masahiro Yamada [Mon, 25 Jul 2016 10:15:24 +0000 (19:15 +0900)]
tools: moveconfig: trim garbage lines after header cleanups

The tools/moveconfig.py has a feature to cleanup #define/#undef's
of moved config options, but I want this tool to do a better job.

For example, when we are moving CONFIG_FOO and its define is
surrounded by #ifdef ... #endif, like follows:

  #ifdef CONFIG_BAR
  #  define CONFIG_FOO
  #endif

The header cleanup will leave empty #ifdef ... #endif:

  #ifdef CONFIG_BAR
  #endif

Likewise, if a define line between two blank lines

  <blank line>
  #define CONFIG_FOO
  <blank lines.

... is deleted, the result of the clean-up will be successive empty
lines, which is a coding-style violation.

It is tedious to remove left-over garbage lines manually, so I want
the tool to take care of this.  The tool's job is still not perfect,
so we should check the output of the tool, but I hope our life will
be much easier with this patch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agotools: moveconfig: do not check clean tree and compilers for -H option
Masahiro Yamada [Mon, 25 Jul 2016 10:15:23 +0000 (19:15 +0900)]
tools: moveconfig: do not check clean tree and compilers for -H option

The clean tree (make mrproper) and compilers are required when moving
config options, but not needed when we only cleanup headers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agotools: moveconfig: do not cleanup headers in include/generated
Masahiro Yamada [Mon, 25 Jul 2016 10:15:22 +0000 (19:15 +0900)]
tools: moveconfig: do not cleanup headers in include/generated

The files in include/generated are generated during build and removed
by "make mrproper", so it has no point to touch them by this tool.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoext4: Refuse to mount filesystems with 64bit feature set
Tom Rini [Fri, 22 Jul 2016 21:59:11 +0000 (17:59 -0400)]
ext4: Refuse to mount filesystems with 64bit feature set

With e2fsprogs after 1.43 the 64bit and metadata_csum features are
enabled by default.  The metadata_csum feature changes how
ext4_group_desc->bg_checksum is calculated, which would break write
support.  The 64bit feature however introduces changes such that it
cannot be read by implementations that do not support it.  Since we do
not support this, we must not mount it.

Cc: Stephen Warren <swarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reported-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoARM: Rework and correct barrier definitions
Tom Rini [Mon, 1 Aug 2016 22:54:53 +0000 (18:54 -0400)]
ARM: Rework and correct barrier definitions

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Sandy Patterson <apatterson@sightlogix.com>
Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reported-by: Sandy Patterson <apatterson@sightlogix.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoarc: Rename AXS101 board to more generic AXS10x
Alexey Brodkin [Thu, 4 Aug 2016 12:00:35 +0000 (15:00 +0300)]
arc: Rename AXS101 board to more generic AXS10x

As of now we have 2 flavors of ARC SDP boards:
 1) AXS101 - with ARC770 in ASIC
 2) AXS103 - with ARC HS38 in FPGA

Both options share exactly the same base-board and only differ with
CPU-tiles in use. That means all peripherals are the same (they are
implemented in FPGA on the base-board) and so generic board could be
used for both.

While at it:
 * Recreated defconfigs with savedefconfig
 * In include/configs/axs10x.h numerical sizes replaced with
defines from linux/sizes.h for better readability.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarc: Rename ARCangel4 board to nSIM
Alexey Brodkin [Thu, 4 Aug 2016 11:35:01 +0000 (14:35 +0300)]
arc: Rename ARCangel4 board to nSIM

ARCangel was one of the main development boards back in the day but
now it's gone and replaced by other boards like ARC SDP.

But we also used to have simulation platform very similar to ARCangel4
in terms of CPU settings as well as basic IO like UART. Even though
ARCangel4 is long gone now we have a replacement for simulation which is
a plain or stand-alone nSIM and Free nSIM.

Note Free nSIM is available for download here:
https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi

And while at it:
 * Finally switch hex numerical values in nsim.h to defines from
   include/linux/sizes.h
 * Add defconfigs with ARC HS38 cores
 * Recreated all defconfigs with savedefconfig

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
8 years agoarc: No need in sections defined in sources with newer tools
Alexey Brodkin [Wed, 3 Aug 2016 17:44:39 +0000 (20:44 +0300)]
arc: No need in sections defined in sources with newer tools

Starting from arc-2016.03 GNU tools linker properly works with
symbols defined in linker script and so external declarations
are no longer required, dump them.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
8 years agoarc: Update exception & interrupt handling for ARCv2
Alexey Brodkin [Thu, 4 Aug 2016 06:21:50 +0000 (09:21 +0300)]
arc: Update exception & interrupt handling for ARCv2

Initially IVT for ARCv2 was simply copypasted from ARCompact
with some selected fixes so basic stuff works.

Now we update it with more ARCv2 specific vectors like
 * Software Interrupt
 * Division by zero
 * Data cache consistency error
 * Misaligned access

Also normal interrupts are now implemented properly and extened to
all possible 240 items.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
8 years agoarc: Add debug messages during relocation fixups
Alexey Brodkin [Wed, 3 Aug 2016 17:45:22 +0000 (20:45 +0300)]
arc: Add debug messages during relocation fixups

This might be useful to make sure relocation fixups really
happen. And since this info gets printed only in DEBUG
build it doesn't really hurt normal execution.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
8 years agopowerpc/86xx: Increase boot map size to 256 MiB
Scott Wood [Tue, 19 Jul 2016 22:51:55 +0000 (17:51 -0500)]
powerpc/86xx: Increase boot map size to 256 MiB

This is what Linux maps on classic PPC during boot, and modern kernel
images don't fit within the current 8 MiB uncompressed limit.

Adjust image load addresses to be above this limit to avoid conflicts.

Signed-off-by: Scott Wood <oss@buserror.net>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Wed, 3 Aug 2016 00:45:24 +0000 (20:45 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

8 years agoARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP
Hou Zhiqiang [Fri, 29 Jul 2016 11:26:34 +0000 (19:26 +0800)]
ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP

The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT node
Hou Zhiqiang [Fri, 29 Jul 2016 10:26:37 +0000 (18:26 +0800)]
arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT node

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarm/PSCI: Fixed the backward compatiblity issue
Hou Zhiqiang [Fri, 29 Jul 2016 10:26:36 +0000 (18:26 +0800)]
arm/PSCI: Fixed the backward compatiblity issue

Appended the compatible strings of old version PSCI to the latest
version supported. And there are some psci functions' property must
be added to DT only for psci version 0.1, including cpu_on, cpu_off,
cpu_suspend, migrate.

Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarm/PSCI: Removed unused code
Hou Zhiqiang [Fri, 29 Jul 2016 10:26:35 +0000 (18:26 +0800)]
arm/PSCI: Removed unused code

Identify the PSCI node only by its name, so removed the code finding
it by compatible string.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver/ddr/fsl: Fix timing_cfg_2
York Sun [Fri, 29 Jul 2016 16:02:29 +0000 (09:02 -0700)]
driver/ddr/fsl: Fix timing_cfg_2

Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
8 years agoboard/freescale: Update MAINTAINERS files
York Sun [Fri, 29 Jul 2016 15:46:49 +0000 (08:46 -0700)]
board/freescale: Update MAINTAINERS files

Update maintainers for secure boot targets.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls1043a: enable pxe commands
Wenbin Song [Fri, 15 Jul 2016 09:17:46 +0000 (17:17 +0800)]
armv8: ls1043a: enable pxe commands

Enable pxe command for ls1043ardb and ls1043aqds.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls1012a: Update Refresh cycle for DDR
Prabhakar Kushwaha [Tue, 19 Jul 2016 10:24:33 +0000 (15:54 +0530)]
armv8: ls1012a: Update Refresh cycle for DDR

Refresh cycle value must be selected based on the frequency
of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
value should be 0x0f3c8000.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls1012a: Enable DDR row-bank-column decoding
Prabhakar Kushwaha [Tue, 19 Jul 2016 10:24:22 +0000 (15:54 +0530)]
armv8: ls1012a: Enable DDR row-bank-column decoding

Enable DDR row-bank-column decoding to decode DDR address as
row-bank-column instead of bank-row-column for improving
performance of serial data transfers.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET
Prabhakar Kushwaha [Tue, 19 Jul 2016 08:35:47 +0000 (14:05 +0530)]
board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET

qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define
inverse value QIXIS_LBMAP_MASK.

Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
as 0b11 i.e. PORESET during qixis_reset

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agocrypto/fsl: Update blob cmd to accept 64bit addresses
Sumit Garg [Thu, 14 Jul 2016 17:27:50 +0000 (13:27 -0400)]
crypto/fsl: Update blob cmd to accept 64bit addresses

Update blob cmd to accept 64bit source, key modifier and destination
addresses. Also correct output result print format for fsl specific
implementation of blob cmd.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: spi: fsl-qspi: remove compile Warnings
Yunhui Cui [Wed, 13 Jul 2016 02:46:27 +0000 (10:46 +0800)]
driver: spi: fsl-qspi: remove compile Warnings

Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);

Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agopowerpc/mpc85xx: Update erratum workaround for A006379
York Sun [Mon, 1 Aug 2016 16:00:13 +0000 (09:00 -0700)]
powerpc/mpc85xx: Update erratum workaround for A006379

Update erratum workaround for A006379 to set register CPCHDBCR0
with value 0x001e0000, replacing the old value 0x003c0000.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Dave Liu <dave.liu@nxp.com>
8 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Tue, 2 Aug 2016 11:32:30 +0000 (07:32 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-microblaze

8 years agoMAINTAINERS, git-mailrc: Update the mmc maintainer
Jaehoon Chung [Mon, 1 Aug 2016 03:35:20 +0000 (12:35 +0900)]
MAINTAINERS, git-mailrc: Update the mmc maintainer

Update the mmc maintainer from Pantelis to me.

Acked-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
8 years agoARM64: zynqmp: Do not enable DM_MMC by default
Michal Simek [Mon, 1 Aug 2016 06:49:12 +0000 (08:49 +0200)]
ARM64: zynqmp: Do not enable DM_MMC by default

The patch:
"dm: mmc: zynq: Convert zynq to use driver model for MMC"
(sha1: 329a449f2c289b4de8f892fca1d9379ce5fd81b8)
added dependency on enabling some MMC options by default.
There are minimal ZynqMP configurations which require
only minimal configurations to be enabled to keep u-boot size
as lower as possible.

Move options to defconfig instead.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Fix stack pointer initialization
Soren Brinkmann [Wed, 27 Jul 2016 21:12:03 +0000 (14:12 -0700)]
ARM64: zynqmp: Fix stack pointer initialization

This partly reverts commit:
"ARM64: zynqmp: Add SPL support support"
(sha1: e6a9ed04e78cf87ec97e306fa4e7a1669ef98df6)

Stack can rewrite ATF code.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Define config USB_STORAGE through defconfig
Michal Simek [Wed, 27 Jul 2016 12:56:49 +0000 (14:56 +0200)]
ARM64: zynqmp: Define config USB_STORAGE through defconfig

Define config USB_STORAGE through defconfig for all
Xilinx ZynqMP boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoxilinx: Sync defconfigs with the latest Kconfig layout
Michal Simek [Wed, 27 Jul 2016 13:08:03 +0000 (15:08 +0200)]
xilinx: Sync defconfigs with the latest Kconfig layout

Update Microblaze, Zynq and ZynqMP defconfigs to reflect
latest Kconfig changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Wire up PSCI reset
Michal Simek [Wed, 27 Jul 2016 11:40:19 +0000 (13:40 +0200)]
ARM64: zynqmp: Wire up PSCI reset

Using PSCI to reset the system.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodes
Michal Simek [Fri, 29 Jul 2016 11:03:29 +0000 (13:03 +0200)]
ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodes

Serial driver is getting clk information via DT that's why
also clk node needs to have this flag.

Different behavior was introduced by:
"dm: Use dm_scan_fdt_dev() directly where possible"
(sha1: 911954859d6dece49c3e4835faea004cfe392506)
where simple-bus driver starts to call dm_scan_fdt_dev() which has
additional logic around pre_reloc_only parameter which exclude
clk nodes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoDrop references to MAKEALL in the documentation
Simon Glass [Thu, 28 Jul 2016 02:33:08 +0000 (20:33 -0600)]
Drop references to MAKEALL in the documentation

It is confusing to mention MAKEALL when it is not the normal way of building
U-Boot anymore. Update the documentation to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoDrop the MAKEALL tool
Simon Glass [Thu, 28 Jul 2016 02:33:07 +0000 (20:33 -0600)]
Drop the MAKEALL tool

Buildman has been around for 3 years now. It has had a lot of use and
testing. Perhaps it is time to remove MAKEALL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agobuildman: Add a quick-start note
Simon Glass [Thu, 28 Jul 2016 02:33:06 +0000 (20:33 -0600)]
buildman: Add a quick-start note

For those who just want to build a board, it is useful to see a quick hint
right at the start of the documentation. Add a few commands showing how to
download toolchains and build a board.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agobuildman: Avoid overwriting existing toolchain entries
Simon Glass [Thu, 28 Jul 2016 02:33:05 +0000 (20:33 -0600)]
buildman: Avoid overwriting existing toolchain entries

The current code for setting up the toolchain config always writes the new
paths to an item called 'toolchain'. This means that it will overwrite any
existing toolchain item with the same name. In practice, this means that:

   buildman --fetch-arch all

will fetch all toolchains, but only the path of the final one will be added
to the config. This normally works out OK, since most toolchains are the
same version (e.g. gcc 4.9) and will be found on the same path. But it is
not correct and toolchains for archs which don't use the same version will
not function as expected.

Adjust the code to use a complete glob of the toolchain path.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agobuildman: Drop the toolchain error when downloading toolchains
Simon Glass [Thu, 28 Jul 2016 02:33:04 +0000 (20:33 -0600)]
buildman: Drop the toolchain error when downloading toolchains

It doesn't make sense to complain about missing toolchains when the
--fetch-arch option is being used. The user is presumably aware that there
is a toolchain problem and is actively correcting it by running with this
option.

Refactor the code to avoid printing this confusing message.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agobuildman: Fix a typo in TestSettingsHasPath()
Simon Glass [Thu, 28 Jul 2016 02:33:03 +0000 (20:33 -0600)]
buildman: Fix a typo in TestSettingsHasPath()

The function comment should say 'buildman'. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agobuildman: Improve the toolchain progress/error output
Simon Glass [Thu, 28 Jul 2016 02:33:02 +0000 (20:33 -0600)]
buildman: Improve the toolchain progress/error output

Use colour to make it easier to see what is going on. Also print a message
before downloading a new toolchain. Mention --fetch-arch in the message that
is shown when there are no available toolchains, since this is the quickest
way to resolve the problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agobuildman: Allow the toolchain error to be suppressed
Simon Glass [Thu, 28 Jul 2016 02:33:01 +0000 (20:33 -0600)]
buildman: Allow the toolchain error to be suppressed

When there are no toolchains a warning is printed. But in some cases this is
confusing, such as when the user is fetching new toolchains.

Adjust the function to supress the warning in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agobuildman: Fix the 'help' test to use the correct path
Simon Glass [Thu, 28 Jul 2016 02:33:00 +0000 (20:33 -0600)]
buildman: Fix the 'help' test to use the correct path

When buildman is run via a symlink, this test fails. Fix it to work the same
way as buildman itself.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agobuildman: Automatically create a config file if needed
Simon Glass [Thu, 28 Jul 2016 02:32:59 +0000 (20:32 -0600)]
buildman: Automatically create a config file if needed

If there is no ~/.buildman file, buildman currently complains and exists. To
make things a little more friendly, create an empty one automatically. This
will not allow things to be built, but --fetch-arch can be used to handle
that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agobuildman: Tidy up the README a little
Simon Glass [Thu, 28 Jul 2016 02:32:58 +0000 (20:32 -0600)]
buildman: Tidy up the README a little

Tidy up some problems found by a recent review.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agolibfdt: Introduce new ARCH_FIXUP_FDT option
Michal Simek [Thu, 28 Jul 2016 07:06:41 +0000 (09:06 +0200)]
libfdt: Introduce new ARCH_FIXUP_FDT option

Add new Kconfig option to disable arch_fixup_fdt() calls for cases where
U-Boot shouldn't update memory setup in DTB file.
One example of usage of this option is to boot OS with different memory
setup than U-Boot use.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agoMerge git://git.denx.de/u-boot-rockchip
Tom Rini [Mon, 1 Aug 2016 00:31:13 +0000 (20:31 -0400)]
Merge git://git.denx.de/u-boot-rockchip

8 years agosunxi: Re-enable h3 emac support
Hans de Goede [Wed, 27 Jul 2016 16:06:35 +0000 (18:06 +0200)]
sunxi: Re-enable h3 emac support

With the recent bug fixes for the sun8i_emac driver all known issues
are resolved, so we can re-enable the driver.

While at it, also enable the emac on the Orange Pi One.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Jagan Teki <jteki@openedev.com>
8 years agonet: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers
Hans de Goede [Wed, 27 Jul 2016 15:31:17 +0000 (17:31 +0200)]
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers

This fixes the following CACHE warnings when using sun8i_emac:

=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a87bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c907bf59e10]
CACHE: Misaligned operation at range [7bf5a4787bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)

Note this commit also changes the max rx size from 2024 to 2044,
matching what the kernel driver uses.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: On newer SoCs use words 1-3 instead of just word 3 from the SID
Hans de Goede [Fri, 29 Jul 2016 09:47:03 +0000 (11:47 +0200)]
sunxi: On newer SoCs use words 1-3 instead of just word 3 from the SID

It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, and the other non constant words (1 and 2) also
have quite a few bits which are the same for some boards,

This commits switches to using the crc32 of words 1 - 3 to get a
more unique value for the mac-address / serialnr.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: Ensure that the NIC specific bytes of the mac are not all 0
Hans de Goede [Wed, 27 Jul 2016 15:58:06 +0000 (17:58 +0200)]
sunxi: Ensure that the NIC specific bytes of the mac are not all 0

On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
the NIC specific bytes of the mac all being 0, which leads to the
boards not getting an ipv6 address from the dhcp server.

This commits adds a check to ensure this does not happen.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: Hummingbird_A31_defconfig: Drop MACPWR option
Chen-Yu Tsai [Fri, 22 Jul 2016 08:13:00 +0000 (16:13 +0800)]
sunxi: Hummingbird_A31_defconfig: Drop MACPWR option

MACPWR was used to bring the Ethernet PHY out of reset. The designware
driver now supports the phy reset gpio binding, so this is no longer
needed. In fact in requesting the same GPIO, it makes the designware
driver fail to probe.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: gpio: Add .xlate function for gpio phandle resolution
Chen-Yu Tsai [Fri, 22 Jul 2016 08:12:59 +0000 (16:12 +0800)]
sunxi: gpio: Add .xlate function for gpio phandle resolution

sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.

Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.

Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver
      model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agorockchip: add support for rk3288 PopMetal board
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:30 +0000 (18:28 +0800)]
rockchip: add support for rk3288 PopMetal board

PopMetal is a rockchip rk3288 based board made by ChipSpark, which has
many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and
Gigabit Ethernet.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: add basic support for fennec-rk3288 board
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:29 +0000 (18:28 +0800)]
rockchip: add basic support for fennec-rk3288 board

Fennec is a RK3288-based development board with 2 USB ports, HDMI,
micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes
on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access
to display pins, I2C, SPI, UART and GPIOs.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3288: move evb board to rockchip folder
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:27 +0000 (18:28 +0800)]
rockchip: rk3288: move evb board to rockchip folder

The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is
the real vendor name.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3288: revise CONFIG_FASTBOOT_BUF_ADDR
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:26 +0000 (18:28 +0800)]
rockchip: rk3288: revise CONFIG_FASTBOOT_BUF_ADDR

CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for
fastboot.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: remove the duplicated macro config
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:25 +0000 (18:28 +0800)]
rockchip: remove the duplicated macro config

CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in
config_distro_defaults.h, and we don't need them in SPL stage.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3288: disable fastboot in SPL stage
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:24 +0000 (18:28 +0800)]
rockchip: rk3288: disable fastboot in SPL stage

Reduce compilation time for SPL.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agoRevert "rockchip: Move the MMC setup check earlier"
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:23 +0000 (18:28 +0800)]
Revert "rockchip: Move the MMC setup check earlier"

Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to
setup sdmmc gpio, otherwise we will hit an error below:

=>mmc info
blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1
   - -1 0
   - found
uclass_find_device_by_seq: 0 1
   - -1 -1
   - -1 0
   - not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
Buswidth = 1, clock: 0
Buswidth = 1, clock: 400000
Sending CMD0
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy

This reverts commit 6efeeea79c880d3dd262e0dca9da2687f0ab68c9.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agocosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:22 +0000 (18:28 +0800)]
cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming

Revise config to CONFIG_ROCKCHIP_RK3288_PINCTRL.

Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
8 years agorockchip: add a dummy byte for the sdram-channel property
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:21 +0000 (18:28 +0800)]
rockchip: add a dummy byte for the sdram-channel property

Add an extra byte so that this data is not byteswapped.

Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
8 years agorockchip: rk3288: Fix pinctrl for GPIO bank 0
John Keeping [Mon, 25 Jul 2016 09:02:05 +0000 (10:02 +0100)]
rockchip: rk3288: Fix pinctrl for GPIO bank 0

Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers.  In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.

Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed.  The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
8 years agork3399: Reserve space for ARM Trust Firmware
Kever Yang [Mon, 25 Jul 2016 03:45:54 +0000 (11:45 +0800)]
rk3399: Reserve space for ARM Trust Firmware

RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3036: update MAINTAINER file
Xu Ziyuan [Sat, 23 Jul 2016 07:09:28 +0000 (15:09 +0800)]
rockchip: rk3036: update MAINTAINER file

Update MAINTAINER files for kylin_rk3036, evb_rk3036.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agoconfigs: rockchip: remove no use MACRO
Kever Yang [Fri, 22 Jul 2016 09:41:37 +0000 (17:41 +0800)]
configs: rockchip: remove no use MACRO

The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now,
remove them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agommc-uclass: correct the device number
Kever Yang [Fri, 22 Jul 2016 09:22:50 +0000 (17:22 +0800)]
mmc-uclass: correct the device number

Not like the mmc-legacy which the devnum starts from 1, it starts from 0
in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
8 years agom68k: code reformatting for all start.S files
Angelo Dureghello [Sat, 21 May 2016 22:14:29 +0000 (00:14 +0200)]
m68k: code reformatting for all start.S files

This patch is style-related only, to reformat all the start.S code,
actually not following a coherent style inside single files and
between different cpu start.S files.

Linux format has been respected, as
  - max line width at 80 columns
  - one 8 cols tab between asm instructions and operands
  - inline comments, where any, fixed at col 41

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
8 years agoARM: am57xx_evm: Enable QSPI support
Vignesh R [Fri, 29 Jul 2016 08:52:30 +0000 (14:22 +0530)]
ARM: am57xx_evm: Enable QSPI support

AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: am57xx-idk-common: Enable support for QSPI
Vignesh R [Fri, 29 Jul 2016 08:52:31 +0000 (14:22 +0530)]
ARM: dts: am57xx-idk-common: Enable support for QSPI

AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoconfigs: am43xx_evm_defconfig: Enable CONFIG_SPI_FLASH_BAR
Vignesh R [Thu, 28 Jul 2016 11:57:57 +0000 (17:27 +0530)]
configs: am43xx_evm_defconfig: Enable CONFIG_SPI_FLASH_BAR

AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM: dts: dra7xx: Update spi-max-frequency for QSPI
Vignesh R [Mon, 25 Jul 2016 10:15:47 +0000 (15:45 +0530)]
ARM: dts: dra7xx: Update spi-max-frequency for QSPI

According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agoconfigs: dra7xx: Update QSPI speed to 76.8MHz
Vignesh R [Mon, 25 Jul 2016 10:15:46 +0000 (15:45 +0530)]
configs: dra7xx: Update QSPI speed to 76.8MHz

Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agospi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
Vignesh R [Mon, 25 Jul 2016 10:15:45 +0000 (15:45 +0530)]
spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agoARM: dra7xx: Change DPLL_PER_HS13 divider value
Lokesh Vutla [Mon, 25 Jul 2016 10:15:44 +0000 (15:45 +0530)]
ARM: dra7xx: Change DPLL_PER_HS13 divider value

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agosf: sf_params: Add AT25DF321 flash support
Wenyou Yang [Tue, 5 Jul 2016 05:17:12 +0000 (13:17 +0800)]
sf: sf_params: Add AT25DF321 flash support

Add AT25DF321 flash support.
Fix AT25DF321A device name.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agospi: ti_qspi: Remove delay in read path for dra7xx
Vignesh R [Fri, 22 Jul 2016 05:25:50 +0000 (10:55 +0530)]
spi: ti_qspi: Remove delay in read path for dra7xx

As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agospi: ti_qspi: Fix compiler warning when DEBUG macro is set
Vignesh R [Fri, 22 Jul 2016 05:25:49 +0000 (10:55 +0530)]
spi: ti_qspi: Fix compiler warning when DEBUG macro is set

clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agospi: ti_qspi: Fix failure on multiple READ_ID cmd
Vignesh R [Fri, 22 Jul 2016 05:25:48 +0000 (10:55 +0530)]
spi: ti_qspi: Fix failure on multiple READ_ID cmd

Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
8 years agospi: Add support for N25Q016A
Moritz Fischer [Thu, 14 Jul 2016 23:22:39 +0000 (16:22 -0700)]
spi: Add support for N25Q016A

This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-imx
Tom Rini [Thu, 28 Jul 2016 12:45:00 +0000 (08:45 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx

8 years agoMAINTAINERS: i.MX: Add board/freescale/*mx* path
Fabio Estevam [Wed, 27 Jul 2016 00:27:49 +0000 (21:27 -0300)]
MAINTAINERS: i.MX: Add board/freescale/*mx* path

Pass the board/freescale/*mx*/ path as files maintained by Stefano
Babic.

While this is not ideal and does not cover all the i.MX board cases,
it gives at least a better hint for the /scripts/get_maintainer.pl
tool.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agomx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfig
Fabio Estevam [Wed, 27 Jul 2016 00:08:58 +0000 (21:08 -0300)]
mx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfig

Add an entry for the mx7dsabresd_secure_defconfig target.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agomx7_common: initialize generic timer on all CPU's
Stefan Agner [Tue, 26 Jul 2016 05:57:47 +0000 (22:57 -0700)]
mx7_common: initialize generic timer on all CPU's

Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize
the generic timer on all CPU's. This allows to make use of the timer
freuquency register also on other CPU than the start CPU which is
important for KVM.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
8 years agomx6ul_14x14_evk: Remove unused define
Diego Dorta [Mon, 25 Jul 2016 16:45:30 +0000 (13:45 -0300)]
mx6ul_14x14_evk: Remove unused define

Remove unused define constant.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agocgtqmx6eval: Remove uneeded PHYS_SDRAM_SIZE
Fabio Estevam [Sat, 23 Jul 2016 16:23:42 +0000 (13:23 -0300)]
cgtqmx6eval: Remove uneeded PHYS_SDRAM_SIZE

cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.

Remove the unneeded definition.

Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
8 years agonovena: Remove uneeded PHYS_SDRAM_SIZE
Fabio Estevam [Sat, 23 Jul 2016 16:23:41 +0000 (13:23 -0300)]
novena: Remove uneeded PHYS_SDRAM_SIZE

novena uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.

Remove the unneeded definition.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>
8 years agobx50v3: Use imx_ddr_size() for calculating the DDR size
Fabio Estevam [Sat, 23 Jul 2016 16:23:40 +0000 (13:23 -0300)]
bx50v3: Use imx_ddr_size() for calculating the DDR size

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Cc: Martin Donnelly <martin.donnelly@ge.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agoaristainetos: Use imx_ddr_size() for calculating the DDR size
Fabio Estevam [Sat, 23 Jul 2016 16:23:39 +0000 (13:23 -0300)]
aristainetos: Use imx_ddr_size() for calculating the DDR size

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Heiko Schocher <hs@denx.de>
8 years agowarp: Use imx_ddr_size() for calculating the DDR size
Fabio Estevam [Sat, 23 Jul 2016 16:23:38 +0000 (13:23 -0300)]
warp: Use imx_ddr_size() for calculating the DDR size

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>