oweals/u-boot.git
7 years agorockchip: pwm: implement pwm_set_invert()
Kever Yang [Mon, 24 Apr 2017 02:27:50 +0000 (10:27 +0800)]
rockchip: pwm: implement pwm_set_invert()

Rockchip pwm need to init polarity, implement pwm_set_invert()
to do it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agopower: regulator: pwm: support pwm polarity setting
Kever Yang [Mon, 24 Apr 2017 02:27:49 +0000 (10:27 +0800)]
power: regulator: pwm: support pwm polarity setting

The latest kernel PWM drivers enable the polarity settings. When system
run from U-Boot to kerenl, if there are differences in polarity set or
duty cycle, the PMW will re-init:
  close -> set polarity and duty cycle -> enable the PWM.
The power supply controled by pwm regulator may have voltage shaking,
which lead to the system not stable.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: add rk3399-firefly dts
Kever Yang [Wed, 19 Apr 2017 10:17:32 +0000 (18:17 +0800)]
rockchip: dts: add rk3399-firefly dts

Firefly-rk3399 is a bord from T-Firefly, you can find detail about
it here:
http://en.t-firefly.com/en/firenow/Firefly_RK3399/

This patch add basic node for the board and make it able to bring
up.

Peripheral/interfaces on board:
- usb hub which connect to ehci controller;
- UART2 debug
- eMMC
- PCIe
- USB 3.0 HOST, type-C port
- sdio, sd-card
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: rk3399: sync with kernel dts
Kever Yang [Wed, 19 Apr 2017 10:17:31 +0000 (18:17 +0800)]
rockchip: dts: rk3399: sync with kernel dts

The kernel dts has update a lot since the first time we commit rk3399.dtsi,
sync with kernel for further development.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agodtoc: Handle nodes with phandles that depend on the same
Simon Glass [Sun, 23 Apr 2017 00:42:22 +0000 (18:42 -0600)]
dtoc: Handle nodes with phandles that depend on the same

At present dtoc assumes that nodes which are phandles do not themselves
reference other phandle nodes. Unfortunately this is not necessarilly
true. As a result we can currently output C code which does not compile
because a node declaration can be referenced before it is declared.

Adjust the code to explicitly output all phandle nodes needed by node
before the node itself is output.

This fixes building with the latest rk3399-firefly.dts from Linux, which
has reordered the nodes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agodtoc: Move the output code into its own function
Simon Glass [Sun, 23 Apr 2017 00:42:21 +0000 (18:42 -0600)]
dtoc: Move the output code into its own function

The code to generate the tables is quite long. Move the node-output code
into its own function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: mmc: handle deprecation of 'clock-freq-min-max'
Philipp Tomsich [Tue, 25 Apr 2017 07:52:07 +0000 (09:52 +0200)]
rockchip: mmc: handle deprecation of 'clock-freq-min-max'

The 'clock-freq-min-max' property was deprecated in the upstream
(i.e. Linux) DTS bindings in favor of the 'max-frequency' property.

With the latest RK3399 DTSI does no longer include the deprecated
property and the rockchip_dw_mmc driver requiring it to be present,
the driver doesn't bind to the node in the RK3399 DTSI any longer
(thus breaking access to the SD card on the RK3399-Q7 board).

To fix this, we implement a similar logic as in the Linux driver: if
the deprecated property is present, we issue a warning (if DEBUG is
enabled); if it is missing, we require 'max-frequency' to be set and
use it to create a min/max value-pair.

See https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b
for the deprecation/matching change in Linux.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTS
Philipp Tomsich [Tue, 25 Apr 2017 07:52:06 +0000 (09:52 +0200)]
rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTS

The clocking of the designware MMC controller in the upstream
(i.e. Linux) RK3399 has changed/does not match what the current DTS in
U-Boot uses: the first clock entry now is HCLK_SDMMC instead of
SCLK_SDMMC.

With the simple clock driver used for the RK3399, this needs a change
in the selector understood by the various case statements in the driver
to ensure that the driver still loads successfully.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: reserve memory for rk3399 ATF data
Kever Yang [Thu, 20 Apr 2017 09:03:46 +0000 (17:03 +0800)]
rockchip: reserve memory for rk3399 ATF data

There are 3 regions used by rk3399 ATF:
- bl31 code, located at 0x10000;
- cortex-m0 code and data, located at 0xff8c0000;
- bl31 data, located at 0xff8c1000 ~ 0xff8c4000;

SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
for ATF data, or else there will be memory corrupt after SPL
loads the ATF image.

More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3399: add gmac io strength support
Kever Yang [Thu, 20 Apr 2017 08:15:34 +0000 (16:15 +0800)]
rockchip: pinctrl: rk3399: add gmac io strength support

GMAC controller need to init the tx io driver strength to 13mA,
just like the description in dts pinctrl node, or else the controller
may only work in 100MHz Mode, and fail to work at 1000MHz mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: evb-rk3399: add gmac support
Kever Yang [Mon, 1 May 2017 22:16:01 +0000 (16:16 -0600)]
rockchip: dts: evb-rk3399: add gmac support

Enable gmac for evb-rk3399.

Change-Id: I85e35667e08e22e38577e63eb0e65731fc9c69b6
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
7 years agorockchip: rk3399: use actual dram size
Kever Yang [Wed, 19 Apr 2017 08:01:14 +0000 (16:01 +0800)]
rockchip: rk3399: use actual dram size

Since our sdram driver is ready, we can use the actual size
instead of hard code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: enable debug uart
Eddie Cai [Tue, 18 Apr 2017 11:17:27 +0000 (19:17 +0800)]
rockchip: enable debug uart

enable debug uart for rk3288 and print something to let people know
where we are

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: evb-rk3399: correct pwm3 polarity
Kever Yang [Tue, 18 Apr 2017 09:06:21 +0000 (17:06 +0800)]
rockchip: dts: evb-rk3399: correct pwm3 polarity

The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
the polarity to make it work correctly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma
Philipp Tomsich [Mon, 17 Apr 2017 15:50:38 +0000 (17:50 +0200)]
rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma

With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
to use these by default.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop blank line at end of file:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi
Philipp Tomsich [Mon, 17 Apr 2017 15:50:37 +0000 (17:50 +0200)]
rockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi

The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended
left-over comments in them. This change cleans the file up.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: remove placeholder functions from rkimage
Philipp Tomsich [Mon, 17 Apr 2017 15:48:06 +0000 (17:48 +0200)]
rockchip: mkimage: remove placeholder functions from rkimage

The imagetool framework checks whether function pointer for the verify,
print and extract actions are available and will will handle their
absence appropriately.

This change removes the unnecessary functions and uses the driver
structure to convey available functionality to imagetool.  This is in
fact better than having verify just return 0 (which previously broke
dumpimage, as dumpimage assumed that we had handled the image and did
not continue to probe further).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: play nice with dumpimage
Philipp Tomsich [Mon, 17 Apr 2017 15:48:05 +0000 (17:48 +0200)]
rockchip: mkimage: play nice with dumpimage

Dumpimage (it invoked with "-T rkspi" or "-T rksd") would not work due
to check_params failing. These changes ensure that we can both be called
with an empty imagename.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: clarify header0 initialisation
Philipp Tomsich [Mon, 17 Apr 2017 15:48:04 +0000 (17:48 +0200)]
rockchip: mkimage: clarify header0 initialisation

This change set adds documentation to the header0 initialisation and
improves readability for the calculations of various offsets/lengths.

As the U-Boot SPL stage doesn't use any payload beyond what is covered
by init_size, we no longer add RK_MAX_BOOT_SIZE to init_boot_size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: rksd: pad SD/MMC images to a full blocksize
Philipp Tomsich [Mon, 17 Apr 2017 15:48:03 +0000 (17:48 +0200)]
rockchip: mkimage: rksd: pad SD/MMC images to a full blocksize

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: Update comments for header size
Philipp Tomsich [Mon, 17 Apr 2017 15:48:02 +0000 (17:48 +0200)]
rockchip: mkimage: Update comments for header size

The calculation of the variable header size in rkcommon_vrec_header
had been update twice in the earlier series (introducing boot0-style
images to deal with the alignment of the first instruction in 64bit
binaries). Unfortunately, I didn't update the comment twice (so it
remained out-of-date).

This change brings the comment back in-sync with what the code is
doing.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images
Philipp Tomsich [Mon, 17 Apr 2017 15:48:01 +0000 (17:48 +0200)]
rockchip: mkimage: rewrite padding calculation for SD/MMC and SPI images

In (first) breaking and (then) fixing the rkspi tool, I realised that
the calculation of the required padding (for the header-size and the
2K-in-every-4K SPI layout) was not as self-explainatory as it could
have been.  This change rewrites the code (using new, common functions
in rkcommon.c) and adds verbose in-line comments to ensure that we
won't fall into the same pit in the future...

Tested on the RK3399 (with has a boot0-style payload) with SD/MMC and SPI.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: mkimage: rkspi: include the header sector in the SPI size calculation
Philipp Tomsich [Mon, 17 Apr 2017 15:48:00 +0000 (17:48 +0200)]
rockchip: mkimage: rkspi: include the header sector in the SPI size calculation

Our earlier change broke the generation of SPI images, by excluding the
2K used for header0 from the size-calculation.

This commit makes sure that these are included before calculating the
required total size (including the padding from the 2K-from-every-4K
conversion).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL
Philipp Tomsich [Thu, 20 Apr 2017 20:05:55 +0000 (22:05 +0200)]
rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL

To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spi: enable support for the rk_spi driver for the RK3399
Jakob Unterwurzacher [Thu, 20 Apr 2017 20:05:54 +0000 (22:05 +0200)]
rockchip: spi: enable support for the rk_spi driver for the RK3399

The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399.  This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.

This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3399: add support for the SPI5 controller
Philipp Tomsich [Thu, 20 Apr 2017 20:05:53 +0000 (22:05 +0200)]
rockchip: pinctrl: rk3399: add support for the SPI5 controller

This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
 * grf_rk3399.h: adds definition for configuring the SPI5 pins
     in the GPIO2C group
 * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
         PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
     through SPI5 to the appropriate pin-config
     function; implements the pin-configuration
     for PERIPH_ID_SPI5 using the GPIO2C group

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting
Philipp Tomsich [Thu, 20 Apr 2017 20:05:52 +0000 (22:05 +0200)]
rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting

The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator.  This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
   bitwise-AND generates rather random-looking (wildly varying)
   actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
   higher baudrate' with the actual error increasing as the dividers
   become very small. E.g., with a 99MHz input clock, a request
   for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
   (which amounts to a 23.75% error)... for a 34 MBit request this
   would be an actual outbout of 49.5 Mbit (i.e. a 45% error).

This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
   requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
   represented), the lowest representable baudrate is chosen.

Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
7 years agorockchip: spi: rk_spi: dynamically select an module input rate
Philipp Tomsich [Thu, 20 Apr 2017 20:05:51 +0000 (22:05 +0200)]
rockchip: spi: rk_spi: dynamically select an module input rate

The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.

To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.

This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.

This replaces
  "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
  "rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
Philipp Tomsich [Thu, 20 Apr 2017 20:05:50 +0000 (22:05 +0200)]
rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate

For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
  1. calculates 'src_div := src_freq / target_freq'
  2. stores 'src_div - 1' into the register (the actual divider applied
     in hardware is biased by adding 1)
  3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
     expects the (decremented) divider from the hardware-register and
     implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')

This can be observed with the SPI driver, which sets a rate of 99MHz
based on the GPLL frequency of 594MHz: the hardware generates a clock
of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
but reports a frequency of 84MHz (594 / 7) on return.

To fix, we have two options:
 * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
   make for a particularily nice read
 * we simply call the i2c/spi_get_rate function (introducing additional
   overhead for the additional register-read), which reads the divider
   from the register and then passes it through the DIV_RATE macro

Given that this code is not time-critical, the more readable solution
(i.e. calling the appropriate get_rate function) is implemented in this
change.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
Philipp Tomsich [Thu, 20 Apr 2017 20:05:49 +0000 (22:05 +0200)]
rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5

This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.

Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: Makefile: Modify Makefile for rockchip video driver
eric.gao@rock-chips.com [Mon, 17 Apr 2017 14:24:24 +0000 (22:24 +0800)]
rockchip: video: Makefile: Modify Makefile for rockchip video driver

Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: video: Kconfig: Add Kconfig for rockchip video driver
eric.gao@rock-chips.com [Mon, 17 Apr 2017 14:24:23 +0000 (22:24 +0800)]
rockchip: video: Kconfig: Add Kconfig for rockchip video driver

1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop indenting in Kconfig:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3399: correct memory region
Kever Yang [Mon, 17 Apr 2017 08:42:44 +0000 (16:42 +0800)]
rockchip: rk3399: correct memory region

RK3399 device memory region is 0xf8000000~0xffffffff.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
Xu Ziyuan [Sun, 16 Apr 2017 09:44:46 +0000 (17:44 +0800)]
rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO
Xu Ziyuan [Sun, 16 Apr 2017 09:44:45 +0000 (17:44 +0800)]
rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
Xu Ziyuan [Sun, 16 Apr 2017 09:44:44 +0000 (17:44 +0800)]
rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO
Xu Ziyuan [Sun, 16 Apr 2017 09:44:43 +0000 (17:44 +0800)]
rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO

The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agommc: dw_mmc: rockchip: select proper card clock
Xu Ziyuan [Sun, 16 Apr 2017 09:44:42 +0000 (17:44 +0800)]
mmc: dw_mmc: rockchip: select proper card clock

As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
used for communication between host and card devices. The real bus clock
is ciu, so let's rectify it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agomkimage: rockchip: add support for rk3328
Kever Yang [Fri, 14 Apr 2017 06:55:05 +0000 (14:55 +0800)]
mkimage: rockchip: add support for rk3328

Add support for rk3328 package header in mkimage tool.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3399: use regulators_enable_boot_on() to init regulator
Kever Yang [Wed, 12 Apr 2017 04:00:06 +0000 (12:00 +0800)]
rockchip: rk3399: use regulators_enable_boot_on() to init regulator

Use regulators_enable_boot_on() instead of init regulators one by one,
the interface can init all the regulators with regulator-boot-on property.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agopower: twl4030: Remove CONFIG_TWL4030_POWER from include/configs
Adam Ford [Wed, 26 Apr 2017 18:41:32 +0000 (13:41 -0500)]
power: twl4030: Remove CONFIG_TWL4030_POWER from include/configs

With the addition of Kconfig now having CONFIG_TWL4030_POWER and
with that being the default when OMAP34XX is selected, this
is no longer needed in include/configs and can be removed from the
whitelist.

This has only been tested on logic PD DM3730 using ti_omap3_common.h

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agopower: twl4030: Move CONFIG_TWL4030_POWER to Kconfig
Adam Ford [Wed, 26 Apr 2017 18:41:31 +0000 (13:41 -0500)]
power: twl4030: Move CONFIG_TWL4030_POWER to Kconfig

As requested, I added the CONFIG_TWL4030_POWER to Kconfig and made it
the implied default when selecting OMAP34XX as a platform.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agopower: twl4030: Add CONFIG_CMD_POWEROFF support
Adam Ford [Mon, 24 Apr 2017 18:34:43 +0000 (13:34 -0500)]
power: twl4030: Add CONFIG_CMD_POWEROFF support

With the addition of twl4030_power_off(), let's allow the 'poweroff' command
to run this function when CONFIG_CMD_POWEROFF is enabled.

Tested on a DM3730 with twl4030 PMIC.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
7 years agoomap3_logic: Add Device Tree Support and more DM drivers
Adam Ford [Mon, 17 Apr 2017 13:09:45 +0000 (08:09 -0500)]
omap3_logic: Add Device Tree Support and more DM drivers

This patch also removes all the excessive code for NS16550 intiailization
as the device tree can do that now.  This also adds DM_I2C and DM_MMC
since the overlying drivers have the built-in support already.  The
corresponding include/config/omap3_logic.h also reduced in size
due to the new device tree support.

Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
  Retain Auto-detect ability between SOM-LV and Torpedo
  Split this off from the device sub submissions

7 years agoARM: DTS: Add Logic PD DM3730 Torpedo Device Tree
Adam Ford [Mon, 17 Apr 2017 13:09:44 +0000 (08:09 -0500)]
ARM: DTS: Add Logic PD DM3730 Torpedo Device Tree

Previous commit has this combined with SOM-LV.  This commit has only
the Torpedo Device Tree.

The device trees were sync'd with 4.9.y stable with two changes:
disable mmc2 and stdout-path = &uart1.  Both of those two changes
will be submitted to the linux-omap list

Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
  Split device tree from other board

7 years agoARM: DTS: Add Logic PD DM3730 SOM-LV initial support
Adam Ford [Mon, 17 Apr 2017 13:09:43 +0000 (08:09 -0500)]
ARM: DTS: Add Logic PD DM3730 SOM-LV initial support

This adds the device tree.  Previous commit added both boards at the
same time.

Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
  Split the SOM-LV from Torpedo

7 years agoOMAP3: Add SMSC9221 device tree for omap devices connected on GPMC.
Adam Ford [Mon, 17 Apr 2017 13:09:42 +0000 (08:09 -0500)]
OMAP3: Add SMSC9221 device tree for omap devices connected on GPMC.

Some OMAP3 devices support an SMSC ethernet PHY connected to the GPMC bus.
This copies this device tree from Linux 4.9.y stable

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoomap3: Copy twl4030 device tree from Linux 4.9.y stable
Adam Ford [Mon, 17 Apr 2017 13:09:41 +0000 (08:09 -0500)]
omap3: Copy twl4030 device tree from Linux 4.9.y stable

Many OMAP3 boards use a TWL4030 PMIC.  This brings in the related
device tree information for common TWL4030 and TWL4030 with OMAP3.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP: I2C: Support New read, write and probe functions for OMAP3
Adam Ford [Mon, 17 Apr 2017 13:09:40 +0000 (08:09 -0500)]
ARM: OMAP: I2C: Support New read, write and probe functions for OMAP3

New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359) were added in 960187ffa125(
"ARM: OMAP: I2C: New read, write and probe functions") but not tested
on OMAP3.  This patch will allow the updated drivers using device tree and
DM_I2C to operate on OMAP3.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoomap3630: Copy Device tree from Linux 4.9.y stable
Adam Ford [Mon, 17 Apr 2017 13:09:39 +0000 (08:09 -0500)]
omap3630: Copy Device tree from Linux 4.9.y stable

Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards.
DM3730 can use this same device tree.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoomap3: Copy Device tree from Linux 4.9.y stable
Adam Ford [Mon, 17 Apr 2017 13:09:38 +0000 (08:09 -0500)]
omap3: Copy Device tree from Linux 4.9.y stable

Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3 boards.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoomap_hsmmc: update struct hsmmc to accommodate omap3 from DT
Adam Ford [Mon, 17 Apr 2017 13:09:37 +0000 (08:09 -0500)]
omap_hsmmc: update struct hsmmc to accommodate omap3 from DT

This patch changes the way DM_MMC calculates offset to the base register of
MMC. Previously this was through an #ifdef but that wasn't necessary for OMAP3.

This patch will now add in the offset to the base address based on the
.compatible flags.

Signed-off-by: Adam Ford <aford173@gmail.com>
V2: Remove ifdef completely and reference offset from the omap_hsmmc_ids table.

V1: Change ifdef to ignore OMAP3
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoAllow boards to initialize the DT at runtime.
Alex Deymo [Sun, 2 Apr 2017 08:25:20 +0000 (01:25 -0700)]
Allow boards to initialize the DT at runtime.

In some boards like the Raspberry Pi the initial bootloader will pass
a DT to the kernel. When using U-Boot as such kernel, the board code in
U-Boot should be able to provide U-Boot with this, already assembled
device tree blob.

This patch introduces a new config option CONFIG_OF_BOARD to use instead
of CONFIG_OF_EMBED or CONFIG_OF_SEPARATE which will initialize the DT
from a board-specific funtion instead of bundling one with U-Boot or as
a separated file. This allows boards like the Raspberry Pi to reuse the
device tree passed from the bootcode.bin and start.elf firmware
files, including the run-time selected device tree overlays.

Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agobcm2835_wdt: support for the BCM2835/2836 watchdog
Paolo Pisati [Fri, 10 Feb 2017 16:28:05 +0000 (17:28 +0100)]
bcm2835_wdt: support for the BCM2835/2836 watchdog

Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
7 years agoarm: rpi: Add a TODO to move all messages into the msg handler
Simon Glass [Wed, 5 Apr 2017 22:23:45 +0000 (16:23 -0600)]
arm: rpi: Add a TODO to move all messages into the msg handler

The board code should all move into msg.c for consistency. Add a TODO for
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodm: video: arm: rpi: Convert to use driver model for video
Simon Glass [Wed, 5 Apr 2017 22:23:44 +0000 (16:23 -0600)]
dm: video: arm: rpi: Convert to use driver model for video

Adjust the video driver to work with driver model and move over existing
baords. There is no need to keep the old code.

We can also drop setting of CONFIG_FB_ADDR since driver model doesn't have
this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
7 years agodm: video: Add driver-model support to lcd_simplefb
Simon Glass [Wed, 5 Apr 2017 22:23:43 +0000 (16:23 -0600)]
dm: video: Add driver-model support to lcd_simplefb

Allow this to work with CONFIG_DM_VIDEO enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
7 years agodm: video: Refactor lcd_simplefb to prepare for driver model
Simon Glass [Wed, 5 Apr 2017 22:23:42 +0000 (16:23 -0600)]
dm: video: Refactor lcd_simplefb to prepare for driver model

Adjust this function so that we can convert it to support CONFIG_DM_VIDEO
without a lot of code duplication.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
7 years agovideo: arm: rpi: Move the video settings out of the driver
Simon Glass [Wed, 5 Apr 2017 22:23:41 +0000 (16:23 -0600)]
video: arm: rpi: Move the video settings out of the driver

Add a function to set the video parameters to the msg handler and remove
it from the video driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
7 years agovideo: arm: rpi: Move the video query out of the driver
Simon Glass [Wed, 5 Apr 2017 22:23:40 +0000 (16:23 -0600)]
video: arm: rpi: Move the video query out of the driver

Add a function to get the video size to the msg handler and remove it from
the video driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
7 years agodm: arm: rpi: Drop CONFIG_OF_EMBED
Simon Glass [Wed, 5 Apr 2017 22:23:39 +0000 (16:23 -0600)]
dm: arm: rpi: Drop CONFIG_OF_EMBED

We should not use an embedded device tree on a production board. There
does not seem to be any reason for it in commit 7670909. So drop this.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodm: mmc: rpi: Convert Raspberry Pi to driver model for MMC
Simon Glass [Wed, 5 Apr 2017 22:23:38 +0000 (16:23 -0600)]
dm: mmc: rpi: Convert Raspberry Pi to driver model for MMC

Convert the bcm2835 SDHCI driver over to support CONFIG_DM_MMC and move
all boards over. There is no need to keep the old code since there are no
other users.

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoarm: rpi: Add a function to obtain the MMC clock
Simon Glass [Wed, 5 Apr 2017 22:23:37 +0000 (16:23 -0600)]
arm: rpi: Add a function to obtain the MMC clock

Move this code into the new message handler file.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoarm: rpi: Add a file to handle messages
Simon Glass [Wed, 5 Apr 2017 22:23:36 +0000 (16:23 -0600)]
arm: rpi: Add a file to handle messages

The bcm283x chips provide a way for the ARM core to communicate with the
graphics processor, which is in charge of many things. This is handled by
way of a message prototcol.

At present the code for sending message (and receiving a reply) is spread
around U-Boot, primarily in the board file. This means that sending a
message from a driver requires duplicating the code.

Create a new message implementation with a function to support powering on
a subsystem as a starting point.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodm: arm: rpi: Use driver model for Ethernet
Simon Glass [Wed, 5 Apr 2017 22:23:35 +0000 (16:23 -0600)]
dm: arm: rpi: Use driver model for Ethernet

Enable CONFIG_DM_ETH so that driver model is used for the USB Ethernet
device.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodm: arm: rpi: Move to driver model for USB
Simon Glass [Wed, 5 Apr 2017 22:23:34 +0000 (16:23 -0600)]
dm: arm: rpi: Move to driver model for USB

Start using driver model for USB on the Raspberry Pi. The dwc2 supports
this now so this is just a config change.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoarm: rpi: Drop CONFIG_CONS_INDEX
Simon Glass [Wed, 5 Apr 2017 22:23:33 +0000 (16:23 -0600)]
arm: rpi: Drop CONFIG_CONS_INDEX

This is not needed now that serial uses driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoarm: rpi: Drop the GPIO device addresses
Simon Glass [Wed, 5 Apr 2017 22:23:32 +0000 (16:23 -0600)]
arm: rpi: Drop the GPIO device addresses

We can rely on the device tree to provide this information.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agostring: Use memcpy() within memmove() when we can
Simon Glass [Wed, 5 Apr 2017 22:23:31 +0000 (16:23 -0600)]
string: Use memcpy() within memmove() when we can

A common use of memmove() can be handled by memcpy(). Also memcpy()
includes an optimisation for large sizes: it copies a word at a time. So
we can get a speed-up by calling memcpy() to handle our move in this case.

Update memmove() to call memcpy() if the destination is before the source.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agonet: smsc95xx: Correct free_pkt() implementation
Simon Glass [Wed, 5 Apr 2017 22:23:28 +0000 (16:23 -0600)]
net: smsc95xx: Correct free_pkt() implementation

On further review this returns the wrong packet length from the driver.
It may not be noticed since protocols will take care of it. Fix it by
subtracting the header length from the packet length returned.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Tue, 9 May 2017 20:11:36 +0000 (16:11 -0400)]
Merge git://git.denx.de/u-boot-dm

7 years agoMerge git://www.denx.de/git/u-boot-marvell
Tom Rini [Tue, 9 May 2017 19:48:09 +0000 (15:48 -0400)]
Merge git://www.denx.de/git/u-boot-marvell

7 years agodefconfig: dra7xx_evm: enable CONFIG_BLK and disk driver model for SCSI
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:32 +0000 (11:51 +0200)]
defconfig: dra7xx_evm: enable CONFIG_BLK and disk driver model for SCSI

Enable disk driver model for dra7xx_evm as dwc_ahci supports
driver model. As a consequence we must also enable CONFIG_BLK and
CONFIG_DM_USB.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dropped CONFIG_SPL_PHY=y in sandbox_spl to fix build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agodrivers: block: dwc_ahci: Implement a driver for Synopsys DWC sata device
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:31 +0000 (11:51 +0200)]
drivers: block: dwc_ahci: Implement a driver for Synopsys DWC sata device

Implement a sata driver for Synopsys DWC sata device based on
U-boot driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodra7: dtsi: mark ocp2scp bus compatible with "simple-bus"
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:30 +0000 (11:51 +0200)]
dra7: dtsi: mark ocp2scp bus compatible with "simple-bus"

This is needed to probe devices under that bus such as the SATA PHY.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodrivers: phy: add PIPE3 phy driver
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:29 +0000 (11:51 +0200)]
drivers: phy: add PIPE3 phy driver

This phy is found on omap platforms with sata capabilities.
Except for the part related to the DM and the PHY framework, the code is
basically a copy paste from arch/arm/mach-omap2/pipe3-phy.c

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: test: Add tests for the generic PHY uclass
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:28 +0000 (11:51 +0200)]
dm: test: Add tests for the generic PHY uclass

Those tests check:
- the ability for a phy-user to get a phy based on its name or its index
- the ability of a phy device (provider) to manage multiple ports
- the ability to perform operations on the phy (init,deinit,on,off)
- the behavior of the uclass when optional operations are not implemented

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodrivers: phy: add generic PHY framework
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:27 +0000 (11:51 +0200)]
drivers: phy: add generic PHY framework

The PHY framework provides a set of APIs to control a PHY. This API is
derived from the linux version of the generic PHY framework.
Currently the API supports init(), deinit(), power_on, power_off() and
reset(). The framework provides a way to get a reference to a phy from the
device-tree.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoscsi: dm: split scsi_scan()
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:26 +0000 (11:51 +0200)]
scsi: dm: split scsi_scan()

The DM version of scsi_scan() is becoming a bit long, it can be split:
scsi_scan() iterates over the IDs and LUNs and for each id/lun pair calls
do_scsi_scan_one() to do the work of:
 - detecting an attached drive
 - creating the associated block device if a drive is found.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9263ek: Enable early debug UART
Wenyou Yang [Tue, 18 Apr 2017 07:31:02 +0000 (15:31 +0800)]
board: at91sam9263ek: Enable early debug UART

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9263ek: Clean up code
Wenyou Yang [Tue, 18 Apr 2017 07:31:01 +0000 (15:31 +0800)]
board: at91sam9263ek: Clean up code

Because the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: at91sam9263ek: Update for DT and DM support
Wenyou Yang [Tue, 18 Apr 2017 07:31:00 +0000 (15:31 +0800)]
configs: at91sam9263ek: Update for DT and DM support

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9rlek: Enable early debug UART
Wenyou Yang [Tue, 18 Apr 2017 07:28:29 +0000 (15:28 +0800)]
board: at91sam9rlek: Enable early debug UART

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9rlek: Clean up code
Wenyou Yang [Tue, 18 Apr 2017 07:28:28 +0000 (15:28 +0800)]
board: at91sam9rlek: Clean up code

Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: at91sam9rlek: Update for DT and DM support
Wenyou Yang [Tue, 18 Apr 2017 07:28:27 +0000 (15:28 +0800)]
configs: at91sam9rlek: Update for DT and DM support

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9260ek/9g20ek: Enable early debug UART
Wenyou Yang [Tue, 18 Apr 2017 07:18:49 +0000 (15:18 +0800)]
board: at91sam9260ek/9g20ek: Enable early debug UART

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9260ek: Clean up code
Wenyou Yang [Tue, 18 Apr 2017 07:18:48 +0000 (15:18 +0800)]
board: at91sam9260ek: Clean up code

Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: at91sam9260ek/9g20ek: Update for DT and DM
Wenyou Yang [Tue, 18 Apr 2017 07:18:47 +0000 (15:18 +0800)]
configs: at91sam9260ek/9g20ek: Update for DT and DM

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9m10g45ek: Enable early debug UART
Wenyou Yang [Tue, 18 Apr 2017 07:15:50 +0000 (15:15 +0800)]
board: at91sam9m10g45ek: Enable early debug UART

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9m10g45ek: Clean up code
Wenyou Yang [Tue, 18 Apr 2017 07:15:49 +0000 (15:15 +0800)]
board: at91sam9m10g45ek: Clean up code

Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: at91sam9m10g45ek: Update to support DM/DT
Wenyou Yang [Tue, 18 Apr 2017 07:15:48 +0000 (15:15 +0800)]
configs: at91sam9m10g45ek: Update to support DM/DT

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9n12ek: Enable early debug UART
Wenyou Yang [Tue, 18 Apr 2017 06:54:53 +0000 (14:54 +0800)]
board: at91sam9n12ek: Enable early debug UART

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9n12ek: Clean up code
Wenyou Yang [Tue, 18 Apr 2017 06:54:52 +0000 (14:54 +0800)]
board: at91sam9n12ek: Clean up code

Since the introduction of the pinctrl and clk driver and the device
tree files, remove unneeded related code from the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: at91sam9n12ek: Update for DT and DM support
Wenyou Yang [Tue, 18 Apr 2017 06:54:51 +0000 (14:54 +0800)]
configs: at91sam9n12ek: Update for DT and DM support

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9x5ek: Enable early debug UART
Wenyou Yang [Tue, 18 Apr 2017 06:51:56 +0000 (14:51 +0800)]
board: at91sam9x5ek: Enable early debug UART

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: at91sam9x5ek: Clean up code
Wenyou Yang [Tue, 18 Apr 2017 06:51:55 +0000 (14:51 +0800)]
board: at91sam9x5ek: Clean up code

Since the introduction of the pinctrl and clock driver and the device
tree files, remove unneeded hard coded related code from the board
file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: at91sam9x5ek: Update to support DM/DT
Wenyou Yang [Tue, 18 Apr 2017 06:51:54 +0000 (14:51 +0800)]
configs: at91sam9x5ek: Update to support DM/DT

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: dts: at91: Add dts files for at91sam9263ek
Wenyou Yang [Tue, 18 Apr 2017 05:49:39 +0000 (13:49 +0800)]
ARM: dts: at91: Add dts files for at91sam9263ek

The device tree source files of at91sam9263ek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: dts: at91: Add dts files for at91sam9rlek
Wenyou Yang [Tue, 18 Apr 2017 05:49:38 +0000 (13:49 +0800)]
ARM: dts: at91: Add dts files for at91sam9rlek

The device tree source files of at91sam9rlek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: dts: at91: Add dts files for at91sam9260ek/9g20ek
Wenyou Yang [Tue, 18 Apr 2017 05:49:37 +0000 (13:49 +0800)]
ARM: dts: at91: Add dts files for at91sam9260ek/9g20ek

The device tree source files of at91sam9g20ek and at91sam9260ek
boards are copied from the Linux v4.10, do the changes below.
 - Fix the build error for the usb0 node.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Add the clk pinctrl of the mmc0 node.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>