Bin Meng [Wed, 17 Feb 2016 08:16:24 +0000 (00:16 -0800)]
x86: ivybridge: bd82x6x: Support FSP enabled configuration
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:23 +0000 (00:16 -0800)]
x86: fsp: Make sure HOB list is not overwritten by U-Boot
Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.
To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:22 +0000 (00:16 -0800)]
superio: Add SMSC SIO1007 driver
The SMSC SIO1007 superio chipset integrates two ns16550 compatible
serial ports for legacy applications, 16 GPIO pins and some other
functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:21 +0000 (00:16 -0800)]
x86: ivybridge: Add FSP support
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Fri, 12 Feb 2016 21:27:56 +0000 (14:27 -0700)]
x86: fix memalign() parameter order
Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)
Fixes:
45b5a37836d5 ("x86: Add multi-processor init")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Sat, 20 Feb 2016 22:32:48 +0000 (17:32 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel
Andreas Bießmann [Sat, 20 Feb 2016 20:39:36 +0000 (21:39 +0100)]
vinco: add Maintainers file
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Alexey Brodkin [Mon, 14 Dec 2015 14:15:13 +0000 (17:15 +0300)]
arc: cache - utilize IO coherency (AKA IOC) engine
With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.
With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Alexey Brodkin [Mon, 14 Dec 2015 14:14:46 +0000 (17:14 +0300)]
arc: cache - accommodate different L1 cache line lengths
ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.
Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.
With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Guillaume GARDET [Thu, 18 Feb 2016 17:17:36 +0000 (18:17 +0100)]
spl: if MMCSD_MODE_RAW fails, try MMCSD_MODE_FS
Since commit
fd61d39970b9901217efc7536d9f3a61b4e1752a:
spl: mmc: add break statements in spl_mmc_load_image()
RAW and FS boot modes are now exclusive again. So, if MMCSD_MODE_RAW fails, the
board hangs. This patch allows to try MMCSD_MODE_FS then.
It has been tested on a beaglebone black to boot on an EXT partition.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@konsulko.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Tom Rini [Fri, 19 Feb 2016 14:25:09 +0000 (09:25 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Gregory CLEMENT [Wed, 16 Dec 2015 16:01:44 +0000 (17:01 +0100)]
ARM: Add Support for the VInCo platform
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[rebase on current TOT]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Samuel Mescoff [Tue, 16 Feb 2016 08:45:06 +0000 (09:45 +0100)]
ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit
b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Thu, 11 Feb 2016 13:13:38 +0000 (14:13 +0100)]
arm: at91: Add support for DENX MA5D4 SoM and EVK
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the
Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI
CAN controllers and DRAM, the baseboard contains UART connectors,
ethernet port, microSD slot, LCD header, 2x CAN connector and a
lot of expansion headers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Matthias Michel [Wed, 27 Jan 2016 14:56:07 +0000 (15:56 +0100)]
siemens,at91: enable features for smartweb
New features for smartweb:
* switch to hush command parser
* change autoboot stop to <ESC><ESC>
* allow to write ethaddr
Signed-off-by: Matthias Michel <matthias.michel@siemens.com>
Reviewed-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 04:46:14 +0000 (12:46 +0800)]
board: atmel: clean up the PMC_PLLICPR init code
Due to introducing the PMC_PLLICPR init function, use this
function to clean up the code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 04:46:13 +0000 (12:46 +0800)]
ARM: at91: clean up the PMC_PLLICPR init code
Due to introducing the PMC_PLLICPR init function, use this
function to clean up the code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 04:46:12 +0000 (12:46 +0800)]
ARM: at91: clock: add PMC_PLLICPR init function
To avoid the duplicated code, add the PMC_PLLICPR init function.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:20:45 +0000 (10:20 +0800)]
board: atmel: siemens: clean up PLLB code
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
Wenyou Yang [Wed, 3 Feb 2016 02:20:44 +0000 (10:20 +0800)]
drivers: usb: ohci-at91: clean up the PLLB code
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable/disable code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
Wenyou Yang [Wed, 3 Feb 2016 02:20:43 +0000 (10:20 +0800)]
ARM: at91: clock: add PLLB enable/disable functions
To avoid the duplicated code, add the PLLB handle functions.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
[add enable/disable functions to arm920t]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:54 +0000 (11:11 +0800)]
board: atmel: siemens: clean up UTMI PLL code
Due to introducing the new UTMI PLL clock handle functions,
use the functions to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:53 +0000 (11:11 +0800)]
drivers: usb: atmel: clean up the UTMI PLL code
Due to introducing the new UTMI PLL clock handle functions,
use these function to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:52 +0000 (11:11 +0800)]
ARM: at91: armv7: clean up UTMI PLL handle code
Due to introducing the UTMI PLL enable function, use this function
to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:51 +0000 (11:11 +0800)]
ARM: at91: clock: add UTMI PLL enable/disable function
To avoid the duplicated code, add the UTMI PLL handle functions,
and add PMC_USB init function too.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:51 +0000 (10:16 +0800)]
drivers: at91: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
[fixup for missing clk.h in at91_emac.c]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:50 +0000 (10:16 +0800)]
board: atmel: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to reduce duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
[Rebased on current master, fixup for at91rm9200ek]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:49 +0000 (10:16 +0800)]
ARM: cpu: at91: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to clean up the duplicated code.
Meanwhile, remove unneeded header file include, at91_pmc.h.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fixup for arm920t code]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:48 +0000 (10:16 +0800)]
ARM: at91: clock: add a new file to handle clock
To reduce the duplicated code, add a new file to accommodate
the peripheral's and system's clock handle code, shared with
the SoCs with different ARM core.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:47 +0000 (10:16 +0800)]
ARM: at91: asm/at91_pmc.h: fix trival register offset
Remove unnecessary #ifdef CPU_HAS_PCR.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Stefan Roese [Wed, 10 Feb 2016 06:06:06 +0000 (07:06 +0100)]
net: phy: marvell: Fix problem with phy_reset() clearing BMCR
With commit
a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.
At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.
Tested on clearfog.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Roese [Wed, 10 Feb 2016 06:06:05 +0000 (07:06 +0100)]
net: phy: marvell: Call phy_reset() where possible
Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Mon, 15 Feb 2016 17:34:04 +0000 (10:34 -0700)]
ARM: tegra: enable USB device mode port on Dalmore
This allows U-Boot to expose UMS and DFU protocols on this port in device
mode, or to act as a USB host on the port, using an "OTG" (micro-B to
female A host) cable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 15 Feb 2016 17:34:03 +0000 (10:34 -0700)]
ARM: tegra: don't set CONFIG_USB_MAX_CONTROLLER_COUNT
This option is no longer used now that DM_USB is enabled.
Fixes:
534f9d3feffd ("dm: tegra: usb: Move USB to driver model")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Wed, 17 Feb 2016 01:09:19 +0000 (18:09 -0700)]
video: tegra: Correct a Kconfig warning with VIDCONSOLE_AS_LCD
This new feature causes a Kconfig warning on boards without a display
enabled. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:38:02 +0000 (16:38 -0700)]
tegra: video: Clean up the old LCD/PWM driver code
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we
are using driver model for video.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:38:01 +0000 (16:38 -0700)]
tegra: video: Move LCD driver to use the DM PWM driver
Use the driver-model PWM driver in preference to the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:38:00 +0000 (16:38 -0700)]
tegra: Convert CONFIG_PWM_TEGRA to Kconfig
Move this option to Kconfig and clean up the header files. Adjust the only
user (the LCD driver) to work with the new driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:59 +0000 (16:37 -0700)]
tegra: video: Move all fdt-decoding into a single function
Join the two functions which decode the device tree and put them in the
ofdata_to_platdata() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:58 +0000 (16:37 -0700)]
tegra: video: Move LCD enums into the driver
There is no need to have these in a separate file as they are not
referenced from anywhere else.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:57 +0000 (16:37 -0700)]
tegra: video: Remove the static variables
We can move the static variables into the driver-private data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:56 +0000 (16:37 -0700)]
tegra: video: Convert tegra20 LCD driver to driver model
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.
Boards which use this are fixed up, but only seaboard is tested.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:55 +0000 (16:37 -0700)]
tegra: video: Merge the two config structures together
We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:54 +0000 (16:37 -0700)]
tegra: video: Move the check for CONFIG_OF_CONTROL to Kconfig
We can check this in Kconfig now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:53 +0000 (16:37 -0700)]
tegra: video: Merge the display driver into one file
At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.
Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:52 +0000 (16:37 -0700)]
tegra: dts: Sync tegra20.dtsi with Linux v4.4
This file has changed quite a bit since it was set up. Sync it back with
Linux v4.4. Adjust the users slightly to cope with the changes:
- the host1x node is now called host1x@
50000000
- we need a clocks node to provide the clk32k_in phandle
- active usb nodes need status = "okay"
- active i2c nodes need status = "okay"
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:51 +0000 (16:37 -0700)]
tegra: video: Rename CONFIG_VIDEO_TEGRA to CONFIG_VIDEO_TEGRA20
This option refers only to the tegra20 video driver, so name it as such
to avoid confusion with tegra124.
Also move this option to Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:50 +0000 (16:37 -0700)]
tegra: nyan-big: Move the LCD driver to driver model
Adjust the driver to use driver model. The SOR becomes a bridge device. We
use the normal simple_panel driver to handle the display itself. We also
need to enable some options such as regulators, PWMs and DM_VIDEO itself.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:49 +0000 (16:37 -0700)]
tegra: Allow CONFIG_DM_VIDEO to be used as well as CONFIG_LCD
While we transition to using driver model for video, we need to support both
options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:48 +0000 (16:37 -0700)]
tegra: Allow driver model to be used for the PWM
We can skip this manual init when using driver model for the PWM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:47 +0000 (16:37 -0700)]
tegra: lcd: Merge tegra124-lcd.c into display.c
There isn't a lot of benefit of have two separate files. With driver model
the code needs to be in the same driver, so it's better to have it in the
same file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:46 +0000 (16:37 -0700)]
tegra: pwm: Add a driver for the tegra PWM
This PWM supports four channels. The driver always uses the 32KHz clock,
and adjusts the duty cycle accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:45 +0000 (16:37 -0700)]
tegra: gpio: Show the GPIO value for outputs
The tegra GPIO controller has two ways of reading the value of a GPIO. It
can supply the 'input' value (which is the value read from the pin) and the
'output' value (which is the value being driven from the pin. With a GPIO
set to output mode, the 'input' value is always low which is not very
useful.
This has the unfortunate result that setting a GPIO high still leaves it
showing as low in the 'gpio status' command.
Adjust the driver to check which direction the GPIO is set to, then read
the value from the appropriate register: 'input' for input GPIOs, 'output'
for output GPIOs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:44 +0000 (16:37 -0700)]
tegra: dts: Sync up nyan-big files with Linux
Sync up these files with Linux v4.4. Some differences remain, principally
that the addresses are still 32-bit in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:43 +0000 (16:37 -0700)]
tegra: dts: Sync up the tegra124 device tree files with Linux
Sync up these files with Linux v4.4.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:42 +0000 (16:37 -0700)]
tegra: mmc: Fix comments in the MMC driver init
Fix the SoC names in two comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:41 +0000 (16:37 -0700)]
dm: video: Flush the cache after a puts()
This helps keep the display consistent. puts() is used when printing the
prompt, so is a useful way to make sure the current display contents is
visible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:40 +0000 (16:37 -0700)]
tegra: keyboard: Fix the init order
We need to add the base tables before adding the function tables. Fix the
init order so the keyboard scans keys correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Rini [Mon, 15 Feb 2016 21:44:30 +0000 (21:44 +0000)]
Prepare v2016.03-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Thu, 11 Feb 2016 18:46:12 +0000 (11:46 -0700)]
test/py: put "Starting U-Boot" into separate log section
The initial boot of U-Boot happens within the context of the first test
that needs to access the U-Boot console when there is no existing
connection. This keeps all activity nestled within test execution, which
fits well into the pytest model. However, this mingles the U-Boot startup
logs with the execution of some test(s), which hides find the boundary
between the two.
To solve this, wrap the "Starting U-Boot" logic into a separate log
section. If the user wishes, they can simply collapse this log section
when viewing the HTML log, to concentrate purely on the test's own
interaction.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Wed, 10 Feb 2016 23:54:37 +0000 (16:54 -0700)]
test/py: handle exceptions in console creation
u_boot_console.exec_attach.get_spawn() performs two steps:
1) Spawn a process to communicate with the serial console.
2) Reset the board so that U-Boot starts running from scratch.
Currently, if an exception happens in step (2), no cleanup is performed on
the process created in step (1). That process stays running and may e.g.
hold serial port locks, or simply continue to read data from the serial
port, thus preventing it from reaching any other process that attempts to
read from the same serial port later. While there is error cleanup code in
u_boot_console_base.ensure_spawned(), this is not triggered since the
exception prevents assignment to self.p there, and hence the exception
handler has no object to operate upon in cleanup_spawn().
Solve this by enhancing u_boot_console.exec_attach.get_spawn() to clean
up any objects it has created.
In theory, u_boot_spawn.Spawn's constructor has a similar issue, so fix
this too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Wed, 10 Feb 2016 20:47:37 +0000 (13:47 -0700)]
test/py: print summary in test order
Use lists rather than sets to record the status of tests. This causes
the test summary in the HTML file to be generated in the same order as
the tests are (or would have been) run. This makes it easier to locate
the first failed test. The log for this test might have interesting
first clues re: interaction with the environment (e.g. hardware flashing,
serial console, ...) and may help tracking down external issues.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Wed, 10 Feb 2016 19:39:30 +0000 (12:39 -0700)]
test/py: fix CONFIG_SPL test
The Python ini file parser that's used to parse .config converts all keys
to lower-case. Hence, all queries against the results must use lower-case.
Fix u_boot_console.ensure_spawned() to test CONFIG_SPL correctly, or the
connection will fail for boards that have SPL.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Tue, 9 Feb 2016 01:23:35 +0000 (18:23 -0700)]
Enable test/py for sandbox in Travis CI
This provides runtime test coverage in Travis, in addition to the existing
build coverage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Roger Meier <r.meier@siemens.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Tue, 9 Feb 2016 01:23:34 +0000 (18:23 -0700)]
test/py: don't import pexpect
The code replaced pexpect with custom code long ago. Don't import the
unused module so it doesn't need to be installed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Mon, 8 Feb 2016 21:49:02 +0000 (14:49 -0700)]
test/py: add docs for gdbserver and pytest options
Add documentation describing the new --gdbserver feature, and some common
pytest options.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Mon, 8 Feb 2016 21:44:16 +0000 (14:44 -0700)]
test/py: run all "ut" subtests
Invoke each "ut"-based unit test as a separate pytest.
Now that the DM unit test runs under test/py, remove the manual shell
script that invokes it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # v2, on sandbox
Stephen Warren [Mon, 8 Feb 2016 21:44:15 +0000 (14:44 -0700)]
Makefile: generate symbol list from u-boot
This information may be useful for both debugging, and processes that want
to perform simple forms of introspection on the U-Boot binary, such as
determining the set of "ut" subtests that are compiled in.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 14 Feb 2016 23:28:59 +0000 (16:28 -0700)]
gpio: Correct handling of 'gpio status'
This is broken - we need to look at the first two characters to distinguish
'gpio status' from 'gpio set'.
Fixes:
0ffe6ab5 (gpio: Allow 's' as an abbreviation for 'status')
Reported-by: Soeren Moch <smoch@web.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Soeren Moch <smoch@web.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Lubomir Rintel [Sun, 14 Feb 2016 19:13:24 +0000 (20:13 +0100)]
tools: fix env_flags build
$ make tools-all
...
In file included from tools/env/env_flags.c:1:0:
tools/env/../../common/env_flags.c: In function
‘env_flags_parse_varaccess_from_binflags’:
tools/env/../../common/env_flags.c:156:18: warning: implicit declaration
of function ‘ARRAY_SIZE’ [-Wimplicit-function-declaration]
for (i = 0; i < ARRAY_SIZE(env_flags_varaccess_mask); i++)
^
Seems like the other utilities just add a copy of ARRAY_SIZE since
there's nowhere to include it from (tools/imagetool.h,
tools/mxsimage.h). Let's do the same here.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Lubomir Rintel [Sun, 14 Feb 2016 18:23:24 +0000 (19:23 +0100)]
ARM: rpi: set initrd_high
The kernel gets much too sad when the ramdisk is loaded too high into the 1GiB
of memory on Raspberry Pi 2:
## Flattened Device Tree blob at
00000100
Booting using the fdt blob at 0x000100
Loading Ramdisk to
39c14000, end
3ab45067 ... OK
Using Device Tree in place at
00000100, end
000045ea
...
[ 0.599346] Unpacking initramfs...
[ 0.602924] Unable to handle kernel paging request at virtual address
f9c14000
Placement of the device tree was fixed in
89ca1000 (ARM: rpi: set fdt_high
in the default environment).
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Wed, 10 Feb 2016 22:16:19 +0000 (15:16 -0700)]
Makefile: remove BUILD_TAG from KBUILD_CFLAGS
If BUILD_TAG is part of KBUILD_CFLAGS, then any time the value changes,
all files get rebuilt. In a continuous integration environment, the value
will change every build. This wastes time, assuming that incremental
builds would otherwise occur.
To solve this, remove BUILD_TAG from KBUILD_CFLAGS and add it to CFLAGS
for just the one file that uses it. This does have the disadvantage that
if any other files want to use the flag, we'll need to duplicate this
custom CFLAGS setup logic. However, it seems unlikely we'll need this.
An alternative would be to add BUILD_TAG to the "local version" and remove
the special case code from display_options.c. However, that would affect
the format of the U-Boot signon message, which may negatively affect
people looking for specific data there. The approach of using
file-specific CFLAGS was suggested by Masahiro Yamada.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Adam Ford [Wed, 10 Feb 2016 07:41:10 +0000 (01:41 -0600)]
OMAP3_logic: Add NAND args to boot UBIFS
With the recent addition of UBI support, this patch will add the preset
parameters to allow for mouting an UBIFS from the 'fs' partition in NAND.
-V2: ubi.mtd=fs instead of ubi.mtd=4
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Vignesh R [Wed, 10 Feb 2016 05:36:09 +0000 (11:06 +0530)]
am43xx: qspi: Fix config to select SPI mode
CONFIG_SF_DEFAULT_MODE is used to select default SPI mode when using
sf commands. Therefore fix am43xx to use CONFIG_SF_DEFAULT_MODE instead
of CONFIG_DEFAULT_SPI_MODE.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 10 Feb 2016 05:21:43 +0000 (10:51 +0530)]
ARM : DRA7: Switch QSPI to use MODE-0 at 64MHz
According to Data Manual(SPRS915P) of AM572x, TI QSPI controller on
DRA74 EVM(rev 1.1+) can support up to 64MHz in MODE-0, whereas MODE-3 is
limited to 48MHz. Hence, switch to MODE-0 for better throughput.
Also, add IODelay parameters for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
David Müller (ELSOFT AG) [Tue, 9 Feb 2016 15:48:31 +0000 (16:48 +0100)]
arm: VCMA9: because of NOR flash space constrains, activate THUMB build mode
Signed-off-by: David Müller <d.mueller@elsoft.ch>
David Müller (ELSOFT AG) [Tue, 9 Feb 2016 15:48:30 +0000 (16:48 +0100)]
arm: build some file(s) as ARM mode only
Signed-off-by: David Müller <d.mueller@elsoft.ch>
David Müller (ELSOFT AG) [Tue, 9 Feb 2016 15:48:29 +0000 (16:48 +0100)]
arm: the ARM920T is THUMB capable, so select the appropriate ISA
Signed-off-by: David Müller <d.mueller@elsoft.ch>
David Müller (ELSOFT AG) [Tue, 9 Feb 2016 15:48:28 +0000 (16:48 +0100)]
arm: make sure board_init_r() is being called using the right mode (ARM / THUMB)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
Vagrant Cascadian [Tue, 9 Feb 2016 03:55:31 +0000 (19:55 -0800)]
Fix variable documented in README.distro for PXE address.
Fixes typo of pxe_addr_r with pxefile_addr_r.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Adam Ford [Tue, 9 Feb 2016 03:27:19 +0000 (21:27 -0600)]
OMAP3LOGIC: Update maintainer
I will take this over from Peter Barada, since I work with it daily
at Logic PD.
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peter Barada <peter.barada@logicpd.com>
Adam Ford [Tue, 9 Feb 2016 01:06:08 +0000 (19:06 -0600)]
OMAP3: omap3_logic: Grow SPL to 64K from 54K
Based on the work done by Overo, this seems to help some compilers
that have a hard time fitting all the code into the allocated space.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Derald D. Woods [Mon, 8 Feb 2016 02:54:47 +0000 (20:54 -0600)]
OMAP3: am3517_evm: SD/MMC boot with uEnv.txt, zImage, and FDT
Boot with the Linux zImage and am3517-evm.dtb pair, when SD/MMC media
is present. This behavior can be overridden by creating a 'uEnv.txt'
file with 'uenvcmd' defined.
To boot an existing 'uImage', create the following 'uEnv.txt':
[start]-----------------------------------------------------------------
loaduimage=fatload mmc 0:1 ${loadaddr} ${bootfile}
uenvcmd=run loaduimage; run mmcargs; bootm ${loadaddr}
[end]-------------------------------------------------------------------
Inspired by similar patches, for other OMAP3 boards, from EEWiki
- https://github.com/eewiki/u-boot-patches/tree/master/v2016.01
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 14 Feb 2016 13:39:32 +0000 (08:39 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
Masahiro Yamada [Fri, 12 Feb 2016 11:27:02 +0000 (20:27 +0900)]
ARM: uniphier: add support for PH1-Pro4 Ace and Sanji boards
Initial commit for PH1-Pro4 Ace and Sanji boards.
Note:
There are two variants for the Ace board in terms of the amount of
DDR memory; 1GB or 2GB.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 12 Feb 2016 11:27:01 +0000 (20:27 +0900)]
ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board
This is used for on-board inter-connection.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 12 Feb 2016 11:27:00 +0000 (20:27 +0900)]
ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board
This board has an EEPROM connected to the I2C channel 0 of the SoC.
Its slave address is 0x54.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 9 Feb 2016 09:59:52 +0000 (18:59 +0900)]
ARM: uniphier: drop unnecessary "bootm_low" environment define
This environment define has been here to work around the LMB
allocation error introduced by commit
9c11135ce053 ("image: fix
getenv_bootm_size() function").
It is no longer needed because the root cause was fixed by commit
0cb389dd1a38 ("image: fix getenv_bootm_size() function again").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 5 Feb 2016 04:21:07 +0000 (13:21 +0900)]
ARM: uniphier: adjust DDR clock delay line for ProXstream2
It turned out that DDR channel 2 was not working on ProXstream2
Vodka board. Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 5 Feb 2016 04:20:32 +0000 (13:20 +0900)]
ARM: uniphier: move cmd_ddrmphy.c to fix build error
If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails.
Fixes:
93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 5 Feb 2016 04:20:31 +0000 (13:20 +0900)]
ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.c
The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram
to build these commands.
Fixes:
93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:51:41 +0000 (21:51 +0900)]
ARM: uniphier: remove unused header mio-regs.h
This header is no longer used.
This is the last file in arch/arm/mach-uniphier/include/mach/.
At last, I've succeeded in eliminating the mach directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:40 +0000 (21:11 +0900)]
ARM: uniphier: drop unneeded EHCI pin mux settings
These pin mux settings are cared by the pinctrl drivers.
Remove the ad-hoc code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:38 +0000 (21:11 +0900)]
usb: remove UniPhier EHCI driver
Now, all this driver does can be covered by the generic EHCI driver
(drivers/usb/host/ehci-generic.c). UniPhier SoCs have switched to
use it. Delete this driver rather than bothering to convert it to
Driver Model.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:39 +0000 (21:11 +0900)]
ARM: uniphier: switch over to generic EHCI driver
The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does
nothing special but set the base address and handle reset/clock.
Since commit
4feefdcfe916 ("usb: add clock support for generic EHCI"),
the generic one (drivers/usb/host/ehci-generic.c) can do those, too.
We no longer need to stick to the dedicated driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:37 +0000 (21:11 +0900)]
ARM: dts: uniphier: add clocks properties to EHCI nodes
This allows the EHCI driver to get clocks from device tree.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:36 +0000 (21:11 +0900)]
ARM: dts: uniphier: add device nodes for MIO control block
This block provides clock and reset control for MIO (Media I/O)
hardware blocks such as USB2.0, SD card, eMMC, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:35 +0000 (21:11 +0900)]
ARM: dts: uniphier: add device nodes for Peripheral control block
This block provides clock and reset control for peripherals such as
UART, I2C, IC card, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:34 +0000 (21:11 +0900)]
ARM: dts: uniphier: add device nodes for System Control blocks
These are mainly used for controlling clocks and resets.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 2 Feb 2016 12:11:33 +0000 (21:11 +0900)]
ARM: dts: uniphier: add reference clock nodes
Add master clock nodes generated by crystal oscillators.
PH1-sLD3, PH1-LD4: 24.576 MHz
PH1-Pro4, ProXstream2: 25.000 MHz
PH1-Pro5: 20.000 MHz
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>