Marek Vasut [Fri, 26 Jun 2015 16:56:54 +0000 (18:56 +0200)]
ddr: altera: Fix debug message format in sequencer
The debug messages missed proper newlines and/or spaces in them.
Fix the formatting.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Wed, 8 Jul 2015 23:47:56 +0000 (01:47 +0200)]
ddr: altera: Fix typo in mp_threshold1 programming
It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Sun, 26 Jul 2015 08:37:54 +0000 (10:37 +0200)]
ddr: altera: Move struct sdram_prot_rule prototype
Move the structure prototype from sdram.h header file into sdram.c
source file, since it is used only there and for local purpose only.
There is no point in having it global.
While at this move, fix the data types in the structure from uintNN_t
to uNN and fix the coding style a bit.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 13:59:10 +0000 (15:59 +0200)]
arm: socfpga: Move sdram_config.h to board dir
This file is absolutelly positively board specific, so move it
into the correct place.
Signed-off-by: Marek Vasut <marex@denx.de>
Dinh Nguyen [Wed, 3 Jun 2015 03:52:50 +0000 (22:52 -0500)]
arm: socfpga: enable the Altera SDRAM controller driver
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Dinh Nguyen [Wed, 3 Jun 2015 03:52:49 +0000 (22:52 -0500)]
driver/ddr/altera: Add the sdram calibration portion
This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh Nguyen [Wed, 3 Jun 2015 03:52:48 +0000 (22:52 -0500)]
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 25 Jul 2015 16:42:34 +0000 (18:42 +0200)]
net: designware: Rename the driver var name to eth_designware
The driver variable name is eth_sandbox, which is probably a copy-paste
mistake. Fix it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 25 Jul 2015 16:38:44 +0000 (18:38 +0200)]
net: designware: Add SoCFPGA GMAC DT compatible string
Add the OF compatible property to match the SoCFPGA GMAC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 25 Jul 2015 06:22:21 +0000 (08:22 +0200)]
arm: socfpga: Move generated files into qts subdir
Move all the files generated by Quartus into the qts/ subdir of the
board/altera/socfpga dir to make them explicitly separate from the
generic U-Boot code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 25 Jul 2015 08:47:22 +0000 (10:47 +0200)]
arm: dts: socfpga: Add mmc alias
Add alias for the SD/MMC controller, so it can be located by U-Boot OF support.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Tue, 21 Jul 2015 09:25:14 +0000 (11:25 +0200)]
arm: dts: socfpga: Fix SPI aliases
The SPI aliases are completely wrong. First, they point to non-existing
/spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use
ad-hoc string instead of a handle. Furthermore, they are copied multiple
times in each board DTS.
So fix it such that we move these into socfpga.dtsi and make them use
the usual handles.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Mon, 27 Jul 2015 20:34:54 +0000 (22:34 +0200)]
arm: socfpga: Fix FPGA bitstream programming routine
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Tom Rini [Thu, 6 Aug 2015 23:56:03 +0000 (19:56 -0400)]
Merge git://git.denx.de/u-boot-dm
Stephen Warren [Wed, 5 Aug 2015 17:52:08 +0000 (11:52 -0600)]
ARM: tegra: Add p2371-0000 board
P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
board. The combination contains SoC, DRAM, eMMC, SD card slot,
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 5 Aug 2015 17:52:07 +0000 (11:52 -0600)]
ARM: tegra: Add e2220-1170 board
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
expansion modules.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 5 Aug 2015 17:51:11 +0000 (11:51 -0600)]
ARM: tegra: p2571: remove another unused define
CONFIG_MAX77620_POWER isn't used anywhere. Don't define it in p2571.h.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Alexandre Courbot [Thu, 9 Jul 2015 07:33:01 +0000 (16:33 +0900)]
ARM: tegra: enable GPU DT node when appropriate
T124/210 requires some specific configuration (VPR setup) to
be performed by the bootloader before the GPU can be used.
For this reason, the GPU node in the device tree is disabled
by default. This patch enables the node if U-boot has performed
VPR configuration.
Boards enabled by this patch are T124's Jetson TK1 and Venice2
and T210's P2571.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Alexandre Courbot [Thu, 9 Jul 2015 07:33:00 +0000 (16:33 +0900)]
ARM: tegra: move VPR configuration to a later stage
U-boot is responsible for enabling the GPU DT node after all necessary
configuration (VPR setup for T124) is performed. In order to be able to
check whether this configuration has been performed right before booting
the kernel, make it happen during board_init().
Also move VPR configuration into the more generic gpu.c file, which will
also host other GPU-related functions, and let boards specify
individually whether they need VPR setup or not.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 30 Jul 2015 20:34:09 +0000 (14:34 -0600)]
ARM: tegra: add comment re: autogeneration to pinmux headers
Add a comment block to the top of each generated Tegra pinmux header file
indicating that the file was auto-generated, should not be manually
edited, and with a pointer to the tool and command used to generate it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 29 Jul 2015 19:47:58 +0000 (13:47 -0600)]
ARM: tegra: restrict usable RAM size further
Additionally, ARM64 devices typically run a secure monitor in EL3 and
U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
code and data. These carve-outs are located at the top of 32-bit address
space. Restrict U-Boot's RAM usage to well below the location of those
carve-outs. Ideally, we would the secure monitor would inform U-Boot of
exactly which RAM it could use at run-time. However, I'm not sure how to
do that at present (and even if such a mechanism does exist, it would
likely not be generic across all forms of secure monitor).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Mon, 3 Aug 2015 14:19:19 +0000 (08:19 -0600)]
exynos: dts: Correct LDO and BUCK naming
At present lower case is used for the regulator names in the device tree.
The kernel uses upper case and U-Boot will require this also since it will
move to a case-sensitive name check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 00:07:21 +0000 (18:07 -0600)]
x86: Enable debug UART for Minnowmax
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.
Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.
So this means that the character output cannot be any earlier than
car_init_ret, where memory is available for a stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Simon Glass [Thu, 30 Jul 2015 19:40:40 +0000 (13:40 -0600)]
dm: core: Fix a typo in the uclass_get_device_by_name() comment
This function comment has a typo. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 30 Jul 2015 19:40:39 +0000 (13:40 -0600)]
dm: core: Add a way to set a device name
Some devices are bound entirely by probing and do not have the benefit of
a device tree to give them a name. This is very common with PCI and USB. In
most cases this is fine, but we should add an official way to set a device
name. This should be called in the device's bind() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 28 Jul 2015 17:53:14 +0000 (11:53 -0600)]
sandbox: Enable devres subsystem
This should be used for sandbox. We can convert at least one driver to use
it, but in the meantime, enable the feature so that the code is
build-tested.
Signed-off-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:38 +0000 (21:52 +0900)]
devres: add debug command to dump device resources
This new command can dump all device resources associated to
each device. The fields in every line shows:
- The address of the resource
- The size of the resource
- The name of the release function
- The stage in which the resource has been acquired (BIND/PROBE)
Currently, there is no driver using devres, but if such drivers are
implemented, the output of this command should look like this:
=> dm devres
- root_driver
- soc
- extbus
- serial@
54006800
bfb541e8 (8 byte) devm_kmalloc_release BIND
bfb54440 (4 byte) devm_kmalloc_release PROBE
bfb54460 (4 byte) devm_kmalloc_release PROBE
- serial@
54006900
bfb54270 (8 byte) devm_kmalloc_release BIND
- gpio@
55000000
- i2c@
58780000
bfb5bce8 (12 byte) devm_kmalloc_release PROBE
bfb5bd10 (4 byte) devm_kmalloc_release PROBE
- eeprom
bfb54418 (12 byte) devm_kmalloc_release BIND
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:37 +0000 (21:52 +0900)]
devres: make Devres optional with CONFIG_DEVRES
Currently, Devres requires additional 16 byte for each allocation,
which is not so insignificant in some cases.
Add CONFIG_DEVRES to make this framework optional.
If the option is disabled, devres functions fall back to
non-managed variants. For example, devres_alloc() to kzalloc(),
devm_kmalloc() to kmalloc(), etc.
Because devres_head is also surrounded by an ifdef conditional,
there is no memory overhead when CONFIG_DEVRES is disabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:36 +0000 (21:52 +0900)]
devres: add devm_kmalloc() and friends (managed memory allocators)
devm_kmalloc() is identical to kmalloc() except that the memory
allocated with it is managed and will be automatically released
when the device is removed/unbound.
Likewise for the other variants.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:35 +0000 (21:52 +0900)]
devres: introduce Devres (Managed Device Resource) framework
In U-Boot's driver model, memory is basically allocated and freed
in the core framework. So, low level drivers generally only have
to specify the size of needed memory with .priv_auto_alloc_size,
.platdata_auto_alloc_size, etc. Nevertheless, some drivers still
need to allocate/free memory on their own in case they cannot
statically know the necessary memory size. So, I believe it is
reasonable enough to port Devres into U-boot.
Devres, which originates in Linux, manages device resources for each
device and automatically releases them on driver detach. With devres,
device resources are guaranteed to be freed whether initialization
fails half-way or the device gets detached.
The basic idea is totally the same to that of Linux, but I tweaked
it a bit so that it fits in U-Boot's driver model.
In U-Boot, drivers are activated in two steps: binding and probing.
Binding puts a driver and a device together. It is just data
manipulation on the system memory, so nothing has happened on the
hardware device at this moment. When the device is really used, it
is probed. Probing initializes the real hardware device to make it
really ready for use.
So, the resources acquired during the probing process must be freed
when the device is removed. Likewise, what has been allocated in
binding should be released when the device is unbound. The struct
devres has a member "probe" to remember when the resource was
allocated.
CONFIG_DEBUG_DEVRES is also supported for easier debugging.
If enabled, debug messages are printed each time a resource is
allocated/freed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:34 +0000 (21:52 +0900)]
dm: add DM_FLAG_BOUND flag
Currently, we only have DM_FLAG_ACTIVATED to indicate the device
status, but we still cannot know in which stage is in progress,
binding or probing.
This commit introduces a new flag, DM_FLAG_BOUND, which is set when
the device is really bound, and cleared when it is unbound.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:44 +0000 (20:53 -0600)]
dm: Support address translation for simple-bus
The 'ranges' property can be used to specify a translation from the system
address to the bus address. Add support for this using the dev_get_addr()
function, which devices should use to find their address.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:42 +0000 (20:53 -0600)]
net: smsc95xx: Add driver-model support
Add support for driver model, so that CONFIG_DM_ETH can be defined and used
with this driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:41 +0000 (20:53 -0600)]
net: smsc95xx: Prepare for conversion to driver model
At present struct eth_device is passed around all over the place. This does
not exist with driver model. Add explicit arguments instead, so that with
driver model we can pass the correct things.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:40 +0000 (20:53 -0600)]
net: smsc95xx: Correct the error numbers
Instead of returning -1 on error, we should use a proper error number. Fix
the code to conform to this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:39 +0000 (20:53 -0600)]
net: smsc95xx: Rename AX_RX_URB_SIZE to RX_URB_SIZE
The AX_ prefix comes from the Asix driver. Since this is not that, we should
avoid this confusing prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:38 +0000 (20:53 -0600)]
net: smsc95xx: Sort the include files
Tidy up the include file order before adding more.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:37 +0000 (20:53 -0600)]
dm: usb: Add driver-model support to dwc2
Add driver model support to this driver so it can be used with the new USB
stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:36 +0000 (20:53 -0600)]
dm: usb: Prepare dwc2 driver for driver-model conversion
Put all global data in a structure and move (what will be) common code into
common functions. This will make the driver-model conversion much easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:35 +0000 (20:53 -0600)]
dm: usb: Add an errno.h header to usb_ether.c
This is required on some platforms, so add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 17 Jul 2015 15:22:07 +0000 (09:22 -0600)]
dm: Make regmap and syscon optional
Not all boards use garbage collection in their link step, so we should avoid
adding options that rely on this for prevention of code bloat. Add separate
Kconfig options for syscon and regmap uclasses.
Signed-off-by: Simon Glass <sjg@chromium.org>
York Sun [Mon, 3 Aug 2015 19:02:04 +0000 (12:02 -0700)]
lib/fdtdec: Fix fdt_addr_t and fdt_size_t typedef
fdt_addr_t is a physical address. It can be either 64-bit or 32-bit,
depending on the architecture. It should be phys_addr_t instead of
u64 or u32. Similarly, fdt_size_t is changed to phys_size_t.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
York Sun [Mon, 3 Aug 2015 19:02:05 +0000 (12:02 -0700)]
lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t type
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:37 +0000 (08:19 -0600)]
exynos: Add support for spring
Spring is the first ARM-based HP Chromebook 11. It is similar to snow
and it uses the same Samsung Exynos5250 chip. But has some unusual
features. Mainline support for it has lagged snow (both in kernel and
U-Boot). Now that the exynos5 code is common we can support spring just
by adding a device tree and a few lines of configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:36 +0000 (08:19 -0600)]
exynos: video: Remove non-device-tree code
We always use device tree on exynos, so remove the unused code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:35 +0000 (08:19 -0600)]
dts: Drop unused compatible ID for the NXP video bridge
This has moved to driver model so we can drop the fdtdec support.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:34 +0000 (08:19 -0600)]
video: Remove the old parade driver
We have a new one which uses driver model and device tree configuration.
Remove the old one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:33 +0000 (08:19 -0600)]
cros_ec: Remove the old tunnel code
This is not needed with driver mode. Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:32 +0000 (08:19 -0600)]
power: Remove old TPS65090 drivers
Remove the old drivers (both the normal one and the cros_ec one) now that
we have new drivers that use driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:31 +0000 (08:19 -0600)]
exynos: Drop old exynos5250-specific board code
Now that most exynos5250 boards can use the generic exynos5 code, switch
over to it and remove the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:30 +0000 (08:19 -0600)]
exynos: Drop old exynos5420-specific board code
Now that exynos5420 boards can use the generic exynos5 code, switch over to
it and remove the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Mon, 3 Aug 2015 14:19:29 +0000 (08:19 -0600)]
exynos: config: Move common options to the common headers and tidy up
Many options are duplicated on the exynos5 boards. Move these to the common
files. Also some options are not used so can be removed.
Tidy this up to make the files easier to maintain.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:16:23 +0000 (18:16 -0600)]
exynos: Remove unneeded device tree control #ifdefs
Since device tree is used for all exynos5 boards, we can remove the #ifdef
and reduce confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:28 +0000 (08:19 -0600)]
exynos: Enable new features for exynos5 boards
Enable PMICs, regulators and the like so that new drivers will be made
available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:27 +0000 (08:19 -0600)]
exynos: Add common board code for exynos5 boards that use device tree
Some boards use device tree for almost all board-specific configuration.
They therefore do not need their own separate board code, but can all use
the same version. Add a common version of the board code. It uses the
PMIC, regulator and video bridge uclasses. This will support smdk5250,
smdk5420, snow, spring, pit and pi.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:26 +0000 (08:19 -0600)]
exynos: dts: Drop the old TPS65090 I2C node
While the AP can access the main PMIC on snow, it must coordinate with the
EC which also wants access. Drop the old definition, which can in principle
generate collision errors. We will use the new arbitration driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:19 +0000 (18:16 -0600)]
dts: exynos: snow: Add a new node for the NXP video bridge driver
The driver supports driver model. Add a node for snow, which needs it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:18 +0000 (18:16 -0600)]
dts: exynos: pit: Add a new node for the parade video bridge driver
The new driver supports driver model and configuration via device tree. Add
a node for pit, which needs this driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:17 +0000 (18:16 -0600)]
dts: exynos: snow: Add memory layout description
Add a description of the snow memory layout to assist flashing tools which
want to be able to deal with any exynos image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:16 +0000 (18:16 -0600)]
dm: gpio: Check a GPIO is valid before using it
Since a gpio_desc is allowed to be invalid we should return an error
indicating that the operation cannot be completed. This can happen if the
GPIO is optional - e.g. some devices may have a reset line and some may
not.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:15 +0000 (18:16 -0600)]
exynos: Tidy up CPU frequency display
Line up the display with the line below, e.g.:
CPU: Exynos5250 @ 1.7 GHz
Model: Google Spring
DRAM: 2 GiB
MMC: EXYNOS DWMMC: 0
Also show the speed as GHz where appropriate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:14 +0000 (18:16 -0600)]
exynos: video: Correct debug output
We should not print a message from the driver when the display is set up.
This is normal behaviour. Change this message to use debug().
Also remove the double newline on another debug message.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:13 +0000 (18:16 -0600)]
exynos: Add support for the DisplayPort hotplug detect
Allow this function to be selected using the pinmux API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:12 +0000 (18:16 -0600)]
exynos: Correct return value in exynos_mmc_init()
This function should return 0 on success, not 1. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:11 +0000 (18:16 -0600)]
exynos: spi: Convert the timeout to debug()
Since the timeout is reported through normal channels, and is sometimes
expected (e.g. if the bus is being probed for a non-existent device),
don't display the message in the driver.
In general, drivers should not write to the console as this limits their
usefulness in error conditions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:10 +0000 (18:16 -0600)]
dm: video: Add support for the NXP PTN3460 bridge
This chip provides an eDP to LVDS bridge which is useful for SoCs that don't
support LVDS displays (or it would waste scarce pins). There is no setup
required by this chip, other than to adjust power-down and reset pins, and
those are managed by the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:09 +0000 (18:16 -0600)]
dm: video: Add support for the Parade PS8622/625 bridge
This chip provides an eDP to LVDS bridge which is useful for SoCs that don't
support LVDS displays (or it would waste scarce pins). The setup is included
in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:20 +0000 (08:19 -0600)]
video: Work around lack of pinctrl
We haven't quite got pinctrl ready to apply to mainline. We don't want to
GPIO pull-up/down support to the driver model GPIO layer either. So work
around this for now.
We can address this when pinctrl is complete.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:08 +0000 (18:16 -0600)]
dm: video: Add support for video bridges
A video bridge typically converts video from one format to another, e.g.
DisplayPort to LVDS. Add driver model support for these with a simple
interface to control activation and backlight. The uclass supports GPIO
control of power and reset lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:07 +0000 (18:16 -0600)]
dm: pmic: Display the regulator limits on error
When a regulator command cannot honour the requested voltage, display the
limits to try to be helpful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:16:06 +0000 (18:16 -0600)]
dm: power: Don't return an error when regulators are not autoset
Not all regulators can be set up automatically. Adjust the code so that
regulators_enable_boot_on() will return success when some are skipped.
Only genuine errors are reported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Mon, 3 Aug 2015 14:19:25 +0000 (08:19 -0600)]
dm: pmic: max77686: Support all BUCK regulators
Add support for all BUCK regulators, now that the correct register is
accessed for each.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:16:04 +0000 (18:16 -0600)]
dm: power: max77686: Correct BUCK register access
Some regulators use the wrong voltage register and thus it is not possible
to control them. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:16:03 +0000 (18:16 -0600)]
dm: pmic: Correct the pmic_reg_write() implementation
This should write the register, not read it. Fix this bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:16:02 +0000 (18:16 -0600)]
dm: pmic: max77686: Correct a few nits
The driver name should not have a space in it. Also the regulator names
should match the case of the device tree. Fix these problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:16:01 +0000 (18:16 -0600)]
dm: power: Add support for S5M8767 regulators
This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
driver supports changing voltage and enabling/disabling each regulator. It
supports the standard device tree binding and supports driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:16:00 +0000 (18:16 -0600)]
dm: power: Add support for the S5M8767 PMIC
This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
driver supports probing and basic register access. It supports the standard
device tree binding and supports driver model. A regulator driver can be
provided also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:15:59 +0000 (18:15 -0600)]
dm: power: Add support for TPS65090 FETs
The TPS65090 has 7 FETs which are modelled as regulators. This allows them
to be controlled by drivers easier, accessed through the 'regulator' command
and used by other drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:15:58 +0000 (18:15 -0600)]
dm: power: Add a new driver for the TPS65090 PMIC
The existing TPS65090 driver does not support driver model. Add a new one
that does. This can be used as a base for a regulator driver also. It uses
the standard device tree binding.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:15:55 +0000 (18:15 -0600)]
exynos: Enable the debug UART in SPL
As a debugging aid, allow UART3 to be used as a debug UART in SPL. This
is a precursor to proper UART support, which requires a substantial
refactor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:15:54 +0000 (18:15 -0600)]
exynos: Add debug UART support for Samsung S5P serial
Add a debug UART implementation for this serial driver. It does not set up
pinmux automatically - this must be done before calling debug_uart_init().
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:15:53 +0000 (18:15 -0600)]
exynos: serial: Refactor init code for debug UART
The debug UART code needs to perform the same init as the normal UART
driver. In preparation for this, move the init code into two functions, one
for the basic init and one for setting the baud rate. This will make adding
debug UART support easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:24 +0000 (08:19 -0600)]
cros_ec: Support the LDO access method used by spring
Add a driver to support the special LDO access used by spring. This is a
custom method in the cros_ec protocol - it does not use an I2C
pass-through.
There are two implementation choices:
1. Write a special LDO driver which can talk across the EC. Duplicate all
the logic from TPS65090 for retrying when the LDO fails to come up.
2. Write a special I2C bus driver which pretends to be a TPS65090 and
transfers reads and writes using the LDO message.
Either is distasteful. The latter method is chosen since it results in less
code duplication and a fairly simple (30-line) implementation of the core
logic.
The crosec 'ldo' subcommand could be removed (since i2c md/mw will work
instead) but is retained as a convenience.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:23 +0000 (08:19 -0600)]
dm: cros_ec: Convert the I2C tunnel code to use driver model
The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This
currently uses a copy of the I2C command code and a special 'crosec'
sub-command.
With driver model we can define an I2C bus which tunnels through to the EC,
and use the normal 'i2c' command to access it. This simplifies the code and
removes some duplication.
Add an I2C driver which tunnels through to the EC. Adjust the EC code to
support binding child devices so that it can be set up. Adjust the existing
I2C xfer function to fit driver model better.
For now the old code remains to allow things to still work. It will be
removed in a later patch once the new flow is fully enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:15:50 +0000 (18:15 -0600)]
exynos: dts: Support EC tunnel and main TPS65090 regulator
On pit and pi the TPS65090 regulator is connected only to the EC and we
must use a tunnel to get to it. The existing U-Boot support relies on a
special driver. Add a tunnel definition so that the new device-model
TPS65090 driver can be used unmodified.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:15:49 +0000 (18:15 -0600)]
exynos: dts: Add PMIC and regulator definitions
Snow and smdk5250 use a max77686 PMIC. We have a driver for this, so add
the relevant node to the device tree so it can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:15:48 +0000 (18:15 -0600)]
exynos: dts: Sync up I2C ports with the kernel
The kernel uses upper case for I2C unit addresses. Follow the same
convention to reduce differences.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Simon Glass [Fri, 3 Jul 2015 00:15:47 +0000 (18:15 -0600)]
exynos: i2c: Tidy up the driver model code
The existing driver model implementation uses the old non-driver-model code
to operate, but has become impossibly tangled as a result. The actual
algorithm is quite simple.
Also the normal-speed and high-speed buses are quite different and it
doesn't seem that useful to put them in the same driver.
Finally, there is a bug which breaks communication with the Maxim sound
codec and may cause problems with other device.
Rewrite the driver model code for normal-speed operation so that it is
easier to understand, and fix the bug. Add a TODO to split the drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Simon Glass [Fri, 3 Jul 2015 00:15:46 +0000 (18:15 -0600)]
exynos: i2c: Fix code style with ReadWriteByte()
This function should not use mixed case, and it is simpler to use
clrbits_le32() when clearing bits. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Mon, 3 Aug 2015 14:19:22 +0000 (08:19 -0600)]
i2c: Add a mux for GPIO-based I2C bus arbitration
While I2C supports multi-master buses this is difficult to get right.
The implementation on the master side in software is quite complex.
Clock-stretching and the arbitrary time that an I2C transaction can take
make it difficult to share the bus fairly in the face of high traffic.
When one or more masters can be reset independently part-way through a
transaction it is hard to know the state of the bus.
This driver provides a scheme based on two 'claim' GPIOs, one driven by the
AP (Application Processor, meaning the main CPU) and one driven by the EC
(Embedded Controller, a small CPU aimed at handling system tasks). With
these they can communicate and reliably share the bus. This scheme has
minimal overhead and involves very little code. It is used on snow to
permit the EC and the AP to share access to the main system PMIC and
battery. The scheme can survive reboots by either side without difficulty.
This scheme has been tested in the field with millions of devices.
Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
meaning the AP's, and 'their' claim GPIO, meaning the EC's. This terminology
is used by the device tree bindings in Linux also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:21 +0000 (08:19 -0600)]
dm: i2c: Add support for multiplexed I2C buses
Add a new I2C_MUX uclass. Devices in this class can multiplex between
several I2C buses, selecting them one at a time for use by the system.
The multiplexing mechanism is left to the driver to decide - it may be
controlled by GPIOs, for example.
The uclass supports only two methods: select() and deselect().
The current mux state is expected to be stored in the mux itself since
it is the only thing that knows how to make things work. The mux can
record the current state and then avoid switching unless it is necessary.
So select() can be skipped if the mux is already in the correct state.
Also deselect() can be made a nop if required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 3 Jul 2015 00:15:42 +0000 (18:15 -0600)]
dm: i2c: Add a function to transfer messages
Sometimes it is useful to be able to transfer a raw I2C message. This
happens when the chip address needs to be set manually, or when the data to
be sent/received is in another buffer.
Add a function to provide access to this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Fri, 3 Jul 2015 00:15:41 +0000 (18:15 -0600)]
dm: i2c: Move definitions to the top of the header file
Move the flags and struct definitions higher in the file so that we can
reference them with functions declared in the driver model section.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Fri, 3 Jul 2015 00:15:40 +0000 (18:15 -0600)]
dm: i2c: Correct comment nits in dm_i2c_reg_read/write()
Add documentation for the @dev parameter.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Fri, 3 Jul 2015 00:15:39 +0000 (18:15 -0600)]
dm: i2c: Add a message debug function
Add a way to dump the contents of an I2C message for debugging purposes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Fri, 3 Jul 2015 00:15:38 +0000 (18:15 -0600)]
dm: core: Support finding a device by phandle
It is common for one node to reference another via a phandle. Add support
for obtaining an attached device by this method. As an example, a node may
have a 'power-supply' property which references a regulator, allowing the
driver to turn on its power.
Signed-off-by: Simon Glass <sjg@chromium.org>
Marcel Ziswiler [Wed, 5 Aug 2015 14:58:17 +0000 (16:58 +0200)]
dm: usb: fix USB Ethernet without CONFIG_DM_ETH regression
The following commit enforces CONFIG_DM_ETH for USB Ethernet which
breaks any board using CONFIG_USB_HOST_ETHER without CONFIG_DM_ETH
which this patch fixes.
commit
69559093f6173dcfcb041df0995063bdbd07d49b
dm: usb: Avoid using USB ethernet with CONFIG_DM_USB and no DM_ETH
Tested on Colibri T20/T30 as well as Apalis T30 with
CONFIG_USB_HOST_ETHER and CONFIG_USB_ETHER_ASIX enabled and a LevelOne
USB-0301 ASIX AX88772 dongle.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Warren [Thu, 30 Jul 2015 21:00:15 +0000 (14:00 -0700)]
Tegra: P2571: Clean up config file
Removed NS16550_COM1 #define, not used since there's no SPL for T210
Also changed the number of USB controllers to 1 as only USBD is used.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Warren [Thu, 30 Jul 2015 02:36:38 +0000 (19:36 -0700)]
Tegra: spi: Move TEGRA114_SPI switch to defconfigs
All T114+ Tegra boards should be using the Kconfig
TEGRA114_SPI switch. Remove it from include/config
and put it into defconfig. Also removed unused
TEGRA114_SPI_CTRLS from T114+ configs.
All Tegra SoCs build OK with this change.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Warren [Thu, 25 Jun 2015 16:50:44 +0000 (09:50 -0700)]
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>