oweals/u-boot.git
7 years agostatus_led: Kconfig migration - introduction
Uri Mashiach [Thu, 19 Jan 2017 08:51:05 +0000 (10:51 +0200)]
status_led: Kconfig migration - introduction

Move all of the status LED feature to drivers/led/Kconfig.
doc/README.LED updated to reflect the Kconfig implementation.

Tested boards: CL-SOM-AM57x, CM-T335

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
7 years agoconfig: Move CONFIG_BOARD_LATE_INIT to defconfigs
Jagan Teki [Sat, 21 Jan 2017 10:48:33 +0000 (11:48 +0100)]
config: Move CONFIG_BOARD_LATE_INIT to defconfigs

Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
7 years agocommon: Kconfig: Add BOARD_LATE_INIT entry
Jagan Teki [Sat, 21 Jan 2017 10:48:32 +0000 (11:48 +0100)]
common: Kconfig: Add BOARD_LATE_INIT entry

This patch add Kconfig entry for CONFIG_BOARD_LATE_INIT

Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
7 years agomx6saberesd_spl: Correct falcon mode addition
Tom Rini [Sat, 21 Jan 2017 00:55:53 +0000 (19:55 -0500)]
mx6saberesd_spl: Correct falcon mode addition

When falcon mode support was added, it was right around when SPL_OS_BOOT
was migrated to Kconfig.  So first we must move the enablement to the
defconfig file.  Next, it turned off EXT support rather than add the
information to allow for falcon mode from EXT.  Add this information so
that the board compiles after 5d28b930f237.

Fixes: d96796ca23b2 ("mx6sabresd: Add Falcon mode support")
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agobootm: qnx: Disable data cache before booting QNX image
Emmanuel Vadot [Thu, 19 Jan 2017 09:23:56 +0000 (10:23 +0100)]
bootm: qnx: Disable data cache before booting QNX image

Instead of disabling the data cache in the bootelf command, disabling
it in the do_bootm_qnxelf function.
Some ELF binary might want the cache enabled.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
7 years agotools: mkimage: fix sizeof_mismatch found by coverity
Sven Ebenfeld [Tue, 17 Jan 2017 18:36:51 +0000 (19:36 +0100)]
tools: mkimage: fix sizeof_mismatch found by coverity

Reported-by: Coverity (CID: 155214)
Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com>
7 years agoARM: OMAP5+: Remove unsed dpll structures
Lokesh Vutla [Tue, 17 Jan 2017 03:22:59 +0000 (08:52 +0530)]
ARM: OMAP5+: Remove unsed dpll structures

Latest gcc compile strted complaining about defined structure definition
that are not used. Remove the unused sturctures.

Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP4: Fix compiler warning
Lokesh Vutla [Tue, 17 Jan 2017 03:22:58 +0000 (08:52 +0530)]
ARM: OMAP4: Fix compiler warning

Latest gcc 6.2 compiler is throwing the below warning for omap4_panda_defconfig
arch/arm/mach-omap2/omap4/hw_data.c:136:3: warning: 'abe_dpll_params_sysclk_196608khz' defined but not used [-Wunused-const-variable=]
   abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {

Fix this by guarding it with CONFIG_SYS_OMAP_ABE_SYSCK

Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agobinman: add tools directory to the python path
Emmanuel Vadot [Mon, 16 Jan 2017 07:14:46 +0000 (08:14 +0100)]
binman: add tools directory to the python path

The built _libfdt.so is placed in the /tools dir and need to say here
as it contains relative paths.
Add the directory to the python path so binman can use this module.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
7 years agobuild: Always build the libfdt python module
Emmanuel Vadot [Mon, 16 Jan 2017 07:07:15 +0000 (08:07 +0100)]
build: Always build the libfdt python module

Do not rely on CONFIG_SPL_OF_PLATDATA to build the libfdt python module.
If swig is present, this will be build

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
7 years agoMAINTAINERS: DFU: Change e-mail address of DFU maintanier
Lukasz Majewski [Sun, 15 Jan 2017 23:04:10 +0000 (00:04 +0100)]
MAINTAINERS: DFU: Change e-mail address of DFU maintanier

Signed-off-by: Lukasz Majewski <lukma@denx.de>
7 years agoodroid-c2: Enable distro boot
Andreas Färber [Sun, 15 Jan 2017 19:22:30 +0000 (20:22 +0100)]
odroid-c2: Enable distro boot

Use the generic "distro" boot framework to enable automatic DHCP boot.
MMC and USB are not yet implemented, so this is the only boot option.

The fdt and kernel addresses are adopted from downstream; ramdisk and
scriptaddr addresses were chosen arbitrarily.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
7 years agomeson: misc_init_r is board-specific
Andreas Färber [Sun, 15 Jan 2017 18:53:53 +0000 (19:53 +0100)]
meson: misc_init_r is board-specific

Move it from meson-gxbb-common.h to odroid-c2.h to allow new boards not
to implement it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
7 years agoboard_init.c: Always use memset()
Tom Rini [Thu, 12 Jan 2017 18:16:03 +0000 (13:16 -0500)]
board_init.c: Always use memset()

We can make the code read more easily here by simply using memset()
always as when we don't have an optimized version of the function we
will still have a version of this function around anyhow.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: Default to using optimized memset and memcpy routines
Tom Rini [Thu, 12 Jan 2017 18:16:02 +0000 (13:16 -0500)]
ARM: Default to using optimized memset and memcpy routines

We have long had available optimized versions of the memset and memcpy
functions that are borrowed from the Linux kernel.  We should use these
in normal conditions as the speed wins in many workflows outweigh the
relatively minor size increase.  However, we have a number of places
where we're simply too close to size limits in SPL and must be able to
make the size vs performance trade-off in those cases.

Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomach-omap2: Fix secure boot media generation
Andrew F. Davis [Thu, 12 Jan 2017 16:21:58 +0000 (10:21 -0600)]
mach-omap2: Fix secure boot media generation

While moving OMAP related files to mach-omap2 the functionality
relating to generating secure boot files was modified. This change
prevents secure platforms other than AM33xx and OMAP54XX from
correctly building files for all needed media types.

Fixes: 983e37007da5 ("arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms")
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agospl: Add some missing newlines
Andrew F. Davis [Thu, 12 Jan 2017 16:19:55 +0000 (10:19 -0600)]
spl: Add some missing newlines

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
7 years agospl: Remove inline ifdef check for EXT and FAT support
Andrew F. Davis [Fri, 6 Jan 2017 19:35:45 +0000 (13:35 -0600)]
spl: Remove inline ifdef check for EXT and FAT support

These files are only included for build by the make system
when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed
checks for these in the source files.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agocommon/image.c: Use correct suffixes for binary sizes
xypron.glpk@gmx.de [Wed, 4 Jan 2017 13:04:44 +0000 (14:04 +0100)]
common/image.c: Use correct suffixes for binary sizes

IEC 80000-13:2008 Quantities and units
Part 13: Information science and technology

defines the prefixes to use for binary multiples.

So instead of writing
Data Size:    6726132 Bytes = 6568.49 kB = 6.41 MB
in dumpimage we should write
Data Size:    6726132 Bytes = 6568.49 KiB = 6.41 MiB.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoapi: storage: Test all block device in dev_stor_get
Emmanuel Vadot [Thu, 5 Jan 2017 05:40:21 +0000 (06:40 +0100)]
api: storage: Test all block device in dev_stor_get

In a config with one MMC at device id '1' and no MMC at device id '0'
(a BeagleBone Black with no sd inserted for example), the current code
will first test to access the MMC 0 (sd port), seeing that no device is
present it will simply return that no more device are present for this
class.
This patch fixes this by testing all devices for each class.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
7 years agoapi: Use hashtable function for API_env_enum
Emmanuel Vadot [Mon, 26 Dec 2016 17:57:56 +0000 (18:57 +0100)]
api: Use hashtable function for API_env_enum

The current code can loop undefinitly as it doesn't parse
correctly the env data.
Since the env is an hashtable, use the hashtable function for
the API_ENV_ENUM api call.

Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agocmd/host: add missing \n in help text
Sébastien Szymanski [Thu, 19 Jan 2017 16:49:13 +0000 (17:49 +0100)]
cmd/host: add missing \n in help text

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
7 years agoARM: omap3_logic: Refactor Boot Environmental variables
Adam Ford [Wed, 4 Jan 2017 17:51:24 +0000 (11:51 -0600)]
ARM: omap3_logic: Refactor Boot Environmental variables

Some scripts are calling the same functions, so these changes consolidate
common scripts together to reduce redundancy and shrink size a bit.  This
also keeps the 'bootargs' variable from growing if manually called more
than one time. This also adds NAND booting scripts based on newly consolidated
scripts.

Signed-off-by: Adam Ford <aford173@gmail.com>
7 years agobootm: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH set
Rick Altherr [Thu, 19 Jan 2017 01:12:24 +0000 (17:12 -0800)]
bootm: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH set

In 35fc84f, bootm was refactored so plain 'bootm' and
'bootm <subcommand>' shared a common implementation.
The 'bootm ramdisk' command implementation is now part of the common
implementation but not invoke by plain 'bootm' since the original
implementation never did ramdisk relocation.  Instead, ramdisk
relocation happened in image_setup_linux() which is typically called
during the OS portion of 'bootm'.

On ARM, parameters to the Linux kernel can either be passed by FDT or
ATAGS. When using FDT, image_setup_linux() is called which also triggers
ramdisk relocation.  When using ATAGS, image_setup_linux() is _not_
called because it mostly does FDT setup.

Instead of calling image_setup_linux() in both FDT and ATAGS cases,
include BOOTM_STATE_RAMDISK in the requested states during a plain
'bootm' if CONFIG_SYS_BOOT_RAMDISK_HIGH is set and remove the ramdisk
relocation from image_setup_linux().  This causes ramdisk relocation to
happen on any system where CONFIG_SYS_BOOT_RAMDISK_HIGH regardless of
the OS being booted. Also remove IMAGE_ENABLE_RAMDISK_HIGH as it was
only used by the now-removed code from image_setup_linux().

Signed-off-by: Rick Altherr <raltherr@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
7 years agoserial, ns16550: bugfix: ns16550 fifo not enabled
Heiko Schocher [Wed, 18 Jan 2017 07:05:49 +0000 (08:05 +0100)]
serial, ns16550: bugfix: ns16550 fifo not enabled

commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.

Since the above patch, you have to setup the fcr register.

For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...

This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.

Detected this issue with automated tbot tests on am335x
based shc board.

The error does not popup, if you type commands. You need
to copy&paste a long command to u-boots commandshell
(or send a long command with tbot)

Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.c

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Thu, 19 Jan 2017 17:22:23 +0000 (12:22 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoarmv8: ls1012a: define esdhc_status_fixup for RDB board
Yangbo Lu [Tue, 17 Jan 2017 02:43:56 +0000 (10:43 +0800)]
armv8: ls1012a: define esdhc_status_fixup for RDB board

On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2
signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select
eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command
inhibit bits of eSDHC2_PRSSTAT register will never release. This would
cause below continious error messages in linux since it uses polling
mode to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for RDB to disable
SDHC2 status if no SDIO wifi or eMMC is selected.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1012a: define esdhc_status_fixup for QDS board
Yangbo Lu [Tue, 17 Jan 2017 02:43:55 +0000 (10:43 +0800)]
armv8: ls1012a: define esdhc_status_fixup for QDS board

The LS1012AQDS board has a hardware issue. When there is no eMMC
adapter card inserted in SDHC2 adapter slot, the command inhibit
bits of eSDHC2_PRSSTAT register will never release. This would cause
below continious error messages in linux since it uses polling mode
to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for QDS to
disable SDHC2 status if no eMMC adapter card is detected.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agommc: fsl_esdhc: move 'status' property fixup into a weak function
Yangbo Lu [Tue, 17 Jan 2017 02:43:54 +0000 (10:43 +0800)]
mmc: fsl_esdhc: move 'status' property fixup into a weak function

Move fdt fixup of 'status' property into a weak function. This allows
board to define 'status' fdt fixup by themselves.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agofsl PPA: enable PPA for ls1043ardb and ls1046ardb
Hou Zhiqiang [Mon, 16 Jan 2017 09:31:50 +0000 (17:31 +0800)]
fsl PPA: enable PPA for ls1043ardb and ls1046ardb

Enable PPA for ls1043ardb NOR boot and ls1046ardb QSPI boot.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agokconfig: fsl PPA: move CONFIG_* to Kconfig
Hou Zhiqiang [Mon, 16 Jan 2017 09:31:49 +0000 (17:31 +0800)]
kconfig: fsl PPA: move CONFIG_* to Kconfig

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI
Hou Zhiqiang [Mon, 16 Jan 2017 09:31:48 +0000 (17:31 +0800)]
ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI

Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to
Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agokconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig
Hou Zhiqiang [Mon, 16 Jan 2017 09:31:47 +0000 (17:31 +0800)]
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York S: clean up scripts/config_whitelist.txt]
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: aarch64: Fix the warning about x1-x3 nonzero issue
Alison Wang [Tue, 17 Jan 2017 01:39:17 +0000 (09:39 +0800)]
armv8: aarch64: Fix the warning about x1-x3 nonzero issue

For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node
Wenbin Song [Tue, 17 Jan 2017 10:31:16 +0000 (18:31 +0800)]
armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if
rev1.1 silicon used, need to fixup the MSI node to match it.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/ls1043a: fixup GIC offset for ls1043a rev1
Wenbin Song [Tue, 17 Jan 2017 10:31:15 +0000 (18:31 +0800)]
armv8/ls1043a: fixup GIC offset for ls1043a rev1

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.

The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.

Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.

The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-lsch3: enable snoopable sata read and write
Tang Yuantian [Thu, 1 Dec 2016 09:06:58 +0000 (17:06 +0800)]
armv8: fsl-lsch3: enable snoopable sata read and write

By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions.  This patch enable it in the
sata axicc register.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agols1046ardb: Add support power initialization
Hou Zhiqiang [Fri, 9 Dec 2016 08:09:01 +0000 (16:09 +0800)]
ls1046ardb: Add support power initialization

Add the chip power supply voltage initialization on LS1046ARDB.
Add function power_init_board(), and it will initialize the
PMIC and call the chip power initialization function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/fsl_lsch2: Add chip power supply voltage setup
Hou Zhiqiang [Fri, 9 Dec 2016 08:09:00 +0000 (16:09 +0800)]
armv8/fsl_lsch2: Add chip power supply voltage setup

Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.

Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agols1046ardb: cpld: add API for selecting core volt
Hou Zhiqiang [Fri, 9 Dec 2016 08:08:59 +0000 (16:08 +0800)]
ls1046ardb: cpld: add API for selecting core volt

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agopmic: pmic_mc34vr500: Add APIs to set/get SWx volt
Hou Zhiqiang [Fri, 9 Dec 2016 08:08:58 +0000 (16:08 +0800)]
pmic: pmic_mc34vr500: Add APIs to set/get SWx volt

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agopmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmic
Hou Zhiqiang [Fri, 9 Dec 2016 08:08:57 +0000 (16:08 +0800)]
pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmic

This patch adds a simple pmic driver for the mc34vr500 pmic which
is used in conjunction with the fsl T1 and LS1 series SoC.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-layerscape: Fix SECURE_BOOT config
York Sun [Wed, 4 Jan 2017 18:32:08 +0000 (10:32 -0800)]
armv8: fsl-layerscape: Fix SECURE_BOOT config

Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoLS2080A: Add validation of MC & DPC images.
Udit Agarwal [Fri, 6 Jan 2017 10:28:57 +0000 (15:58 +0530)]
LS2080A: Add validation of MC & DPC images.

Add secure boot validation of MC, DPC images using
esbc_validate command.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoSECURE_BOOT: Update bootscript and its hdr addresses
Udit Agarwal [Fri, 6 Jan 2017 10:28:56 +0000 (15:58 +0530)]
SECURE_BOOT: Update bootscript and its hdr addresses

Update bootscript and its hdr addresses for Layerscape Chasis 3
based platforms instead of individual SoCs.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoconfigs: ls1012a: enable driver model for eSDHC
Yangbo Lu [Wed, 7 Dec 2016 03:54:33 +0000 (11:54 +0800)]
configs: ls1012a: enable driver model for eSDHC

Enable driver model for eSDHC on ls1012a rdb and qds boards.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1012a: add eSDHC nodes
Yangbo Lu [Wed, 7 Dec 2016 03:54:32 +0000 (11:54 +0800)]
armv8: ls1012a: add eSDHC nodes

This patch is to add eSDHC nodes for ls1012a.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agommc: fsl_esdhc: add 'fsl, esdhc' into of_match table
Yangbo Lu [Wed, 7 Dec 2016 03:54:31 +0000 (11:54 +0800)]
mmc: fsl_esdhc: add 'fsl, esdhc' into of_match table

This patch is to add 'fsl,esdhc' into of_match table to support
driver model for QorIQ eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agommc: fsl_esdhc: make GPIO support optional
Yangbo Lu [Wed, 7 Dec 2016 03:54:30 +0000 (11:54 +0800)]
mmc: fsl_esdhc: make GPIO support optional

There would be compiling error as below when enable driver model for esdhc.
undefined reference to `dm_gpio_get_value'
undefined reference to `gpio_request_by_name_nodev'
This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
all boards of QorIQ platform don't need it and they just check register for
CD/WP status, only some boards of i.MX platform require this.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/fsl-lsch3: consolidate the clock system initialization
Hou Zhiqiang [Tue, 10 Jan 2017 08:44:16 +0000 (16:44 +0800)]
armv8/fsl-lsch3: consolidate the clock system initialization

This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/fsl-lsch2: refactor the clock system initialization
Hou Zhiqiang [Tue, 10 Jan 2017 08:44:15 +0000 (16:44 +0800)]
armv8/fsl-lsch2: refactor the clock system initialization

Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.

This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8/fsl-layerscape: Enable data coherency between cores in cluster
Hou Zhiqiang [Fri, 6 Jan 2017 09:41:11 +0000 (17:41 +0800)]
ARMv8/fsl-layerscape: Enable data coherency between cores in cluster

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: Enable CPUECTLR.SMPEN for coherency
Mingkai Hu [Fri, 6 Jan 2017 09:41:10 +0000 (17:41 +0800)]
armv8: Enable CPUECTLR.SMPEN for coherency

For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: layerscape: Enable UUID & GPT partition for NXP's ARM SoC
Prabhakar Kushwaha [Mon, 26 Dec 2016 06:45:08 +0000 (12:15 +0530)]
arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoC

Enable UUID and GPT partition support for NXP's ARM based SoCs
i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A.

Also enable DOS partition for LS1012AFRDM boards.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1012: Enable CONFIG_DM_USB in defconfigs
Tang Yuantian [Tue, 27 Dec 2016 02:24:45 +0000 (10:24 +0800)]
armv8: ls1012: Enable CONFIG_DM_USB in defconfigs

Enables driver model flag CONFIG_DM_USB for LS1012A platform
in defconfigs.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1012: added usb nodes in dts
Tang Yuantian [Tue, 27 Dec 2016 02:24:44 +0000 (10:24 +0800)]
armv8: ls1012: added usb nodes in dts

The LS1012A processor has two integrated USB controllers.
One is USB2.0 controller, the other is USB3.0 controller that
allow direct connection to the USB ports with appropriate
protection circuitry and power supplies.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/fsl_lsch2: Add the OCRAM initialization
Hou Zhiqiang [Fri, 16 Dec 2016 09:15:46 +0000 (17:15 +0800)]
armv8/fsl_lsch2: Add the OCRAM initialization

Clear the content to zero and the ECC error bit of OCRAM1/2.

The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoARMv8/fsl-layerscape: Correct the OCRAM size
Hou Zhiqiang [Fri, 16 Dec 2016 09:15:45 +0000 (17:15 +0800)]
ARMv8/fsl-layerscape: Correct the OCRAM size

The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agokconfig: move FSL_PCIE_COMPAT to platform Kconfig
Hou Zhiqiang [Tue, 13 Dec 2016 06:54:24 +0000 (14:54 +0800)]
kconfig: move FSL_PCIE_COMPAT to platform Kconfig

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agopci: layerscape: remove unnecessary legacy code
Minghuan Lian [Tue, 13 Dec 2016 06:54:23 +0000 (14:54 +0800)]
pci: layerscape: remove unnecessary legacy code

All Layerscape SoCs have supported new PCIe driver based on DM.
The lagecy PCIe driver code is unused and can be removed.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls2080a: Enable PCIe in defconfigs
Minghuan Lian [Tue, 13 Dec 2016 06:54:22 +0000 (14:54 +0800)]
armv8: ls2080a: Enable PCIe in defconfigs

The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1046a: Enable PCIe and E1000 in defconfigs
Minghuan Lian [Tue, 13 Dec 2016 06:54:21 +0000 (14:54 +0800)]
armv8: ls1046a: Enable PCIe and E1000 in defconfigs

The patch enables PCIe and E1000 in ls1046a related defconfigs.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043a: Enable PCIe and E1000 in defconfigs
Minghuan Lian [Tue, 13 Dec 2016 06:54:20 +0000 (14:54 +0800)]
armv8: ls1043a: Enable PCIe and E1000 in defconfigs

The patch enables PCIe and E1000 in ls1043a defconfigs and
removes unused PCIe related macro defines.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: ls1012a: Enable PCIe and E1000 in defconfigs
Minghuan Lian [Tue, 13 Dec 2016 06:54:19 +0000 (14:54 +0800)]
arm: ls1012a: Enable PCIe and E1000 in defconfigs

The patch enables PCIe and E1000 in ls1012a defconfigs and
removes unused PCIe related macro defines

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: ls1021a: Enable PCIe in defconfigs
Minghuan Lian [Tue, 13 Dec 2016 06:54:18 +0000 (14:54 +0800)]
arm: ls1021a: Enable PCIe in defconfigs

The patch enables PCIe in ls1021a defconfigs and
removes unused PCIe related macro defines.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agopci: layerscape: add pci driver based on DM
Minghuan Lian [Tue, 13 Dec 2016 06:54:17 +0000 (14:54 +0800)]
pci: layerscape: add pci driver based on DM

There are more than five kinds of Layerscape SoCs. unfortunately,
PCIe controller of each SoC is a little bit different. In order
to avoid too many macro definitions, the patch addes a new
implementation of PCIe driver based on DM. PCIe dts node is
used to describe the difference.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agopci: layerscape: move kernel DT fixup to a separate file
Hou Zhiqiang [Tue, 13 Dec 2016 06:54:16 +0000 (14:54 +0800)]
pci: layerscape: move kernel DT fixup to a separate file

To make the layerscape pcie driver clear, move the kernel DT fixup
code from pcie_layerscape.c to pcie_layerscape_fixup.c.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls2080a: add PCIe dts node
Minghuan Lian [Tue, 13 Dec 2016 06:54:15 +0000 (14:54 +0800)]
armv8: ls2080a: add PCIe dts node

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1046a: add PCIe dts node
Minghuan Lian [Tue, 13 Dec 2016 06:54:14 +0000 (14:54 +0800)]
armv8: ls1046a: add PCIe dts node

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043a: add PCIe dts node
Minghuan Lian [Tue, 13 Dec 2016 06:54:13 +0000 (14:54 +0800)]
armv8: ls1043a: add PCIe dts node

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: ls1012a: add PCIe dts node
Minghuan Lian [Tue, 13 Dec 2016 06:54:12 +0000 (14:54 +0800)]
arm: ls1012a: add PCIe dts node

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: ls1021a: add PCIe dts node
Minghuan Lian [Tue, 13 Dec 2016 06:54:11 +0000 (14:54 +0800)]
arm: ls1021a: add PCIe dts node

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agodm: pci: remove pci_bus_to_hose(0) calling
Minghuan Lian [Tue, 13 Dec 2016 06:54:10 +0000 (14:54 +0800)]
dm: pci: remove pci_bus_to_hose(0) calling

There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get
the first PCIe controller for the PCIe device connected other
controllers. We just remove this calling because hose always point
the correct PCIe controller.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agodm: pci: return the real controller in pci_bus_to_hose()
Minghuan Lian [Tue, 13 Dec 2016 06:54:09 +0000 (14:54 +0800)]
dm: pci: return the real controller in pci_bus_to_hose()

for the legacy PCI driver, the function pci_bus_to_hose() returns
the real PCIe controller. To keep consistency, this function is
changed to return the PCIe controller pointer of the root bus
instead of the current PCIe bus.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoconfigs: ls1021a: enable DT and DM support
Hou Zhiqiang [Tue, 13 Dec 2016 06:54:08 +0000 (14:54 +0800)]
configs: ls1021a: enable DT and DM support

Enable DT to support Driver Model.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/layerscape: remove unnecessary function declares
Minghuan Lian [Tue, 15 Nov 2016 09:35:24 +0000 (17:35 +0800)]
armv8/layerscape: remove unnecessary function declares

For the function alloc_stream_ids() append_mmu_masters() and
fdt_fixup_smmu_pcie() there are no related definitions and they
are never called. So the patch removes the unnecessary declares.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20
Priyanka Jain [Wed, 9 Nov 2016 06:57:54 +0000 (12:27 +0530)]
armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20

It is recommended to set forced-order mode in RNI-6,
RNI-20 for performance optimization in LS2088A.

Both LS2080A, LS2088A families has CONFIG_LS2080A define.
As above update is required only for LS2088A, skip this
for LS2080A SoC family.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agofsl/usb: enable usb feature for ls1046ardb
jerry.huang@nxp.com [Tue, 15 Nov 2016 02:47:52 +0000 (10:47 +0800)]
fsl/usb: enable usb feature for ls1046ardb

Enable usb feature for ls1046ardb

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-i2c
Tom Rini [Wed, 18 Jan 2017 12:21:33 +0000 (07:21 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c

7 years agoMerge git://git.denx.de/u-boot-samsung
Tom Rini [Wed, 18 Jan 2017 12:21:12 +0000 (07:21 -0500)]
Merge git://git.denx.de/u-boot-samsung

7 years agoi2c: i2c-cdns: No need for dedicated probe function
Moritz Fischer [Mon, 16 Jan 2017 17:50:47 +0000 (09:50 -0800)]
i2c: i2c-cdns: No need for dedicated probe function

The generic probe code in dm works, so get rid of the leftover cruft.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
7 years agoi2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0
Moritz Fischer [Mon, 16 Jan 2017 17:50:46 +0000 (09:50 -0800)]
i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

Revision 1.0 of this IP has a quirk where if during a long read transfer
the transfer_size register will go to 0, the master will send a NACK to
the slave prematurely.
The way to work around this is to reprogram the transfer_size register
mid-transfer when the only the receive fifo is known full, i.e. the I2C
bus is known non-active.
The workaround is based on the implementation in the linux-kernel.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
7 years agoi2c: i2c-cdns: Reorder timeout loop for interrupt waiting
Moritz Fischer [Mon, 16 Jan 2017 17:50:45 +0000 (09:50 -0800)]
i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

Reorder the timeout loop such that we first check if the
condition is already true, and then call udelay() so if
the condition is already true, break early.

Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
7 years agoi2c: i2c-cdns: Detect unsupported sequences for rev 1.0
Moritz Fischer [Mon, 16 Jan 2017 17:50:44 +0000 (09:50 -0800)]
i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

Revision 1.0 of this IP has a couple of issues, such as not supporting
repeated start conditions for read transfers.

So scan through the list of i2c messages for these conditions
and report an error if they are attempted.

This has been fixed for revision 1.4 of the IP, so only report the error
when the IP can really not do it.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
7 years agoi2c: mux: Allow muxes to work as children of i2c bus without i2c-parent
Moritz Fischer [Mon, 16 Jan 2017 17:46:06 +0000 (09:46 -0800)]
i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent

For mux check if the parent is already a device of UCLASS_I2C and if yes
just use that. Otherwise see if someone specified an i2c-parent phandle.
This mimics the behavior found in the Kernel, as it removes the
requirement to explicitly specify a i2c-parent phandle.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
7 years agoexynos: video: Enable stdout env var backward compatibility for LCD
Javier Martinez Canillas [Mon, 16 Jan 2017 17:15:23 +0000 (14:15 -0300)]
exynos: video: Enable stdout env var backward compatibility for LCD

Commit bb5930d5c97f ("exynos: video: Convert several boards to driver
model for video") converted the Exynos Chromebooks machines to use DM
for video, but this breaks backward compatibility with the stdout env
var since now stdout is expected to be "vidconsole" instead of "lcd".

This causes display to not work when updating u-boot on these boards
if the old stdout env var is used. Since these are consumer devices,
there's no easy way to have a serial console so users may be confused
thinking that u-boot failed to boot, or in the best case will need to
update the stdout env var blindly to make the display to work again.

There's a CONFIG_VIDCONSOLE_AS_LCD config option to workaround this,
so enable it in the Chromebooks' default configuration files to allow
users to change their stdout env var before the workaround is removed.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoexynos: Enable XHCI on exynos5250 boards
Sjoerd Simons [Tue, 10 Jan 2017 13:36:17 +0000 (14:36 +0100)]
exynos: Enable XHCI on exynos5250 boards

Once upon a time u-boot didn't support building with two usb host
controller types, these days it does. Enable XHCI in addition to the
existing EHCI support so user can plug usb devices in all available
ports regardless of the controller type.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoexynos5: Don't potentially undervoltage the CPU
Sjoerd Simons [Tue, 10 Jan 2017 11:28:57 +0000 (12:28 +0100)]
exynos5: Don't potentially undervoltage the CPU

For snow when chainloading u-boot the CPU seems to be running at full
speed. The lower CPU voltage seems to be ok for u-boot, but when booting
linux (bringing up all cores) I'm seeing random crashes.

Bump the voltage up to a level that's safe for all cpu frequencies.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoboard: samsung: universal_c210: remove the codes relevant to soft_i2c
Jaehoon Chung [Mon, 9 Jan 2017 05:47:53 +0000 (14:47 +0900)]
board: samsung: universal_c210: remove the codes relevant to soft_i2c

Removes the codes of soft_i2c.
There is no usasge for universal_c210, also didn't define
CONFIG_SOFT_I2C_GPIO_SCL.
This code seems a dead code.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoi2c: Kconfig: Add SYS_I2C_S3C24X0 entry
Jaehoon Chung [Mon, 9 Jan 2017 05:47:52 +0000 (14:47 +0900)]
i2c: Kconfig: Add SYS_I2C_S3C24X0 entry

Adding Kconfig for SYS_I2C_S3C24X0.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoi2c: s3c24x0: fix the compiler error for exynos4
Jaehoon Chung [Mon, 9 Jan 2017 05:47:51 +0000 (14:47 +0900)]
i2c: s3c24x0: fix the compiler error for exynos4

If CONFIG_SYS_I2C_S3C24X0_SLAVE isn't defined, then complie error should
be occurred.
This patch is for preventing it.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoboard: samsung: universal_210: use the driver model for max8998
Jaehoon Chung [Mon, 9 Jan 2017 05:47:50 +0000 (14:47 +0900)]
board: samsung: universal_210: use the driver model for max8998

Revmoe the "ifndef CONFIG_DM_I2C".
Intead, use the driver model for max8998.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoconfigs: s5pc210_universal: enable the DM_PMIC and MAX8998
Jaehoon Chung [Mon, 9 Jan 2017 05:47:49 +0000 (14:47 +0900)]
configs: s5pc210_universal: enable the DM_PMIC and MAX8998

Enable the CONFIG_DM_PMIC and CONFIG_DM_PMIC_MAX8998.
s5pc210_universal board is using max8998 pmic.
To use the i2c/pmic driver model, enable these configurations.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoARM: dts: exnyos4210-universl_c210: add i2c_5 and pmic nodes
Jaehoon Chung [Mon, 9 Jan 2017 05:47:48 +0000 (14:47 +0900)]
ARM: dts: exnyos4210-universl_c210: add i2c_5 and pmic nodes

Add the i2c_5 node and pmic as its child node.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoARM: dts: exynos4: use the node's name for i2c
Jaehoon Chung [Mon, 9 Jan 2017 05:47:47 +0000 (14:47 +0900)]
ARM: dts: exynos4: use the node's name for i2c

Use the node's name for i2c.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoboard: samsung: goni: fix the pmic's name for getting
Jaehoon Chung [Thu, 5 Jan 2017 07:55:14 +0000 (16:55 +0900)]
board: samsung: goni: fix the pmic's name for getting

For Getting from uclass, use the "max8998-pmic" as name.
It also needs to change the dt-node's name as "max8998-pmic".
Otherwise, it doesn't find the pmic device.
Because it's only searching for 'max8998_pmic'.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-uniphier
Tom Rini [Tue, 17 Jan 2017 16:39:43 +0000 (11:39 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier

  - Enable eMMC driver for LD11/LD20 SoCs
  - Refactoring of SoC init code
  - Bug fix of pinctrl driver

7 years agopinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20
Masahiro Yamada [Tue, 17 Jan 2017 12:07:35 +0000 (21:07 +0900)]
pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20

Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins.

Fixes: fc9da85c6059 ("pinctrl: uniphier: add Ethernet pin-mux settings")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: move SBC and Support Card init code to U-Boot proper
Masahiro Yamada [Sun, 15 Jan 2017 05:59:10 +0000 (14:59 +0900)]
ARM: uniphier: move SBC and Support Card init code to U-Boot proper

Initialize SBC and Support Card in U-Boot proper instead of SPL.

We may run different firmware (ex. ARM Trusted Firmware) before
U-Boot, and basic SoC initialization may be done there.  In that
case, SPL may not be used.

The motivation for preparing SBC and Support Card in SPL was to use
LED for early debugging, but this is not mandatory to boot SoCs.
With this commit, LED will be unavailable in SPL, but we can use a
debug serial instead.  So, this change will not be a big deal.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: refactor spl_init_board()
Masahiro Yamada [Sun, 15 Jan 2017 05:59:09 +0000 (14:59 +0900)]
ARM: uniphier: refactor spl_init_board()

Merge init-*.c into a single file using a table of callbacks because
the initialization flow is almost common among SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>