CVE: nfs: fix stack-based buffer overflow in some nfs_handler reply helper functions

This patch adds a check to nfs_handler to fix buffer overflow for CVE-2019-14197,
CVE-2019-14200, CVE-2019-14201, CVE-2019-14202, CVE-2019-14203 and CVE-2019-14204.

Signed-off-by: Cheng Liu <liucheng32@huawei.com>
Reported-by: Fermín Serna <fermin@semmle.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

CVE: net: fix unbounded memcpy of UDP packet

This patch adds a check to udp_len to fix unbounded memcpy for
CVE-2019-14192, CVE-2019-14193 and CVE-2019-14199.

Signed-off-by: Cheng Liu <liucheng32@huawei.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reported-by: Fermín Serna <fermin@semmle.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: make net_random_ethaddr() more random

The net_random_ethaddr() tries to get some entropy from different
startup times of a board. The seed is initialized with get_timer() which
has only a granularity of milliseconds. We can do better if we use
get_ticks() which returns the raw timer ticks. Using this we have a
higher chance of getting different values at startup.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: macb: Fix rx buffer cache handling

With commit c6d07bf440bc ("net/macb: increase RX buffer size for GEM")
ethernet support does not work any more with d-cache enabled on the
AT91SAM. The reason is, that MACB_RX_BUFFER_SIZE was changed from 4096
to 128 but this change was not refected in the rx_buffer flush and
invalidate functions, as these also use this macro.

This patch now fixes this by calculating the rx buffer size correctly
again in those functions. With this change, ethernet works again
reliably on my AT91SAM board.

Signed-off-by: Stefan Roese <sr@denx.de>
Fixes: c6d07bf440bc ("net/macb: increase RX buffer size for GEM")
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: designware: drop compatible altr, socfpga-stmmac

The same compatible = "altr,socfpga-stmmac" appears in both
drivers/net/designware.c and drivers/net/dwmac_socfgpa.c,
creating ambiguity in which driver will be bound.

For Intel/Altera SoC devices, dwmac_socfpga.c is the correct driver.
So drop the compatible string from designware.c.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Revert "net: macb: Fixed reading MII_LPA register"

This reverts commit 1b0c9914cc75d1570359181ebd493cd5746cb0ed.

Commit 1b0c9914cc75 ("net: macb: Fixed reading MII_LPA register")
causes 100Mbps does not work any more with SiFive FU540 GEM on the
HiFive Unleashed board. Revert it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

network: set timeline for CONFIG_DM_ETH conversion

The driver model has been supported for network drivers since 2015. It is
time to convert the remaining boards. Set July 2020 as a timeline.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers: net: fsl_enet_mdio: fix missing terminator in PCI ID array

It was missing in the original submission and not having it in place causes
issues with probing of PCI devices.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: dwc_et_qos: update weak function board_interface_eth_init

Align the board and driver prototype for board_interface_eth_init
to avoid execution issue (the interface_type parameter is defined
as int or phy_interface_t).

To have a generic weak function (it should be reused by other driver)
I change the prototype to use directly udevice.

This prototype is added in netdev.h to allow compilation check
and avoid warning when compiling with W=1 on file
board/st/stm32mp1/stm32mp1.c

warning: no previous prototype for 'board_interface_eth_init'\
[-Wmissing-prototypes]
     int board_interface_eth_init(int interface_type, ....
         ^~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: dwc_eth_qos: Change eqos_ops function to static

This patch solves many warnings when compiling with W=1:
warning: no previous prototype for '....' [-Wmissing-prototypes]

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers: net: pfe_eth: undefined return value

Do not use random value from stack as return value of pfe_phy_write().

Indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

test: dm_mdio: avoid out of bounds access

SANDBOX_PHY_REG_CNT is not an allowable index for the array
u16 reg[SANDBOX_PHY_REG_CNT].

Identified by cppcheck.

Fixes: b47edf8069cc ("test: dm_mdio: add a 2nd register to the emulated PHY")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: mvpp2: support setting hardware addresses from ethernet core

mvpp2 already has support for setting MAC addresses but this
functionality was not exposed to the ethernet core. This commit exposes
this functionality so that MAC address assignments stored in U-Boot's
environment are correctly applied before Linux boots.

Signed-off-by: Matt Pelland <mpelland@starry.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

arm: dts: Set custom names for cp110 master/slave MDIO buses

Implicitly Marvell MDIO driver uses DT node names for devices, but in this
case that is not unique.  Set MDIO device names for master/slave to
cpm/cps.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers: net: add marvell MDIO driver

This patch adds a separate driver for the MDIO interface of the
Marvell Ethernet controllers based on driver model. There are two
reasons to have a separate driver rather than including it inside
the MAC driver itself:
  *) The MDIO interface is shared by all Ethernet ports, so a driver
     must guarantee non-concurrent accesses to this MDIO interface. The
     most logical way is to have a separate driver that handles this
     single MDIO interface, used by all Ethernet ports.
  *) The MDIO interface is the same between the existing mv643xx_eth
     driver and the new mvneta/mvpp2 driver. Even though it is for now
     only used by the mvneta/mvpp2 driver, it will in the future be
     used by the mv643xx_eth driver as well.

This driver supports SMI IEEE for 802.3 Clause 22 and XSMI for IEEE
802.3 Clause 45.

This patch also adds device tree binding for marvell MDIO driver.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

doc: bindings: add mdio.txt describing generic MDIO properties

Adds a binding document for mdio.  A notable deviation from corresponding
Linux binding is the introduction of device-name optional property, which
can be used to name MDIO buses.  Two reset optional properties described
by Linux binding are also not present as they don't seem to be used in
U-Boot at this time.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

net: mdio-uclass: name MDIO according to device-name property if preset

Use the optional property device-name to name the MDIO bus.  This works
around limitations with using the DT node name on devices such as
Armada-8040, which integrates two cp100 cores, both featuring MDIOs at the
same relative offsets and with the same DT node names.
The concept was originally proposed by Marvell as a custom property called
mdio-name specific to Marvell driver.  This patch uses the more generic
property device-name and moves this into MDIO class code so other can use
it as well.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

configs: sandbox: enable PCAP capture cmd

Enable CONFIG_CMD_PCAP for testing PCAP capture.

Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

doc: pcap: add pcap cmd documentation

Add documentation for new "pcap" command.

Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: introduce packet capture support

Add support for capturing ethernet packets and storing
them in memory in PCAP(2.4) format, later to be analyzed by
any PCAP viewer software (IE. Wireshark)

This feature greatly assist debugging network issues such
as detecting dropped packets, packet corruption etc.

Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Tested-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers/fsl-mc: Create Kconfig file to manage driver specific configs better

Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs
from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers: net: driver for MDIO muxes controlled over I2C

This driver is used for MDIO muxes driven over I2C.  This is currently
used on Freescale LS1028A QDS board, on which the physical MDIO MUX is
controlled by an on-board FPGA which in turn is configured through I2C.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Revert "drivers: net: driver for MDIO muxes controlled over I2C"

This reverts commit d9a9174fa5687521035b2ec82cce86cdcf4f36e6.

net: mdio: Clarify code flow Covarity 244085 & 244090

Document that the lack of breaks is intentional.

Series-to: u-boot
Series-cc: ti

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

net: Fix Covarity Defect 244093

Don't allow unterminated strings

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

Merge tag 'arc-for-2019.10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc

These are some very late changes mostly required to get 64-bit
division working on ARC boards.

For that we had to import missing parts of libgcc and add compiler
flags to EMSDP which otherwise used very simple profile for compliation.

And while at it another fix for EM SDP initialization is inluded as well.

arc: emsdp: Add more platform-specific compiler options

Even though EM SDP is FPGA-based board and different FPGA
images (known as .bit-files) are awailable for the board still
there's a common subset of options we may rely on for all configs.

These are:
 * Normalizer
 * Swap instructions
 * Simple multiplier
 * Barrel-shifter
 * Floating-point unit
 * Shorter instructions (code density)

This among other improvements allows to compile code with
64-bit divisions, see [1].

[1] https://patchwork.ozlabs.org/patch/1156541/

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Kever Yang <kever.yang@rock-chips.com>

arc: libgcc: Import __udivdi3 & __udivmoddi4 to allow 64-bit division

As reported by Kever here [1] we were unable to compile 64-bit division
code due to missing definition of __udivdi3().

Import its implementation and __udivmoddi4() as its direct dependency
from today's libgcc [2].

[1] https://patchwork.ozlabs.org/patch/1146845/
[2] https://github.com/gcc-mirror/gcc/commit/5d8723600bc0eed41226b5a6785bc02a053b45d5

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Kever Yang <kever.yang@rock-chips.com>

arc: emsdp: Add initialization of PSRAM

If the "Page Mode" is not enabled on the device,
read operations from PSRAM may result in incorrect data.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Merge tag 'for-v2019.10-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c

i2c bugfixes for 2019.10 take 2
- i2c: mxc: add CONFIG_CLK support
  If CONFIG_CLK is enabled use clk framework for clock settings.

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

- Skip unavailable hart in the get_count().
- fu540 set serial env from otp.
- fu540 add mmc0 as a boot target device.
- Update fix_rela_dyn and add absolute reloc addend.
- Andestech PLIC driver will skip unavailable hart.
- Support Andestech V5L2 cache driver.

riscv: cache: use CCTL to flush d-cache

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: dts: move out AE350 L2 node from cpus node

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: cache: Flush L2 cache before jump to linux

Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: ax25: add imply v5l2 cache controller

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: ae350: use the v5l2 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: cache: add v5l2 cache controller driver

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: cache: Add enable and disable ops for sandbox and test

Add cache enable and disable ops for test coverage.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: cache: Add enable and disable ops for cache uclass

Add cache enable/disable ops to the DM cache uclass driver

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: andes_plic: init plic by scanning each cpu node

Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().

This way can support to skip some harts which maybe marked as
unavailable, but the cpu node exists indeed.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: update fix_rela_dyn

The addend is now added for RELOC_TYPE relocs.  Also, changed the loop
structure so that all the R_RISCV_RELATIVE relocs are not required to
be at the beginning of the list.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>

riscv: tools: Handle addend to absolute reloc in prelink-riscv

Previously the handling of R_RISCV_32 and R_RISCV_64 would simply
insert the value of the symbol and ignore any addend.  However, there
exist relocs where the addend is non-zero:

0000000080250900 R_RISCV_64        efi_runtime_services+0x0000000000000068
0000000080250910 R_RISCV_64        efi_runtime_services+0x0000000000000038
0000000080250920 R_RISCV_64        efi_runtime_services+0x0000000000000018
0000000080250930 R_RISCV_64        efi_runtime_services+0x0000000000000020
0000000080250980 R_RISCV_64        efi_runtime_services+0x0000000000000048
0000000080250990 R_RISCV_64        efi_runtime_services+0x0000000000000050
00000000802509a0 R_RISCV_64        efi_runtime_services+0x0000000000000058
0000000080250940 R_RISCV_64        systab+0x0000000000000030
0000000080250950 R_RISCV_64        systab+0x0000000000000040
0000000080250960 R_RISCV_64        systab+0x0000000000000050
0000000080250970 R_RISCV_64        systab+0x0000000000000060

In these cases the addend needs to be added to the symbol value to get
the correct value for the reloc.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>

sifive-fu540: config: Add mmc0 as a boot target device

Add the mmc0 device as a BOOT_TARGET_DEVICES.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

riscv: sifive: fu540: set serial environment variable from otp

This patch sets the serial# environment variable by reading the
board serial number from the OTP memory region.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

riscv: cpu: Skip unavailable hart in the get_count() op

We should not count in hart that is marked as not available in the
device tree in riscv_cpu_get_count().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

i2c: mxc: add CONFIG_CLK support

When CONFIG_CLK enabled, use CLK UCLASS for clk related settings.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
hs: removed hunk in mxc_i2c_probe() as not longer in code

Merge branch 'master' of git://git.denx.de/u-boot-sh

- r8a66597 usb changes

Merge branch '2019-08-30-master-imports'

- Assorted bug fixes

Makefile: fix newline escaping for CONFIG_DEFAULT_ENV_FILE

I wanted this to be compatible with mkenvimage, including the ability
to embed newlines in variables by escaping them. But I failed to check
that it works more than once.

Fixes: f3d8f7dd73a (Allow providing default environment from file)
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>

Revert "vexpress64: fvp dram: add DRAM configuration"

This reverts commit fc04b923541d984b1544056fd3bfa8129d4e5aac where the
FVP DRAM configuration was added.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>

siemens: avoid out of bound access

char num[1];
sprintf(num, "%d", i);

leads to a buffer overrun.

Simplify the overly complex coding.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>

arm: omap2: am43xx: Enable CONFIG_DM_USB

Enable CONFIG_DM_USB to remove compile warning for
am43xx based targets:

===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>

Makefile: clean build generated SPL binary for TI AM65x

TI AM65x platforms (evm and HS) generate an SPL image
'tispl.bin*' and there is no rule for cleanup.
Added entry for cleanup in clean target.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>

configs: enable CONFIG_BLOCK_CACHE for mt7623n_bpir2

This patch enables CONFIG_BLOCK_CACHE for mt7623n_bpir2.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

mmc: invalidate block cache after hwpart switched successfully

eMMC device has multiple hw partitions both address from zero. However the
mmc driver lacks block cache invalidation for switch hwpart. This causes a
problem that data of current hw partition is cached before switching to
another hw partition. And the following read operation of the latter hw
partition will get wrong data when reading from the addresses that have
been cached previously.

To solve this problem, invalidate block cache after a successful
mmc_switch_part() operation.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Felix Brack <fb@ltec.ch>

Revert "blk: Invalidate block cache when switching hwpart"

This reverts commit 0ebe112d09b48230ba4be833cd3504b06997d9a4.

Most block devices have only one hwpart. Multiple hwparts only found used
by eMMC devices in u-boot. The mmc driver do blk_dselect_hwpart() at the
beginning of mmc_bread() which causes block cache being invalidated too
frequently and makes block cache useless.

So it's not a good idea to put blkcache_invalidate() in the common
functions. It should be called inside mmc_select_hwpart().

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Felix Brack <fb@ltec.ch>

board_f: fix noncached reservation calculation

The current code in reserve_noncached() has two issues:

1) The first update of gd->start_addr_sp always rounds down to a section
start. However, the equivalent calculation in cache.c:noncached_init()
always first rounds up to a section start, then subtracts a section size.
These two calculations differ if the initial value is already rounded to
section alignment.

2) The second update of gd->start_addr_sp subtracts exactly
CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in
cache.c:noncached_init() rounds the noncached size up to section
alignment before subtracting it. The two calculations differ if the
noncached region size is not a multiple of the MMU section size.

In practice, one/both of those issues causes a practical problem on
Jetson TX1; U-Boot triggers a synchronous abort during initialization,
likely due to overlapping use of some memory region.

This change fixes both these issues by duplicating the exact calculations
from noncached_init() into reserve_noncached().

However, this fix assumes that gd->start_addr_sp on entry to
reserve_noncached() exactly matches mem_malloc_start on entry to
noncached_init(). I haven't traced the code to see whether it absolutely
guarantees this in all (or indeed any!) cases. Consequently, I added some
comments in the hope that this condition will continue to be true.

Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area")
Cc: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

Merge tag 'efi-2019-10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for v2019.10-rc4

Enable the unit test for UEFI runtime service Exit() on x86_64.
Use as standalone UEFI binary for testing the handling of exceptions.

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB,
P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS

Merge tag 'u-boot-amlogic-20190828' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- add missing g12b clock driver compatible, fixing odroid-n2 usb support

efi_selftest: use standalone UEFI program for exception

To fully demonstrate crash outputs for UEFI images provide a standalone
UEFI application that tries to invoke an illegal opcode.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

efi_selftest: enable Exit() unit test on x86_64

Enable unit tests for StartImage() and Exit() unit tests on x86_64.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

configs: MPC8548CDS: Enable PCIe driver

Enable the DM PCIe driver in MPC8548CDS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

MPC8548: dts: Added PCIe DT node

MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add MPC8548 PCIe support

Add compatible string for MPC8548 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected

Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P5040DS: Enable PCIe driver

Enable the DM PCIe driver in P5040DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
eviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P5040: dts: Added PCIe DT nodes

P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P5040 PCIe support

Add compatible string for P5040 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P4080DS: Enable PCIe driver

Enable the DM PCIe driver in P4080DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P4080: dts: Added PCIe DT nodes

P4080 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P4080 PCIe support

Add compatible string for P4080 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P3041DS: Enable PCIe driver

Enable the DM PCIe driver in P3041DS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P3041: dts: Added PCIe DT nodes

P3041 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P3041 PCIe support

Add compatible string for P3041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P2041RDB: Enable PCIe driver

Enable the DM PCIe driver in P2041RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P2041: dts: Added PCIe DT nodes

P2041 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add P2041 PCIe support

Add compatible string for P2041 PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: p_corenet: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines for P2041RDB,
P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is
 not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P2020RDB: Enable PCIe driver

Enable the DM PCIe driver in P2020RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P2020: dts: Added PCIe DT nodes

P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: P1020RDB: Enable PCIe driver

Enable the DM PCIe driver in P1020RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
for P1020, P1021, P1024, P1025 and P2020 RDB boards.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

P1020: dts: Added PCIe DT nodes

P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs

Add compatible string for PCIe of P1020, P1021, P1024, P1025
and P2020 SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines for P1020,
P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI
is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: T1042D4RDB: Enable PCIe driver

Enable the DM PCIe driver in T1042D4RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

t104x: dts: Added PCIe DT nodes

T104x integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add T104x PCIe support

Add compatible string for T104x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T104xRDB: Compile legacy PCIe routines conditionally

Compile the legacy PCIe initialization routines only when
DM_PCI is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

configs: T1024RDB: Enable PCIe driver

Enable the DM PCIe driver in T1024RDB defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled

Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040

Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and
the PCIE4 related macros, as there are only 3 PCIe controllers
on T102x SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

t102x: dts: Added PCIe DT nodes

T102x integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

dm: pcie_fsl: Add T102x PCIe support

Add compatible string for T102x PCIe.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>