oweals/u-boot.git
8 years agorpi: add Raspberry Pi 3 board ID
Stephen Warren [Fri, 25 Mar 2016 04:15:18 +0000 (22:15 -0600)]
rpi: add Raspberry Pi 3 board ID

This allows U-Boot to known the name of the board.

The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3
in 32-bit mode /if/ you have configured the firmware to use the PL011 UART
as the console UART (the default is the mini UART). This requires two
things:
a) config.txt should contain dtoverlay=pi3-miniuart-bt
b) You should run the following to tell the VC FW to process DT when
booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD card
as the kernel image:

   path/to/kernel/scripts/mkknlimg --dtok u-boot.bin u-boot.bin.img

This works as of firmware.git commit 046effa13ebc "firmware: arm_loader:
emmc clock depends on core clock See:
https://github.com/raspberrypi/firmware/issues/572".

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agorpi: use constant "unknown board" DT filename
Stephen Warren [Fri, 25 Mar 2016 04:15:17 +0000 (22:15 -0600)]
rpi: use constant "unknown board" DT filename

To simplify support for new SoCs, just use a constant filename
for the unknown case. In practice this case shouldn't be hit anyway, so
the filename isn't relevant, and certainly doesn't need to differentiate
between SoCs. If a user has an as-yet-unknown board, they can override
this value in the environment anyway.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: bcm2835: move CONFIG_BCM283* to Kconfig
Stephen Warren [Fri, 25 Mar 2016 04:15:16 +0000 (22:15 -0600)]
ARM: bcm2835: move CONFIG_BCM283* to Kconfig

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agodoc: clarify openssl-based key and certificate generation process
Andreas Dannenberg [Wed, 23 Mar 2016 23:24:10 +0000 (18:24 -0500)]
doc: clarify openssl-based key and certificate generation process

Add some basic clarification that the dev.key file generated by OpenSSL
contains both the public and private key, and further highlight that
the certificate generated here contains the public key only.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
8 years agodoc: fix file extension for flattened image tree blob
Andreas Dannenberg [Wed, 23 Mar 2016 22:44:17 +0000 (17:44 -0500)]
doc: fix file extension for flattened image tree blob

Different sections in the document suggest flattened image tree blob
files have a file name extension of .itb. Fix the list of file extensions
to reflect that.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
8 years agoREADME: Specify the full path for README.displaying-bmps
Fabio Estevam [Wed, 23 Mar 2016 15:46:12 +0000 (12:46 -0300)]
README: Specify the full path for README.displaying-bmps

It is clearer to specify the full path to access the
doc/README.displaying-bmps file.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agoARM: keystone2: Add missing privilege ID settings
Nishanth Menon [Wed, 23 Mar 2016 15:14:19 +0000 (10:14 -0500)]
ARM: keystone2: Add missing privilege ID settings

Add missing Privilege ID settings for KS2 SoCs.

Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
  http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
  http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
  http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
  http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)

Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K    | K2L       | K2E       | K2G
-------+-----------+-----------+-----------+---------
0      | C66x 0    | C66x 0    | C66x 0    | C66x 0
1      | C66x 1    | C66x 1    | Reserved  | ARM
2      | C66x 2    | C66x 2    | Reserved  | ICSS0
3      | C66x 3    | C66x 3    | Reserved  | ICSS1
4      | C66x 4    | Reserved  | Reserved  | NETCP
5      | C66x 5    | Reserved  | Reserved  | CPIE
6      | C66x 6    | Reserved  | Reserved  | USB
7      | C66x 7    | Reserved  | Reserved  | Reserved
8      | ARM       | ARM       | ARM       | MLB
9      | NetCP     | NetCP     | NetCP     | PMMC
10     | QM_PDSP   | QM_PDSP   | QM_PDSP   | DSS
11     | PCIe_0    | PCIe_0    | PCIe_0    | MMC
12     | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13     | Reserved  | Reserved  | PCIe_1    | Reserved
14     | HyperLink | PCIe_1    | HyperLink | Reserved
15     | Reserved  | Reserved  | TSIP      | Reserved
-------+-----------+-----------+-----------+---------

NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.

Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).

By marking these segments as shared, we also ensure SoC wide coherency
is enabled.

Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
Nishanth Menon [Wed, 23 Mar 2016 15:14:18 +0000 (10:14 -0500)]
ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery

MSMC segment Privilege ID is not consistent accross the keystone2 SoCs.
As the first step to ensure complete SoC wide coherency setup, lets
refactor the macros to remove the #if-deffery around the code which
obfuscates which IDs are actually enabled for which SoC.

As a result of this change the PCIe configuration is moved after the
msmc configuration is complete, but that should ideally have no
functional impact.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agosmsc95xx: fix operation on 64-bit systems
Stephen Warren [Wed, 23 Mar 2016 04:28:16 +0000 (22:28 -0600)]
smsc95xx: fix operation on 64-bit systems

smsc95xx_read_reg() should calculate sizeof(*data) not sizeof(data) since
data is a pointer, and the value pointed at is being transferred over USB,
not the value of the pointer. This fixes operation of the driver in 64-bit
builds, such as the Raspberry Pi 3.

Reported-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoDrop command-processing code when CONFIG_CMDLINE is disabled
Simon Glass [Sat, 19 Mar 2016 08:18:38 +0000 (02:18 -0600)]
Drop command-processing code when CONFIG_CMDLINE is disabled

Command parsing and processing code is not needed when the command line is
disabled. Remove this code in that case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agofastboot: allow retrieving fastboot variables from env
Rob Herring [Thu, 17 Mar 2016 16:21:23 +0000 (17:21 +0100)]
fastboot: allow retrieving fastboot variables from env

Some boards need to expose device specific variable through fastboot
(to adpat the flashing script depending on hardware revision for
example).

Provide a way to expose custom fastboot variables. Note that all
variables meant to be exposed through fastboot should be be prefixed
with 'fastboot.', the variable should not exceed 32 bytes (including
the prefix and the trailing '\0') and the variable content should
fit in the response buffer (60 bytes excluding the 'OKAY' prefix and
the trailing '\0').

Signed-off-by: Rob Herring <rob.herring@linaro.org>
[Boris Brezillon: add a commit message]
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Steve Rae <srae@broadcom.com>
8 years agoarm: clang: Update support slightly
Tom Rini [Wed, 16 Mar 2016 23:55:55 +0000 (19:55 -0400)]
arm: clang: Update support slightly

- Move most of the flags required into LLVM_RELFLAGS to test at build
  time instead of requiring them to be passed in.
- Update doc/README.clang to reflect this
- Switch to rpi_2 as the example as it's closer to working out of the
  box than rpi is.

Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoMerge branch 'master' of http://git.denx.de/u-boot-sunxi
Tom Rini [Fri, 1 Apr 2016 12:17:55 +0000 (08:17 -0400)]
Merge branch 'master' of git.denx.de/u-boot-sunxi

8 years agosunxi: Reserve ATF memory space on A64
Alexander Graf [Wed, 30 Mar 2016 15:53:56 +0000 (17:53 +0200)]
sunxi: Reserve ATF memory space on A64

On the A64 we usually boot with ATF running in EL3. ATF as it is available
today resides in the first 16MB of RAM. So we should make sure we reserve
that space in our memory maps.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Add Pine64+ support
Siarhei Siamashka [Tue, 29 Mar 2016 15:29:11 +0000 (17:29 +0200)]
sunxi: Add Pine64+ support

The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of
running AArch64 code and thus is the first of its kind for the sunxi target.

This patch adds a defconfig and device tree chunks for it.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: Change patch description]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Add support for Allwinner A64 SoCs
Siarhei Siamashka [Tue, 29 Mar 2016 15:29:10 +0000 (17:29 +0200)]
sunxi: Add support for Allwinner A64 SoCs

The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.

Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Explicitly cast u32 pointer conversions
Alexander Graf [Tue, 29 Mar 2016 15:29:09 +0000 (17:29 +0200)]
sunxi: Explicitly cast u32 pointer conversions

Some parts of the sunxi code cast explicitly between u32 values and pointers.
This is not a problem in practice, because all 64bit SoCs today only use the
lower 32 bits for their phyical address space. But we need to make sure that
the compiler is sure this is not an accident as well.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Depend SPL configs on SUPPORT_SPL
Alexander Graf [Tue, 29 Mar 2016 15:29:07 +0000 (17:29 +0200)]
sunxi: Depend SPL configs on SUPPORT_SPL

We currently depend SPL config options on specific machine types which doesn't
scale. Fortunately there's already a kconfig variable that tells us whether we
want to build SPL code at all, so just depend them on this.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Move cpu independent code to mach directory
Alexander Graf [Tue, 29 Mar 2016 15:29:06 +0000 (17:29 +0200)]
sunxi: Move cpu independent code to mach directory

Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while
most of it is just generic code that could as well be used on an AArch64 SoC.

Move all files that are not really tied to armv7 into a new mach-sunxi
directory.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Enable USB nodes for H8Homlet v2
Chen-Yu Tsai [Tue, 29 Mar 2016 16:27:02 +0000 (00:27 +0800)]
sunxi: Enable USB nodes for H8Homlet v2

This provides the minimal changes to the H8Homlet v2 dts to enable USB
in U-boot. It is not what will be submitted to the kernel.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Enable USB on Cubietruck Plus
Chen-Yu Tsai [Tue, 29 Mar 2016 16:27:01 +0000 (00:27 +0800)]
sunxi: Enable USB on Cubietruck Plus

This provides the minimal changes to the Cubietruck Plus dts to enable USB
in U-boot. It is not what will be submitted to the kernel.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi
Chen-Yu Tsai [Tue, 29 Mar 2016 16:27:00 +0000 (00:27 +0800)]
sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi

This provides the minimal changes to the A83T dtsi to enable USB in
U-boot. It is not what will be submitted to the kernel.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:59 +0000 (00:26 +0800)]
sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig

The Cubietruck Plus uses all 3 USB controllers:

  - USB OTG functions are provided by the musb USB OTG controller
  - Onboard SATA is provied by a USB-SATA bridge connected to USB1
  - The USB host ports on the board are provided by an HSIC USB hub

FLDO1 is set to 1.2V for HSIC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: h8_homlet_v2: Enable USB Kconfig options in defconfig
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:58 +0000 (00:26 +0800)]
sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfig

The h8_homlet_v2 has 2 USB host ports, one connected to the OTG
controller, one connected to the EHCI/OHCI pair.

Also provide the card detect pin for MMC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoARM: uniphier: remove CONFIG_ARP_TIMEOUT define
Masahiro Yamada [Wed, 30 Mar 2016 11:45:19 +0000 (20:45 +0900)]
ARM: uniphier: remove CONFIG_ARP_TIMEOUT define

I no longer see the problem claimed in the comment block.  Rather,
the 0.5 msec timeout seems too short for some TFTP servers.

Drop the CONFIG_ARM_TIMEOUT to fall back to the 5 sec timeout.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agocosmetic: Fix typos "privide"
Masahiro Yamada [Wed, 30 Mar 2016 11:17:42 +0000 (20:17 +0900)]
cosmetic: Fix typos "privide"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: uniphier: rename function names ph1_* to uniphier_*
Masahiro Yamada [Wed, 30 Mar 2016 11:17:02 +0000 (20:17 +0900)]
ARM: uniphier: rename function names ph1_* to uniphier_*

Eliminate the "ph1"_ prefixes from function names because "uniphier_"
describes the SoC familiy better.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3
Masahiro Yamada [Wed, 30 Mar 2016 01:53:15 +0000 (10:53 +0900)]
ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: uniphier: enable eMMC on PH1-sLD3 reference board
Masahiro Yamada [Wed, 30 Mar 2016 01:52:49 +0000 (10:52 +0900)]
ARM: uniphier: enable eMMC on PH1-sLD3 reference board

On PH1-sLD3, eMMC and NAND are assigned to different I/O pins.
Both devices can be enabled at the same time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64
Masahiro Yamada [Tue, 29 Mar 2016 11:18:45 +0000 (20:18 +0900)]
ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64

Currently, these functions assume #address-cells and #size-cells are
both one.  Fix them to support 64bit DTB.

Also, I am fixing a buffer overrun bug while I am here.  The array
size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS.  The number of
iteration in the loop should be limited by that CONFIG.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: uniphier: drop unneeded defines related to legacy serial driver
Masahiro Yamada [Tue, 29 Mar 2016 11:12:22 +0000 (20:12 +0900)]
ARM: uniphier: drop unneeded defines related to legacy serial driver

These defined were used for pre-DM ns16550 serial driver.  They are
unneeded because UniPhier SoCs now use DM serial.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: dts: uniphier: add NAND pinmux node
Masahiro Yamada [Mon, 28 Mar 2016 12:41:15 +0000 (21:41 +0900)]
ARM: dts: uniphier: add NAND pinmux node

This will be used to set up pin-muxing for the NAND controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20
Masahiro Yamada [Mon, 28 Mar 2016 12:39:17 +0000 (21:39 +0900)]
ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20

Since no clock driver is implemented for peripherals in U-Boot yet,
this property is needed for the serial driver to set up the divisor
register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agopinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driver
Masahiro Yamada [Thu, 24 Mar 2016 13:32:47 +0000 (22:32 +0900)]
pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driver

The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20
(as far as used in boot-loader), so this commit makes the driver
shared between the two SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agopinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver
Masahiro Yamada [Thu, 24 Mar 2016 13:32:46 +0000 (22:32 +0900)]
pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver

Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agopinctrl: uniphier: support per-pin input enable for new SoCs
Masahiro Yamada [Thu, 24 Mar 2016 13:32:45 +0000 (22:32 +0900)]
pinctrl: uniphier: support per-pin input enable for new SoCs

Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin.  (While, existing ones only support it
per pin-group.)  This commit prepares the core part for that.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agopinctrl: uniphier: introduce capability flag
Masahiro Yamada [Thu, 24 Mar 2016 13:32:44 +0000 (22:32 +0900)]
pinctrl: uniphier: introduce capability flag

The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
because pinctrl drivers include really SoC-specific stuff.

This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones.  Having flags would be better than
adding new members every time a new SoC-specific capability comes up.

At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer.  For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agopinctrl: uniphier: use devm_get_addr() to get base address
Masahiro Yamada [Thu, 24 Mar 2016 13:32:43 +0000 (22:32 +0900)]
pinctrl: uniphier: use devm_get_addr() to get base address

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agommc: uniphier: use devm_get_addr() to get base address
Masahiro Yamada [Thu, 24 Mar 2016 13:32:42 +0000 (22:32 +0900)]
mmc: uniphier: use devm_get_addr() to get base address

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agogpio: uniphier: use devm_get_addr() to get base address
Masahiro Yamada [Thu, 24 Mar 2016 13:32:41 +0000 (22:32 +0900)]
gpio: uniphier: use devm_get_addr() to get base address

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoi2c: uniphier: use devm_get_addr() to get base address
Masahiro Yamada [Thu, 24 Mar 2016 13:32:40 +0000 (22:32 +0900)]
i2c: uniphier: use devm_get_addr() to get base address

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoclk: uniphier: use devm_get_addr() to get base address
Masahiro Yamada [Thu, 24 Mar 2016 13:32:39 +0000 (22:32 +0900)]
clk: uniphier: use devm_get_addr() to get base address

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoserial: uniphier: use devm_get_addr() to get base address
Masahiro Yamada [Thu, 24 Mar 2016 13:32:38 +0000 (22:32 +0900)]
serial: uniphier: use devm_get_addr() to get base address

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: uniphier: add sramupdate command
Masahiro Yamada [Thu, 24 Mar 2016 13:23:36 +0000 (22:23 +0900)]
ARM: uniphier: add sramupdate command

This command would be useful to update U-Boot images in SRAM.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoARM: uniphier: make u-boot-with-spl.bin really available
Masahiro Yamada [Thu, 24 Mar 2016 13:22:23 +0000 (22:22 +0900)]
ARM: uniphier: make u-boot-with-spl.bin really available

Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image")
claimed that u-boot-with-spl.bin would be useful in its commit log,
but it was not available because the commit missed to define
CONFIG_SPL_MAX_SIZE.  Without it, CONFIG_SPL_PAD_TO is not defined
either (see include/config_fallbacks.h).  So, the SPL image is not
padded correctly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agomtd: nand: denali: max_banks calculation changed in revision 5.1
Graham Moore [Thu, 24 Mar 2016 13:14:35 +0000 (22:14 +0900)]
mtd: nand: denali: max_banks calculation changed in revision 5.1

Read Denali hardware revision number and use it to
calculate max_banks,  The encoding of max_banks changed
in Denali revision 5.1.

[ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ]

Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
[Brian: parentheses around macro arg]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[Masahiro: import from Linux and adjust ioread32() to readl() ]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agosunxi: ohci: Add A83T compatible
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:54 +0000 (00:26 +0800)]
sunxi: ohci: Add A83T compatible

We have a separate compatible for almost each SoC. Add one for the A83T.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: ehci: Add A83T compatible
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:53 +0000 (00:26 +0800)]
sunxi: ehci: Add A83T compatible

We have a separate compatible for almost each SoC. Add one for the A83T.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: clk: Fix USB PHY clock macros for A83T
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:52 +0000 (00:26 +0800)]
sunxi: clk: Fix USB PHY clock macros for A83T

The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: usb_phy: Add support for A83T USB PHYs
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:51 +0000 (00:26 +0800)]
sunxi: usb_phy: Add support for A83T USB PHYs

The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host,
1 for USB HSIC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: h8_homlet_v2: Set DLDO4 to 3.3V
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:50 +0000 (00:26 +0800)]
sunxi: h8_homlet_v2: Set DLDO4 to 3.3V

DLDO4 supplies power to the PD pins, and the AC200 Ethernet PHY /
composite video encoder.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:49 +0000 (00:26 +0800)]
sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V)

The schematics of the h8_homlet_v2 show DCDC1 set to 3.3V. Some
Allwinner-based boards set it to 3.0V to conserve power. Since the
h8_homlet_v2 is a set-top box board with external power, there is
no such requirement.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agopower: axp818: Add support for FLDOs
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:48 +0000 (00:26 +0800)]
power: axp818: Add support for FLDOs

The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY
on the A83T/H8.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agopower: axp818: Fix DCDC5 default voltage
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:47 +0000 (00:26 +0800)]
power: axp818: Fix DCDC5 default voltage

DCDC5 is designed to supply VCC-DRAM, which is normally 1.5V for DDR3,
1.35V for DDR3L, and 1.2V for LPDDR3.

Also remove CONFIG_AXP_DCDC5_VOLT from h8_homlet_v2_defconfig.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: axp: Support VBUS drive GPIO on AXP818
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:57 +0000 (00:26 +0800)]
sunxi: axp: Support VBUS drive GPIO on AXP818

AXP818 supports VBUS drive function, even though the manual does not
mention it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: axp: Generalize register macros for VBUS drive GPIO
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:56 +0000 (00:26 +0800)]
sunxi: axp: Generalize register macros for VBUS drive GPIO

VBUS drive is supported on AXP221 and later PMICs. Rework the macros
so we can support this on later PMICs without too much work.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agomusb: sunxi: Add support for A83T
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:55 +0000 (00:26 +0800)]
musb: sunxi: Add support for A83T

Like the Allwinner A33 SoC, the A83T is missing the config register
from the musb USB DRD hardware block. Use a known working value for
it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agopower: axp818: Remove undefined axp818_init()
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:46 +0000 (00:26 +0800)]
power: axp818: Remove undefined axp818_init()

axp818_init() is declared, but never defined.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Enable LDO3 and LDO4 at 2.8V on OLinuxIno Lime boards
Hans de Goede [Thu, 31 Mar 2016 12:38:14 +0000 (14:38 +0200)]
sunxi: Enable LDO3 and LDO4 at 2.8V on OLinuxIno Lime boards

LDO3 and LDO4 are used to power port E resp. port G, which are exposed
on gpio headers, so enable them at 2.8V as specified in the schematic.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: A20-OLinuXino-Lime2: Force 8211CL to master
Michael Haas [Fri, 25 Mar 2016 17:22:52 +0000 (18:22 +0100)]
sunxi: A20-OLinuXino-Lime2: Force 8211CL to master

Force master mode on the A20-OLinuXino-Lime2. This change is required
to get a reliable link at gigabit speeds.

Signed-off-by: Michael Haas <haas@computerlinguist.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: A20-Olimex-SOM-EVB: Force 8211CL to master
Michael Haas [Fri, 25 Mar 2016 17:22:51 +0000 (18:22 +0100)]
sunxi: A20-Olimex-SOM-EVB: Force 8211CL to master

Force master mode for 1000BASE-T operation on the
A20-Olimex-SOM-EVB.

Karsten Merker reports that this change is necessary to get a reliable
link at gigabit speeds.

Signed-off-by: Michael Haas <haas@computerlinguist.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agonet: phy: Optionally force master mode for RTL PHY
Michael Haas [Fri, 25 Mar 2016 17:22:50 +0000 (18:22 +0100)]
net: phy: Optionally force master mode for RTL PHY

This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this
define is set, RTL8211x PHYs (except for the RTL8211F) will have their
1000BASE-T master/slave autonegotiation disabled and forced to master
mode.

This is helpful for PHYs like the RTL8211C which produce unstable links
in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB
and A20-OLinuXino-Lime2.

There is no proper way to identify affected PHYs in software as the
RTL8211C shares its UID with the RTL8211B. Thus, this fix requires
the introduction of an #ifdef.

CC: fradav@gmail.com
CC: merker@debian.org
CC: hdegoede@redhat.com
CC: ijc@hellion.org.uk
CC: joe.hershberger@ni.com
Signed-off-by: Michael Haas <haas@computerlinguist.org>
Tested-by: Karsten Merker <merker@debian.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Print soc-id from sram controller for sun8i boards
Hans de Goede [Thu, 24 Mar 2016 21:38:23 +0000 (22:38 +0100)]
sunxi: Print soc-id from sram controller for sun8i boards

As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agosunxi: Add conditional magic sram poke for A33
Hans de Goede [Thu, 24 Mar 2016 21:37:08 +0000 (22:37 +0100)]
sunxi: Add conditional magic sram poke for A33

I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Tue, 29 Mar 2016 17:33:13 +0000 (13:33 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 29 Mar 2016 16:58:45 +0000 (12:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agoARM: tegra210: set PLLE_PTS bit when enabling PLLE
Stephen Warren [Tue, 22 Mar 2016 15:45:36 +0000 (09:45 -0600)]
ARM: tegra210: set PLLE_PTS bit when enabling PLLE

This bit needs to be set for system suspend/resume to work. This setting
will be documented in an updated TRM at some time in the future.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoarmv8/ls2080ardb: Enable VID support
Rai Harninder [Wed, 23 Mar 2016 11:34:38 +0000 (17:04 +0530)]
armv8/ls2080ardb: Enable VID support

This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.

Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8/ls1043aqds: dts: Set SPI mode for DSPI
Qianyu Gong [Wed, 23 Mar 2016 11:11:36 +0000 (19:11 +0800)]
armv8/ls1043aqds: dts: Set SPI mode for DSPI

Clock phase and polarity for DSPI flash need to be set.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Add LS1023A SVR
Mingkai Hu [Wed, 23 Mar 2016 11:10:43 +0000 (19:10 +0800)]
armv8: fsl-layerscape: Add LS1023A SVR

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Fix LS1043A SVR register
Mingkai Hu [Wed, 23 Mar 2016 11:10:42 +0000 (19:10 +0800)]
armv8: fsl-layerscape: Fix LS1043A SVR register

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoSECURE BOOT: Change fsl_secboot_validate func to pass image addr
Saksham Jain [Wed, 23 Mar 2016 10:54:45 +0000 (16:24 +0530)]
SECURE BOOT: Change fsl_secboot_validate func to pass image addr

Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoSECURE BOOT: Halt execution when secure boot fail
Saksham Jain [Wed, 23 Mar 2016 10:54:44 +0000 (16:24 +0530)]
SECURE BOOT: Halt execution when secure boot fail

In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.

Add esbh_halt() after the reset to make sure execution stops.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoSECURE_BOOT: Use default bootargs
Saksham Jain [Wed, 23 Mar 2016 10:54:43 +0000 (16:24 +0530)]
SECURE_BOOT: Use default bootargs

For secure boot, currently we were using fixed bootargs for all SoCs.
This is not needed and we can use the bootargs which are used in
non-secure boot.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agocrypto/fsl: Make CAAM transactions cacheable
Saksham Jain [Wed, 23 Mar 2016 10:54:42 +0000 (16:24 +0530)]
crypto/fsl: Make CAAM transactions cacheable

This commit solves CAAM coherency issue on ls2080. When caches are
enabled and CAAM's DMA's AXI transcations are not made cacheable,
Core reads/writes data from/to caches and CAAM does from main memory.
This forces data flushes to synchronize various data structures. But
even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.

To avoid this problem, either all the data that CAAM accesses can be
made cache line aligned or CAAM transcations can be made cacheable.

So, this commit makes CAAM transcations as write back with write and
read allocate.

Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agocrypto/fsl: Correct 64-bit write when MMU disabled
Saksham Jain [Wed, 23 Mar 2016 10:54:41 +0000 (16:24 +0530)]
crypto/fsl: Correct 64-bit write when MMU disabled

When MMU is disabled, 64-bit write must be aligned at 64-bit
boundary. Becaue the memory location is not guaranteed to be 64-bit
aligned, the 64-bit write needs to be split into two 32-bit writes
to avoid the alignment exception.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-lsch3: Disable SMMU during secure boot
Saksham Jain [Wed, 23 Mar 2016 10:54:40 +0000 (16:24 +0530)]
armv8: fsl-lsch3: Disable SMMU during secure boot

During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.

For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080: Add config for endianess of CCSR GUR
Saksham Jain [Wed, 23 Mar 2016 10:54:39 +0000 (16:24 +0530)]
armv8: ls2080: Add config for endianess of CCSR GUR

The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080: Change env variable "fdt_high"
Saksham Jain [Wed, 23 Mar 2016 10:54:38 +0000 (16:24 +0530)]
armv8: ls2080: Change env variable "fdt_high"

"fdt_high" env variable was set to 0xcfffffff for secure boot.
Change it to 0xa0000000 for LS2080 to be consistent with non-secure
boot targets.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-lsch3: Copy Bootscript and header from NOR to DDR
Saksham Jain [Wed, 23 Mar 2016 10:54:37 +0000 (16:24 +0530)]
armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDR

To unify steps for secure boot for xip (eg. NOR) and non-xip memories
(eg. NAND, SD), bootscipts and its header are copied to main memory.
Validation and execution are performed from there.

For other ARM Platforms (ls1043 and ls1020), to avoid disruption of
existing users, this copy step is not used for NOR boot.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080: Add bootscript header addr for secure boot
Saksham Jain [Wed, 23 Mar 2016 10:54:36 +0000 (16:24 +0530)]
armv8: ls2080: Add bootscript header addr for secure boot

During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it executes. This requires a header for bootscript.

When secure boot is enabled, default bootcmd is changed to first
validate bootscript using the header and then execute the script.

For ls2080, NOR memory map is different from other ARM SoCs. So a new
address on NOR is used for this bootscript header (0x583920000). The
Bootscript address is mentioned in this header along with addresses of
other images.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080rdb: ls2080qds: Add secure boot support
Saksham Jain [Wed, 23 Mar 2016 10:54:35 +0000 (16:24 +0530)]
armv8: ls2080rdb: ls2080qds: Add secure boot support

Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).

Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-lsch3: Add new header for secure boot
Saksham Jain [Wed, 23 Mar 2016 10:54:34 +0000 (16:24 +0530)]
armv8: fsl-lsch3: Add new header for secure boot

For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.

Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080: Add configs for SEC, SecMon, SRK and DCFG
Saksham Jain [Wed, 23 Mar 2016 10:54:33 +0000 (16:24 +0530)]
armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFG

Add configs for various IPs used during secure boot. Add address
and endianness for SEC and Security Monitor. SRK are fuses in SFP
(fuses for public key's hash). These are stored in little endian
format.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080: Add SFP Configs for LS2080
Saksham Jain [Wed, 23 Mar 2016 10:54:32 +0000 (16:24 +0530)]
armv8: ls2080: Add SFP Configs for LS2080

In LS2080, SFP has version 3.4. It is in little endian. The base
address is 0x01e80200. SFP is used in Secure Boot to read fuses.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: net: fsl-mc: Check NULL before pointer dereference
Prabhakar Kushwaha [Fri, 18 Mar 2016 10:46:03 +0000 (16:16 +0530)]
driver: net: fsl-mc: Check NULL before pointer dereference

NULL pointer should be checked before any dereference.  This patch
move memest after the NULL pointer check.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: net: fsl-mc: Free dflt_dpio pointer after its usage
Prabhakar Kushwaha [Fri, 18 Mar 2016 10:45:29 +0000 (16:15 +0530)]
driver: net: fsl-mc: Free dflt_dpio pointer after its usage

Free dflt_dpio pointer after its usage during error handling

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPI
Qianyu Gong [Wed, 16 Mar 2016 10:01:52 +0000 (18:01 +0800)]
armv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPI

The qspi_cfg register is set by PBI when booting from QSPI. No need
to changing it again.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoomap24xx_i2c: Implement CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
Guy Thouret [Fri, 11 Mar 2016 16:23:41 +0000 (16:23 +0000)]
omap24xx_i2c: Implement CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW

Signed-off-by: Guy Thouret <guy.thouret@wems.co.uk>
Cc: Heiko Schocher <hs@denx.de>
8 years agodm: i2c: mxc_i2c: implement i2c_idle_bus
Peng Fan [Fri, 11 Mar 2016 08:47:50 +0000 (16:47 +0800)]
dm: i2c: mxc_i2c: implement i2c_idle_bus

Implement i2c_idle_bus in driver, then setup_i2c can
be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL.
The i2c_idle_bus force bus idle flow follows setup_i2c in
arch/arm/imx-common/i2c-mxv7.c

This patch is an implementation following linux kernel patch:
"
commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5
Author: Gao Pan <b54642@freescale.com>
Date:   Fri Oct 23 20:28:54 2015 +0800

    i2c: imx: implement bus recovery

    Implement bus recovery methods for i2c-imx so we can recover from
    situations where SCL/SDA are stuck low.

    Once i2c bus SCL/SDA are stuck low during transfer, config the i2c
    pinctrl to gpio mode by calling pinctrl sleep set function, and then
    use GPIO to emulate the i2c protocol to send nine dummy clock to recover
    i2c device. After recovery, set i2c pinctrl to default group setting.
"

See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed
description.
1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus.
2. Discard the __weak attribute for i2c_idle_bus and implement it,
   since we have pinctrl driver/driver model gpio driver. We can
   use device tree, but not let board code to do this.
3. gpio state for mxc_i2c is not a must, but it is recommended. If
   there is no gpio state, driver will give tips, but not fail.
4. The i2c controller was first probed, default pinctrl state will
   be used, so when need to use gpio function, need to do
   "pinctrl_select_state(dev, "gpio")" and after force bus idle,
   need to switch back "pinctrl_select_state(dev, "default")".

This is example about how to use the gpio force bus
idle function:
"
 &i2c1 {
  clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
  pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
status = "okay";
[....]
 };

[.....]

pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
>;
};
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
8 years agoRevert "pxa_lcd: make driver cache-aware"
Tom Rini [Mon, 28 Mar 2016 00:58:08 +0000 (20:58 -0400)]
Revert "pxa_lcd: make driver cache-aware"

This reverts commit 59deb7fe8d23c8ec2b659d99323ec4a2ec19148a.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoRevert "pxa_lcd: invert colors for Zipit Z2 to get white on black palette"
Tom Rini [Mon, 28 Mar 2016 00:57:54 +0000 (20:57 -0400)]
Revert "pxa_lcd: invert colors for Zipit Z2 to get white on black palette"

This reverts commit 3bc8ffd9cb774feceefc7bdebe9353fcea071343.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agotools: env: bug: config structs must be defined in tools library
Andreas Fenkart [Fri, 25 Mar 2016 13:52:19 +0000 (14:52 +0100)]
tools: env: bug: config structs must be defined in tools library

fw_senten/fw_printenv can be compiled as a tools library,
excluding the fw_env_main object.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
8 years agoARM: asm: types: Introduce DMA_ADDR_T_64BIT
Lokesh Vutla [Thu, 24 Mar 2016 10:32:00 +0000 (16:02 +0530)]
ARM: asm: types: Introduce DMA_ADDR_T_64BIT

dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
addresses, dma_addr_t need only be 32 bits wide.  Bus addresses, e.g., PCI BARs,
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
kernel virtual addresses, so they don't care about the size of the actual
bus addresses.
Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
DMA still use 32bit address like in case of DRA7 and Keystone platforms.

This is inspired from the Linux kernel types implementation[1]

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142

Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoefi_loader: Fix some entry/exit points
Alexander Graf [Thu, 24 Mar 2016 00:37:37 +0000 (01:37 +0100)]
efi_loader: Fix some entry/exit points

When switching between EFI context and U-Boot context we need to swap
the register that "gd" resides in.

Some functions slipped through here, with efi_allocate_pool / efi_free_pool
not doing the switch correctly and efi_return_handle switching too often.

Fix them all up to make sure we always have consistent register state.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agocfi_flash: return device into read array mode after reading status
Vasily Khoruzhick [Mon, 21 Mar 2016 01:37:10 +0000 (18:37 -0700)]
cfi_flash: return device into read array mode after reading status

Otherwise flash remains in read status mode and it's not possible
to access data on flash.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
8 years agozipitz2: enable caches
Vasily Khoruzhick [Mon, 21 Mar 2016 01:37:09 +0000 (18:37 -0700)]
zipitz2: enable caches

It speeds up loading kernel from SD or USB a lot.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
8 years agopxa_lcd: make driver cache-aware
Vasily Khoruzhick [Mon, 21 Mar 2016 01:37:08 +0000 (18:37 -0700)]
pxa_lcd: make driver cache-aware

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
8 years agopxa: add support for D- and I- caches
Vasily Khoruzhick [Mon, 21 Mar 2016 01:37:07 +0000 (18:37 -0700)]
pxa: add support for D- and I- caches

Tested with OHCI and pxafb drivers - no issues found

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
8 years agopxa: start.S: enable SRAM clock
Vasily Khoruzhick [Mon, 21 Mar 2016 01:37:06 +0000 (18:37 -0700)]
pxa: start.S: enable SRAM clock

SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>