Maxime Ripard [Fri, 4 Nov 2016 15:18:11 +0000 (16:18 +0100)]
sunxi: sina33: Enable the LCD
The SinA33 comes with an optional 7" display. Enable it in the
configuration.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Fri, 4 Nov 2016 15:18:10 +0000 (16:18 +0100)]
sunxi: sina33: Enable the eMMC
The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller.
Enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Fri, 4 Nov 2016 15:18:09 +0000 (16:18 +0100)]
mmc: sunxi: Enable 8bits bus width for sun8i
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the
support for those too.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Fri, 4 Nov 2016 15:18:08 +0000 (16:18 +0100)]
mmc: Retry the switch command
Some eMMC will fail at the first switch, but would succeed in a subsequent
one.
Make sure we try several times to cover those cases. The number of retries
(and the behaviour) is currently what is being used in Linux.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Bharat Kumar Gogada [Tue, 2 Aug 2016 15:04:13 +0000 (20:34 +0530)]
ARM64: zynqmp: Adding prefetchable memory space to pcie
Adding prefetchable memory space to pcie device tree node.
Shifting configuration space to 64-bit address space.
Removing pcie device tree node from amba as it requires size-cells=<2>
in order to access 64-bit address space.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kedareswara rao Appana [Fri, 30 Sep 2016 05:04:59 +0000 (10:34 +0530)]
ARM64: zynqmp: Add clocks for LPDDMA
Zynqmp DMA driver expects two clocks (main clock and apb clock)
For LPDDMA channels the two clocks are missing in the
Dma node resulting probe failure.
xilinx-zynqmp-dma
ffa80000.dma: main clock not found.
xilinx-zynqmp-dma
ffa80000.dma: Probing channel failed
xilinx-zynqmp-dma: probe of
ffa80000.dma failed with error -2
This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kedareswara rao Appana [Fri, 9 Sep 2016 07:06:01 +0000 (12:36 +0530)]
ARM64: zynqmp: Add description for LPDDMA channel usage
LPDDMA default allows only secured access.
inorder to enable these dma channels,
one should ensure that it allows non secure access.
This patch updates the same.
Reported-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 11 Feb 2016 06:19:06 +0000 (07:19 +0100)]
ARM64: zynqmp: Use 64bit size cell format for main amba bus
Use 64bit size cell for main amba bus instead of 32bit because PCIe
node requires it Change 64bit sizes also for all others IPs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Naga Sureshkumar Relli [Wed, 18 May 2016 06:53:13 +0000 (12:23 +0530)]
ARM64: zynqmp: Add ocm node in dtsi
This patch adds ocm controller node in zynqmp.dtsi.
needed for OCM edac support.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Tue, 17 May 2016 11:19:01 +0000 (16:49 +0530)]
ARM64: zynqmp: Add device tree properties for ZynqMP GT core
This patch adds the ZynqMP GT core device-tree properties for
zynqmp.dtsi file.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Tested-by: Hyun Kwon <hyunk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 20 Oct 2016 08:36:05 +0000 (10:36 +0200)]
Revert "ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes"
This reverts commit
bd750e7a6c515c081b72d4ef108a2bfa691a3fd1
Implemented the new workaround for auto tuning based on
zynqmp compatible string, so removed the 'broken-tuning'
property.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sai Krishna Potthuri [Tue, 16 Aug 2016 09:11:35 +0000 (14:41 +0530)]
ARM64: zynqmp: change sdhci compatible string.
This patch changes the compatible string for sdhci node,
adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node.
Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 6 Apr 2016 08:43:23 +0000 (10:43 +0200)]
ARM64: zynqmp: List all SMMU ids
Add SMMU description for all tested IPs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nava kishore Manne [Sat, 20 Aug 2016 18:47:52 +0000 (00:17 +0530)]
ARM64: zynqmp: Add support for zynqmp fpga manager
Add support for zynqmp fpga manager.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Naga Sureshkumar Relli [Mon, 20 Jun 2016 10:18:30 +0000 (15:48 +0530)]
ARM64: zynqmp: Add cortexa53 edac node
This patch adds edac node for arm cortexa53 to report
errors on L1 and L2 caches.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 20 Oct 2016 08:38:16 +0000 (10:38 +0200)]
Revert "ARM64: zynqmp: Add serdes address space dp driver"
This reverts commit
786db82bd5bf09cc8f78c8b14445e843d7566b1c.
Since we are using serdes driver , no need of mapping serdes register
space into DP driver.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Tested-by: Hyun Kwon <hyunk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Fri, 15 Jul 2016 00:42:44 +0000 (17:42 -0700)]
ARM64: zynqmp: drm: Add DMA index
Each plane can be associated with multiple DMA channels. So add
index for each DMA channel.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 20 Oct 2016 08:26:13 +0000 (10:26 +0200)]
ARM64: zynqmp: Sync gpio node properties
Keep dtsi in sync with mainline kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 9 Aug 2016 13:06:58 +0000 (15:06 +0200)]
ARM64: zynqmp: Remove xlnx,id property
Remove unused xlnx,id property because it is not the part of
DT binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Bharat Kumar Gogada [Tue, 19 Jul 2016 15:19:29 +0000 (20:49 +0530)]
ARM64: zynqmp: pci: Updating device tree as per upstream
Updating required device tree changes as per mainlined driver
from 4.6 kernel.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Filip Drazic [Mon, 29 Aug 2016 17:32:59 +0000 (19:32 +0200)]
ARM64: zynqmp: Support for multiple PM IDs assigned to a PM domain
Previously, it was assumed that there is a 1:1 mapping between
PM ID defined in the platform firmware and a PM domain. However, there
can be a situation where multiple PM IDs belong to a single PM domain
(e.g. PM IDs for GPU and two pixel processors correspond to a single
PM domain).
This patch adds support for assigning more than one PM ID to
a single PM domain.
Updated documentation accordingly.
Assigned pixel processors PM IDs to GPU PM domain.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Filip Drazic [Mon, 29 Aug 2016 17:32:56 +0000 (19:32 +0200)]
ARM64: zynqmp: DT: Add PM domains for GPU and PCIE
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Filip Drazic [Thu, 25 Aug 2016 16:58:51 +0000 (18:58 +0200)]
ARM64: zynqmp: DT: Remove unused PM domains for PLL
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Filip Drazic [Thu, 25 Aug 2016 16:58:49 +0000 (18:58 +0200)]
ARM64: zynqmp: DT: Remove unused DDR PM domain
DDR power states are handled by the PM firmware, so this domain is
redundant. Also, since there is no device using this PM domain,
it will be powered off during boot, which is wrong.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 19 Oct 2016 14:07:58 +0000 (16:07 +0200)]
ARM64: zynqmp: Remove note about level shifter on zcu102
i2c device is just level shifter. Remove reference from dts.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 9 Sep 2016 06:46:39 +0000 (08:46 +0200)]
ARM64: zynqmp: Add dcc port to dtsi
Add dcc to dtsi for supporting system without serial port.
DCC is enabled by default on ZynqMP.
Adding dcc to zcu100 and zcu102 which were tested.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 25 May 2016 18:09:35 +0000 (20:09 +0200)]
ARM64: zynqmp: Add gpio-keys for zcu102
There is gpio push button on MIO22. Add it to DTS to have full board
description.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 20 Apr 2016 11:12:25 +0000 (13:12 +0200)]
ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102
Show user that Linux is alive on the board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Naga Sureshkumar Relli [Tue, 12 Apr 2016 06:16:11 +0000 (11:46 +0530)]
ARM64: zynqmp: Enable can1 for ep108
This patch enables can1 for ep108.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
VNSL Durga [Mon, 11 Apr 2016 12:13:47 +0000 (17:43 +0530)]
ARM64: zynqmp: Added clocks to DT for ep108
Added clks for ep108 platform.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kedareswara rao Appana [Fri, 9 Sep 2016 07:06:00 +0000 (12:36 +0530)]
ARM64: zynqmp: Add clocks for LPDDMA
Zynqmp DMA driver expects two clocks (main clock and apb clock)
LPDDMA clock cofiguration is missing for the same in the
zynqmp-clk.dtsi file.
This patch updates for the same.
Reported-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 11 Nov 2016 12:21:04 +0000 (13:21 +0100)]
ARM64: zynqmp: Remove DTC 1.4.2 warnings
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /amba has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /amba/usb@
fe200000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node /amba/usb@
fe300000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node
/amba/dma@
fd4c0000/dma-video0channel@
fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@
fd4c0000/dma-video1channel@
fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@
fd4c0000/dma-video2channel@
fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@
fd4c0000/dma-graphicschannel@
fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@
fd4c0000/dma-audio0channel@
fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@
fd4c0000/dma-audio1channel@
fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
This patch is fixing them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 11 Nov 2016 12:11:37 +0000 (13:11 +0100)]
ARM: zynq: Remove DTC 1.4.2 warnings
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name,
but no reg property
This patch is fixing them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 1 Nov 2016 18:19:53 +0000 (23:49 +0530)]
ARM64: zynqmp: Correct the sdhci minimum frequency for ep108
Correct the sdhci minimum frequency for ep platform.
It should be right shift instead of left shift operand.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 14 Jul 2016 09:13:04 +0000 (11:13 +0200)]
ARM64: zynqmp: Ignore warnings from autogenerated files
Autogenerated files contain casting issues and missing function
declaration and even usleep implementation. Suppress them for now
till these files are fixed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 25 Oct 2016 09:43:02 +0000 (11:43 +0200)]
ARM64: zynqmp: Fix secondary bootmode enabling
Do not setup use_alt bit which copy alternative boot mode to
boot mode. The reason is that this bit is cleared after POR
but not after any software reset which will cause
that after SW reset bootrom will look for different boot image.
This patch setups alternative boot mode selection (purely SW
handling) and extends code to read this alternative boot mode first and
use it if it is setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Wed, 21 Sep 2016 06:15:05 +0000 (11:45 +0530)]
ARM64: zynqmp: Add support for SD1 with level shifters bootmode
Add support for SD1 with level shifters bootmode.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 1 Sep 2016 09:27:32 +0000 (11:27 +0200)]
ARM64: zynqmp: Record board name as serial number for DFU/FASTBOOT
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Thu, 29 Sep 2016 18:44:41 +0000 (11:44 -0700)]
ARM64: zynqmp: Adjust to new SMC interface to get silicon version
The new FW interface returns the IDCODE and version register, leaving
extracting bitfields to the caller.
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 18 Oct 2016 14:10:25 +0000 (16:10 +0200)]
ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devices
Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Mon, 16 May 2016 10:01:38 +0000 (15:31 +0530)]
net: zynq_gem: Correct SGMII enable bit setting
Correct the SGMII enable bit position to 27 instead
of 31.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Siva Durga Prasad Paladugu [Mon, 16 May 2016 10:01:37 +0000 (15:31 +0530)]
net: zynq_gem: Modify the nwcfg bit definitions
Modify the nwcfg bit definitions to have 32-bit
by removing the extra nibble.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Siva Durga Prasad Paladugu [Thu, 25 Aug 2016 10:30:04 +0000 (16:00 +0530)]
nand: arasan_nfc: Clear ecc on bit while sending read command
Clear ecc ON bit while sending read command as all types
of read command(like reading spare) doesnt need ECC to be
enabled. It has been anyway taken care in other places
whereever required using arasan_nand_enable_ecc().
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 26 Oct 2016 08:49:37 +0000 (10:49 +0200)]
zynq: nand: Runtime detection of nand buswidth through slcr
This patch adds support to check the buswidth on nand flash
at runtime based on nand MIO configurations done by FSBL.
User needs to correctly configure the MIO's based on the
buswidth supported by the nand flash which is present on the board.
Added nand8 and nand16 @periph names on slcr driver.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 27 Sep 2016 05:25:47 +0000 (10:55 +0530)]
zynq: nand: Enable Nand flash controller driver a zynq board
Enable zynq Nand flash controller driver for a zynq ZC770
XM011(dc2) board.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 27 Sep 2016 05:25:46 +0000 (10:55 +0530)]
mtd: nand: zynq_nand: Add nand driver support for zynq
Add nand flash controller driver support for zynq SoC.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mike Looijmans [Fri, 30 Sep 2016 06:13:13 +0000 (08:13 +0200)]
ARM: zynq: Add support for the topic-miami system-on-modules and carrier boards
The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM,
32MB QSPI NOR flash and 256MB NAND flash.
The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC,
2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources
and a fan controller.
The "Florida" carrier boards add SD, USB, ethernet and other interfaces.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mike Looijmans [Wed, 28 Sep 2016 05:46:30 +0000 (07:46 +0200)]
ARM: zynq: Make SYS_VENDOR configurable
Add a string description for SYS_VENDOR to allow configuring boards from
other vendors than just "xilinx".
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 21 Oct 2016 11:16:13 +0000 (13:16 +0200)]
tools: mkimage: Check if file is regular file
Current Makefile.spl passes -R parameter which is not empty
and pointing to ./ folder.
"./tools/mkimage -T zynqmpimage -R ./"" -d spl/u-boot-spl.bin
spl/boot.bin"
That's why mkimage is trying to parse ./ file and generate
register init which is wrong.
Check that passed filename is regular file. If not do not work with it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mike Looijmans [Tue, 20 Sep 2016 09:37:24 +0000 (11:37 +0200)]
tools: mkimage: Add support for initialization table for Zynq and ZynqMP
The Zynq/ZynqMP boot.bin file contains a region for register initialization
data. Filling in proper values in this table can reduce boot time
(e.g. about 50ms faster on QSPI boot) and also reduce the size of
the SPL binary.
The table is a simple text file with register+data on each line. Other
lines are simply skipped. The file can be passed to mkimage using the
"-R" parameter.
It is recommended to add reg init file to board folder.
For example:
CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Simon Glass [Mon, 7 Nov 2016 15:47:16 +0000 (08:47 -0700)]
x86: Enable EFI loader support
Enable this so that EFI applications (notably grub) can be run under U-Boot
on x86 platforms.
At present the 'hello world' EFI application is not supported for the
qemu-x86_efi_payload64 board. That board builds a payload consisting of a
64-bit header and a 32-bit U-Boot, which is incompatible with the way the
EFI loader builds its EFI application. The following error is obtained:
x86_64-linux-ld.bfd: i386 architecture of input file
`lib/efi_loader/helloworld.o' is incompatible with i386:x86-64 output
This could be corrected with additional Makefile rules. For now, this
feature is disabled for that board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[agraf: drop hello kconfig bits]
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:15 +0000 (08:47 -0700)]
efi: x86: Adjust EFI files support efi_loader
Add compiler flags and make a few minor adjustments to support the efi
loader.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Add Kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:14 +0000 (08:47 -0700)]
x86: Move efi .S files into the 'lib' directory
These files now need to be in a standard place so that they can be located
by generic Makefile rules. Move them to the 'lib' directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:13 +0000 (08:47 -0700)]
x86: Move efi .lds files into the 'lib' directory
These files now need to be in a standard place so that they can be located
by generic Makefile rules. Move them to the 'lib' directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:11 +0000 (08:47 -0700)]
efi: arm: Add aarch64 EFI app support
Add support for EFI apps on aarch64. This includes start-up and relocation
code plus a link script.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: add kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:10 +0000 (08:47 -0700)]
efi: arm: Add EFI app support
Add support for EFI apps on ARM. This includes start-up and relocation
code, plus a link script and some compiler setting changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Remove whitespace change, add kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:09 +0000 (08:47 -0700)]
elf: arm: Add a few ARM relocation types
Rather than hard-coding the relocation type, add it to the ELF header file
and use it from there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:08 +0000 (08:47 -0700)]
efi: Add support for a hello world test program
It is useful to have a basic sanity check for EFI loader support. Add a
'bootefi hello' command which loads HelloWord.efi and runs it under U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
[agraf: Fix documentation, add unfulfilled kconfig dep]
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:07 +0000 (08:47 -0700)]
efi: Makefile: Export variables for use with EFI
When building an EFI app we need three things:
- start-up code
- relocation code
- link script
These are all different for each architecture. We also need special
compiler flags in some cases.
Add top-level Makefile variables for these along with documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:06 +0000 (08:47 -0700)]
x86: Tidy up selection of building the EFI stub
At present we use a CONFIG option in efi.h to determine whether we are
building the EFI stub or not. This means that the same header cannot be
used for EFI_LOADER support. The CONFIG option will be enabled for the
whole build, even when not building the stub.
Use a different define instead, set up just for the files that make up the
stub.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:05 +0000 (08:47 -0700)]
efi: Fix debug message address format
This should use U-Boot's standard format for hex address. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:04 +0000 (08:47 -0700)]
efi: Correct cache flush alignment
Make sure that the cache flushes correctly by ensuring that the end
address is correctly aligned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Simon Glass [Mon, 7 Nov 2016 15:47:03 +0000 (08:47 -0700)]
x86: Correct a build warning in x86 tables
There is a build warning for three x86 boards since
write_smbios_table_wrapper() is not used. Fix it.
Fixes:
e824cf3f (smbios: Allow compilation on 64bit systems)
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Emmanuel Vadot [Tue, 8 Nov 2016 05:03:29 +0000 (06:03 +0100)]
efi_loader: console: Correctly report modes
Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.
If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode 1,
we install it as mode 2.
Modes can be switch with cout_set_mode.
Changes in V5:
Correctly detect mode before enabling mode 2.
Changes in V4:
Reset cursor positon on mode switch
Use local variables in console query code
Changes in V3:
Valid mode are 0 to EFIMode-1
Fix style
Changes in V2:
Add mode switch
Report only the modes that we support
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Oleksandr Tymoshenko [Mon, 24 Oct 2016 17:47:01 +0000 (10:47 -0700)]
efi: Use device device path type Messaging for network interface node
When adding network interface node use Messaging device path with
subtype MAC Address and device's MAC address as a value instead
of Media Device path type with subtype File Path and path "Net"
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Masahiro Yamada [Wed, 19 Oct 2016 15:23:43 +0000 (00:23 +0900)]
efi_loader: fix depends on line of EFI_LOADER
This line is shown as
depends on (ARM64 ||\302\240ARM) && OF_LIBFDT
on my Emacs. Use ASCII characters only.
Assuming it is (ARM64 || ARM), remove the redundancy.
Unlike Linux, CONFIG_ARM includes CONFIG_ARM64 in U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Rini [Mon, 14 Nov 2016 16:27:11 +0000 (11:27 -0500)]
Prepare v2016.11
Signed-off-by: Tom Rini <trini@konsulko.com>
Hans de Goede [Mon, 14 Nov 2016 11:53:25 +0000 (12:53 +0100)]
MAINTAINERS: mark sunxi status as Orphan
Ian has not had any time for sunxi for some time now and I'm
in the same situation now, so I'm stepping down as sunxi
custodian and marking the sunxi support as Orphan.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Stefan Roese [Sat, 12 Nov 2016 09:32:38 +0000 (10:32 +0100)]
video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabled
Compiling the 'bmp' command with DM and having one of the following macros
enabled:
CONFIG_BMP_16BPP, CONFIG_BMP_24BPP ONFIG_BMP_32BPP
generates this error:
drivers/video/video_bmp.c: In function ‘video_bmp_display’:
drivers/video/video_bmp.c:315:22: error: ‘lcd_line_length’ undeclared (first use in this function)
fb -= width * 2 + lcd_line_length;
^
This patch moves to using the correct variable instead and enables the
'bmp' command for DM again.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Marek Vasut [Sat, 12 Nov 2016 15:28:40 +0000 (16:28 +0100)]
net: write enetaddr down to hardware on env_callback
If mac-address is changed using "setenv ethaddr ...." command the new
mac-adress also must be written into the responsible ethernet driver.
This fixes the legacy ethernet handling.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Vignesh R [Sat, 5 Nov 2016 10:35:16 +0000 (16:05 +0530)]
spi: ti_qspi: Fix baudrate divider calculation
Fix the divider calculation logic to choose a value so that the
resulting baudrate is either equal to or closest possible baudrate less
than the requested value. While at that, cleanup ti_spi_set_speed().
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Vignesh R [Sat, 5 Nov 2016 10:35:15 +0000 (16:05 +0530)]
ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node
Update the spi-max-frequency property of m25p80 flash slave to match
that of TI QSPI controller node, so that QSPI operations happen at
maximum supported frequency of 76.8MHz.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Lokesh Vutla [Thu, 3 Nov 2016 10:05:02 +0000 (15:35 +0530)]
ARM: k2g: Update PLL Multiplier and divider values
Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18
[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Thu, 3 Nov 2016 10:02:51 +0000 (15:32 +0530)]
ARM: keystone2: PLL: Enable glitch free initialization sequence
Update the PLL initialization sequence to avoid glitches while
programming. User guide for the same is available at[1].
[1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Keerthy [Sat, 29 Oct 2016 09:49:10 +0000 (15:19 +0530)]
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.
Fix this to mark the regions as XN by default.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Keerthy [Sat, 29 Oct 2016 09:49:09 +0000 (15:19 +0530)]
arm: print the cache config option in hex instead of decimal
Printing the option value in hex makes it more comprehensible.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diego Dorta [Thu, 10 Nov 2016 17:05:37 +0000 (15:05 -0200)]
mx6ull_14x14_evk: Add README file
Add a README file to help users getting started with the board.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Fabien Parent [Thu, 10 Nov 2016 16:16:35 +0000 (17:16 +0100)]
davinci: omapl138_lcdk: keep booting even when MAC address is invalid
If the MAC address specified on the EEPROM is invalid (multicast or
zero address), then u-boot fails to boot. Having a bad MAC address
in the EEPROM should not prevent the system from booting.
This commit changes the error path to just print an error messages
in case of bad MAC address.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Alex G [Wed, 9 Nov 2016 04:48:44 +0000 (20:48 -0800)]
board: am335x/mux: Do not hang when encountering a bad EEPROM
In most cases, the SPL and u-boot.img will be on the same boot media.
Since the SPL was loaded by the boot rom, the pinmux will already have
been configured for this media. This, the board will still be able to
boot successfully, or at least reach the u-boot console, where more
recovery options are available.
I've encountered this on a beaglebone black with a corrupted EEPROM.
Removing this check allowed the board to boot successfully. I've also
seen this on EVM-based boards with an unprogrammed EEPROM. On those
boards, for some reason there were no UART messages. This made it look
as if the SOC was dead.
Remove the hang(), as it is not a fatal error. Also reformat the error
message to be clearer as to the cause. The original message made it
appear as if the wrong binary was being loaded.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Ladislav Michl [Fri, 4 Nov 2016 11:59:46 +0000 (12:59 +0100)]
igep00x0: add Hynix timings
Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and
Hynix H27S4G6F2DKA-BM
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Javier Martinez Canillas <javier@samsung.com>
Tested-by: Javier Martinez Canillas <javier@samsung.com>
Ladislav Michl [Fri, 4 Nov 2016 11:57:27 +0000 (12:57 +0100)]
igep00x0: consolidate defconfigs
Defconfigs should remain the same except CONFIG_SYS_EXTRA_OPTIONS.
Drop NAND specific defconfig as flash type is runtime detected.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Javier Martinez Canillas <javier@samsung.com>
Ladislav Michl [Fri, 4 Nov 2016 11:55:21 +0000 (12:55 +0100)]
igep00x0: disable CONFIG_DISPLAY_BOARDINFO
As a single U-Boot binary can now run on various board modifications,
drop CONFIG_DISPLAY_BOARDINFO as it prints flash memory information
too early to give us chance to easily detect it. Also saves few bytes
as a bonus.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Javier Martinez Canillas <javier@samsung.com>
Tested-by: Javier Martinez Canillas <javier@samsung.com>
Andre Przywara [Thu, 10 Nov 2016 12:13:23 +0000 (12:13 +0000)]
tools: fix mksunxiboot build for tools-all target
Commit
fed329aebe3a ("tools: add mksunxiboot to tools-all target") added
mksunxiboot to the tools-all target, but used the CONFIG_SUNXI symbol
to enable its build. Now commit
aec9a0f19f64 ("sunxi: Rename CONFIG_SUNXI
to CONFIG_ARCH_SUNXI"), merged before that, renamed that symbol, so that
the first patch basically gets ineffective.
Adjust the symbol name in tools/Makefile to make it build again.
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tom Rini [Tue, 8 Nov 2016 15:36:57 +0000 (10:36 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Stephen Warren [Wed, 19 Oct 2016 21:18:47 +0000 (15:18 -0600)]
ARM: tegra186: call secure monitor for all cache-wide ops
An SMC call is required for all cache-wide operations on Tegra186. This
patch implements the two missing hooks now that U-Boot supports them, and
fixes the mapping of "hook name" to SMC call code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 19 Oct 2016 21:18:46 +0000 (15:18 -0600)]
armv8: add hooks for all cache-wide operations
SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 19 Oct 2016 21:18:45 +0000 (15:18 -0600)]
ARM: tegra: translate __asm_flush_l3_cache to assembly
When performing a cache disable function, code must not access DRAM.
That is because when the cache is disabled, it will be bypassed and all
loads and stores will be serviced by RAM. This prevents accessing any
dirty data in the cache. In turn, this means the stack cannot be
used, since that is in RAM. To guarantee that code doesn't use RAM (and
in particular the stack) __asm_flush_l3_cache() must be manually
implemented in assembly, rather than implemented in C since the compiler
won't know not to touch RAM.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 19 Oct 2016 21:18:44 +0000 (15:18 -0600)]
ARM: tegra: ensure nvtboot_boot_x0 alignment
nvtboot_boot_x0 is a 64-bit variable and hence must be 64-bit aligned.
So far this has happened by accident! Fix the code so this is guaranteed.
This fixes the following build error:
... relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC
against symbol `nvtboot_boot_x0' ...
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Rini [Mon, 7 Nov 2016 18:16:00 +0000 (13:16 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-net
Siva Durga Prasad Paladugu [Wed, 2 Nov 2016 11:52:13 +0000 (12:52 +0100)]
net: use random ethernet address if invalid and not zero
Use random ethernet address if the ethernet address found
is invalid, not zero and config for random address
is defined.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Chris Packham [Mon, 31 Oct 2016 21:48:32 +0000 (10:48 +1300)]
net: mvgbe: Fix build error with CONFIG_PHYLIB
Commit
5a49f17481bb ("net: mii: Use spatch to update miiphy_register")
updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to
that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to
satisfy the phylib APIs. Because these functions weren't updated in that
commit build errors where triggered when CONFIG_PHYLIB was enabled.
Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write
and using smi_reg_read/smi_reg_write directly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Ash Charles [Fri, 21 Oct 2016 21:31:33 +0000 (17:31 -0400)]
net: phy: micrel: center FLP burst timing at 16ms
Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms
specified by the IEEE802.3 standard from the chip's default of 8ms.
For more details, see the "Auto-Negotiation Timing" section of the
KSZ9031RNX datasheet.
[1] https://patchwork.kernel.org/patch/
6558371/
Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Mon, 12 Sep 2016 17:51:15 +0000 (11:51 -0600)]
ARM: tegra: enable Ethernet on p2771-0000
Enable the Ethernet device in DT, provide board-specific configuration,
and enable the driver in Kconfig.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Mon, 12 Sep 2016 17:51:14 +0000 (11:51 -0600)]
ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DT
Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the
Tegra186 SoC DT so that boards can make use of it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Mon, 12 Sep 2016 17:51:13 +0000 (11:51 -0600)]
ARM: tegra: configure Ethernet address on Tegra186
On Tegra186, the bootloader which runs before U-Boot passes the Ethernet
MAC address to U-Boot using device tree. Extract this value and write it
to the environment, so that the Ethernet uclass picks it up and uses it
for the built-in Ethernet device.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Mon, 12 Sep 2016 17:51:12 +0000 (11:51 -0600)]
ARM: tegra: add SoC-level hook for board_late_init()
Extend the Tegra186 implementation of board_late_init() to call a per-SoC
"hook" function. This will allow SoC-specific (rather than Tegra-wide)
functionality to be implemented without the core Tegra code needing to be
aware of the details. While board186.c is currently only used for
Tegra186, it should be applicable to any other future SoC, and perhaps its
simple design could be back-ported to older SoCs in the future too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Fri, 21 Oct 2016 20:46:47 +0000 (14:46 -0600)]
net: add driver for Synopsys Ethernet QoS device
This driver supports the Synopsys Designware Ethernet QoS (Quality of
Service) a/k/a eqos IP block, which is a different design than the HW
supported by the existing designware.c driver. The IP supports many
options for bus type, clocking/reset structure, and feature list. This
driver currently supports the specific configuration used in NVIDIA's
Tegra186 chip, but should be extensible to other combinations quite
easily, as explained in the source.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org> # V1
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Fri, 21 Oct 2016 20:46:46 +0000 (14:46 -0600)]
dt: net: add DWC EQoS binding
The Synopsys DWC EQoS is a configurable Ethernet MAC/DMA IP block which
supports multiple options for bus type, clocking and reset structure, and
feature list.
This patch imports the binding from the Linux kernel, including my V3
patch to extend the binding to cover the Tegra186, which is applied for
next-
20160912. So far, my changes have been acked by Lars Persson, the
original author of the binding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fabio Estevam [Tue, 1 Nov 2016 16:58:16 +0000 (14:58 -0200)]
wandboard: Make Ethernet functional again
Since commit
ce412b79e7255770 ("drivers: net: phy: atheros: add separate
config for AR8031") ethernet does not work on mx6sabresd.
This commit correctly assigns ar8031_config() as the configuration
function for AR8031 in the same way as done in the Linux kernel.
However, on wandboard design we need some additional configuration,
such as enabling the 125 MHz AR8031 output that needs to be done
in the board file.
This also aligns with the same method that the kernel performs
the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tomeu Vizoso [Fri, 4 Nov 2016 13:22:15 +0000 (14:22 +0100)]
mkimage: Allow including a ramdisk in FIT auto mode
Adds -i option that allows specifying a ramdisk file to be added to the
FIT image when we are using the automatic FIT mode (no ITS file).
This makes adding Depthcharge support to LAVA much more convenient, as
no additional configuration files need to be kept around in the machine
that dispatches jobs to the boards.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Matt Hart <matthew.hart@linaro.org>
Cc: Neil Williams <codehelp@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>