oweals/u-boot.git
10 years agopmic: pmic_pfuze100: Use a shorter name for PMIC name
Fabio Estevam [Fri, 1 Aug 2014 11:50:03 +0000 (08:50 -0300)]
pmic: pmic_pfuze100: Use a shorter name for PMIC name

It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already
know it is a PMIC.

Call it simply 'PFUZE100' instead.

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED
Fabio Estevam [Fri, 1 Aug 2014 11:50:02 +0000 (08:50 -0300)]
mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED

According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of
register CCM_CIMR corresponds to bit 19 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definition
Fabio Estevam [Fri, 1 Aug 2014 11:50:01 +0000 (08:50 -0300)]
mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definition

According to the Reference Manual the 'wb_per_at_lpm' field of register
CCM_CLPCR corresponds to bit 16 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offset
Fabio Estevam [Fri, 1 Aug 2014 11:50:00 +0000 (08:50 -0300)]
mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offset

According to the Reference Manual the 'spdif0_clk_podf' field of register
CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset
definitions accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agomx6: imx-regs: Remove unused 'omux' field from iomux struct
Fabio Estevam [Fri, 1 Aug 2014 11:49:59 +0000 (08:49 -0300)]
mx6: imx-regs: Remove unused 'omux' field from iomux struct

'omux' field is not used anywhere and such layout is not valid for mx6solox.

Instead of adding more ifdef's into the structure, let's simply remove this
unused 'omux' field.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agoarm: m53evk: Fix RTC bus number
Marek Vasut [Fri, 25 Jul 2014 15:23:35 +0000 (17:23 +0200)]
arm: m53evk: Fix RTC bus number

A previous update to the I2C stack introduced a typo in the
configuration option. Fix the typo and therefore allow the
RTC to work correctly with the 'date' command again.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
10 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Stefano Babic [Fri, 8 Aug 2014 08:18:40 +0000 (10:18 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

10 years agoARM: HYP/non-sec: remove MIDR check to validate CBAR
Marc Zyngier [Sat, 12 Jul 2014 13:24:08 +0000 (14:24 +0100)]
ARM: HYP/non-sec: remove MIDR check to validate CBAR

Having a form of whitelist to check if we know of a CPU core
and and obtain CBAR is a bit silly.

It doesn't scale (how about A12, A17, as well as other I don't know
about?), and is actually a property of the SoC, not the core.

So either it works and everybody is happy, or it doesn't and
the u-boot port to this SoC is providing the real address via
a configuration option.

The result of the above is that this code doesn't need to exist,
is thus forcefully removed.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: HYP/non-sec/PSCI: emit DT nodes
Marc Zyngier [Sat, 12 Jul 2014 13:24:07 +0000 (14:24 +0100)]
ARM: HYP/non-sec/PSCI: emit DT nodes

Generate the PSCI node in the device tree.

Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: convert arch_fixup_memory_node to a generic FDT fixup function
Ma Haijun [Sat, 12 Jul 2014 13:24:06 +0000 (14:24 +0100)]
ARM: convert arch_fixup_memory_node to a generic FDT fixup function

Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.

[maz: collapsed 3 patches into one, rewrote commit message]

Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: HYP/non-sec: add the option for a second-stage monitor
Marc Zyngier [Sat, 12 Jul 2014 13:24:05 +0000 (14:24 +0100)]
ARM: HYP/non-sec: add the option for a second-stage monitor

Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: HYP/non-sec: add generic ARMv7 PSCI code
Marc Zyngier [Sat, 12 Jul 2014 13:24:04 +0000 (14:24 +0100)]
ARM: HYP/non-sec: add generic ARMv7 PSCI code

Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: HYP/non-sec: allow relocation to secure RAM
Marc Zyngier [Sat, 12 Jul 2014 13:24:03 +0000 (14:24 +0100)]
ARM: HYP/non-sec: allow relocation to secure RAM

The current non-sec switching code suffers from one major issue:
it cannot run in secure RAM, as a large part of u-boot still needs
to be run while we're switched to non-secure.

This patch reworks the whole HYP/non-secure strategy by:
- making sure the secure code is the *last* thing u-boot executes
  before entering the payload
- performing an exception return from secure mode directly into
  the payload
- allowing the code to be dynamically relocated to secure RAM
  before switching to non-secure.

This involves quite a bit of horrible code, specially as u-boot
relocation is quite primitive.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: HYP/non-sec: add separate section for secure code
Marc Zyngier [Sat, 12 Jul 2014 13:24:02 +0000 (14:24 +0100)]
ARM: HYP/non-sec: add separate section for secure code

In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.

Nothing is using it just yet.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: add missing HYP mode constant
Marc Zyngier [Sat, 12 Jul 2014 13:24:01 +0000 (14:24 +0100)]
ARM: add missing HYP mode constant

In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.

Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: non-sec: reset CNTVOFF to zero
Marc Zyngier [Sat, 12 Jul 2014 13:24:00 +0000 (14:24 +0100)]
ARM: non-sec: reset CNTVOFF to zero

Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: HYP/non-sec: add a barrier after setting SCR.NS==1
Marc Zyngier [Sat, 12 Jul 2014 13:23:59 +0000 (14:23 +0100)]
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoARM: HYP/non-sec: move switch to non-sec to the last boot phase
Marc Zyngier [Sat, 12 Jul 2014 13:23:58 +0000 (14:23 +0100)]
ARM: HYP/non-sec: move switch to non-sec to the last boot phase

Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
10 years agoMerge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 28 Jul 2014 10:26:21 +0000 (12:26 +0200)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

10 years agoMerge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 28 Jul 2014 08:54:54 +0000 (10:54 +0200)]
Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'

10 years agoMerge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 28 Jul 2014 08:12:45 +0000 (10:12 +0200)]
Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'

10 years agoMerge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'
Albert ARIBAUD [Sat, 26 Jul 2014 12:08:36 +0000 (14:08 +0200)]
Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'

10 years agoARM: omap: move board specific NAND configs out from ti_armv7_common.h
pekon gupta [Fri, 18 Jul 2014 12:29:42 +0000 (17:59 +0530)]
ARM: omap: move board specific NAND configs out from ti_armv7_common.h

This patch moves some board specific NAND configs:
- FROM: generic config file 'ti_armv7_common.h'
- TO:   individual board config files using these configs.
So that each board can independently set the value as per its design.

Following configs are affected in this patch:
  CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
  CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon>
  CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
  CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>

This patch also updates documentation for few of above NAND configs.

Signed-off-by: Pekon Gupta <pekon@ti.com>
10 years agoARM: omap: clean redundant PISMO_xx macros used in OMAP3
pekon gupta [Fri, 18 Jul 2014 12:29:41 +0000 (17:59 +0530)]
ARM: omap: clean redundant PISMO_xx macros used in OMAP3

PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
  by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
  merging of common platform code in following commit
      commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
      ARM: omap: merge GPMC initialization code for all platform

+-----------------+-----------------------------------------------------------+
| Macro           | Reason for removal                                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE                         |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE                      |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so     |
|                 | configuring GPMC chip-select for smallest allowable       |
|                 | segment (GPMC_SIZE_16M) is enough.                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of    |
|                 | 128MB (GPMC_SIZE_128M)                                    |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR      |  Unused Macros                                            |
| PISMO1_NAND     |                                                           |
| PISMO2_CS0      |                                                           |
| PISMO2_CS1      |                                                           |
| PISMO1_ONENAND  |                                                           |
| PISMO2_NAND_CS0 |                                                           |
| PISMO2_NAND_CS1 |                                                           |
| PISMO1_NOR_BASE |                                                           |
| PISMO1_NAND_BASE|                                                           |
| PISMO2_CS0_BASE |                                                           |
+-----------------+-----------------------------------------------------------+

Signed-off-by: Pekon Gupta <pekon@ti.com>
10 years agoARM: omap: fix GPMC address-map size for NAND and NOR devices
pekon gupta [Fri, 18 Jul 2014 12:29:40 +0000 (17:59 +0530)]
ARM: omap: fix GPMC address-map size for NAND and NOR devices

Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
    ARM: omap: merge GPMC initialization code for all platform

1) NAND device are not directly memory-mapped to CPU address-space, they are
 indirectly accessed via following GPMC registers:
 - GPMC_NAND_COMMAND_x
 - GPMC_NAND_ADDRESS_x
 - GPMC_NAND_DATA_x
 Therefore from CPU's point of view, NAND address-map can be limited to just
 above register addresses. But GPMC chip-select address-map can be configured
 in granularity of 16MB only.
 So this patch uses GPMC_SIZE_16M for all NAND devices.

2) NOR device are directly memory-mapped to CPU address-space, so its
 address-map size depends on actual addressable region in NOR FLASH device.
 So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
 size configuration.

Signed-off-by: Pekon Gupta <pekon@ti.com>
10 years agoARM: OMAP: Fix handling of errata i727
Rajendra Nayak [Fri, 18 Jul 2014 05:48:48 +0000 (11:18 +0530)]
ARM: OMAP: Fix handling of errata i727

The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5
ES 1.0 devices. The current revision check erroneously implements this
on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance)
infact causes an asynchronous abort and ends up masking it in CPSR,
only to be uncovered once the kernel switches to userspace.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
10 years agoboard: k2e-evm: add board support
Hao Zhang [Tue, 15 Jul 2014 21:59:27 +0000 (00:59 +0300)]
board: k2e-evm: add board support

This patch adds Keystone2 k2e_evm evaluation board support.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone2: spl: add K2E SoC support
Khoronzhuk, Ivan [Tue, 15 Jul 2014 21:59:26 +0000 (00:59 +0300)]
ARM: keystone2: spl: add K2E SoC support

Keystone2 K2E SoC has slightly different spl pll settings then
K2HK, so correct this.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agokeystone2: use CONFIG_SOC_KEYSTONE in common places
Khoronzhuk, Ivan [Tue, 15 Jul 2014 21:59:25 +0000 (00:59 +0300)]
keystone2: use CONFIG_SOC_KEYSTONE in common places

Use CONFIG_SOC_KEYSTONE in common places instead of defining
a lot of "if def .. || if def " for different Keystone2 SoC types.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone2: add MSMC cache coherency support for K2E SOC
Hao Zhang [Tue, 15 Jul 2014 21:59:24 +0000 (00:59 +0300)]
ARM: keystone2: add MSMC cache coherency support for K2E SOC

This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone2: clock: add K2E clock support
Hao Zhang [Tue, 15 Jul 2014 21:59:23 +0000 (00:59 +0300)]
ARM: keystone2: clock: add K2E clock support

This patch adds clock definitions and commands to support Keystone2
K2E SOC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone2: add K2E SoC hardware definitions
Hao Zhang [Tue, 15 Jul 2014 21:59:22 +0000 (00:59 +0300)]
ARM: keystone2: add K2E SoC hardware definitions

This patch adds hardware definitions specific to Keystone II
K2E device. It has a lot common definitions with k2hk SoC, so
move them to common hardware.h. This is preparation patch for
adding K2E SoC support.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agokeystone: ddr3: move K2HK DDR3 configuration to a common file
Hao Zhang [Wed, 9 Jul 2014 20:44:49 +0000 (23:44 +0300)]
keystone: ddr3: move K2HK DDR3 configuration to a common file

It's convenient to hold configurations for DDR3 PHY and EMIF in
separate common place. This patch moves K2HK DDR3 PHY and EMIF
configuration data with different rates and memory size to a common
ddr3_cfg.c file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoconfigs: k2hk_evm: config: add common EVM configuration header
Hao Zhang [Wed, 9 Jul 2014 20:44:48 +0000 (23:44 +0300)]
configs: k2hk_evm: config: add common EVM configuration header

This patch adds a common config header file for all the Keystone II
EVM platforms. It combines a lot of general definitions in one file.
The common header included in the EVM should be specific configuration
header.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone: clock: move K2HK SoC dependent code in separate file
Khoronzhuk, Ivan [Wed, 9 Jul 2014 20:44:47 +0000 (23:44 +0300)]
ARM: keystone: clock: move K2HK SoC dependent code in separate file

This patch in general spit SoC type clock dependent code and general
clock code. Before adding keystone II Edison k2e SoC which has
slightly different dpll set, move k2hk dependent clock code to
separate clock-k2hk.c file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone2: move K2HK board files to common KS2 board directory
Hao Zhang [Wed, 9 Jul 2014 20:44:46 +0000 (23:44 +0300)]
ARM: keystone2: move K2HK board files to common KS2 board directory

This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agokeystone2: add env option to do unitrd dt fixup
Murali Karicheri [Wed, 9 Jul 2014 20:44:45 +0000 (23:44 +0300)]
keystone2: add env option to do unitrd dt fixup

With latest v3.13 kernel, unitrd dt fixup is not needed. However for
older kernel versions such as v3.8/v3.10, it is needed. So to work
with both, add a u-boot env variable that can be set to do dt fixup
for older kernels.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agok2hk: use common KS2_ prefix for all hardware definitions
Khoronzhuk, Ivan [Wed, 9 Jul 2014 20:44:44 +0000 (23:44 +0300)]
k2hk: use common KS2_ prefix for all hardware definitions

Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agokeystone2: add possibility to turn off all dsps
Hao Zhang [Wed, 9 Jul 2014 16:48:44 +0000 (19:48 +0300)]
keystone2: add possibility to turn off all dsps

By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agokeystone2: move cpu_to_bus() to keystone.c
Hao Zhang [Wed, 9 Jul 2014 16:48:43 +0000 (19:48 +0300)]
keystone2: move cpu_to_bus() to keystone.c

The SoC related common functions in board.c should be placed to
a common keystone.c arch file.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone2: keystone_nav: make it dependent on keystone driver
Khoronzhuk, Ivan [Wed, 9 Jul 2014 16:48:42 +0000 (19:48 +0300)]
ARM: keystone2: keystone_nav: make it dependent on keystone driver

This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agokeystone2: ddr: add DDR3 PHY configs updated for PG 2.0
Hao Zhang [Wed, 9 Jul 2014 16:48:41 +0000 (19:48 +0300)]
keystone2: ddr: add DDR3 PHY configs updated for PG 2.0

Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agokeystone: ddr3: add ddr3.h to hold ddr3 API
Khoronzhuk, Ivan [Wed, 9 Jul 2014 16:48:40 +0000 (19:48 +0300)]
keystone: ddr3: add ddr3.h to hold ddr3 API

It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: keystone2: psc: use common PSC base
Khoronzhuk, Ivan [Wed, 9 Jul 2014 16:48:39 +0000 (19:48 +0300)]
ARM: keystone2: psc: use common PSC base

Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agoARM: omap: tao3530: Convert to generic board
Stefan Roese [Wed, 9 Jul 2014 15:18:11 +0000 (17:18 +0200)]
ARM: omap: tao3530: Convert to generic board

Use generic board setup functions by defining
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
10 years agoARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c
Stefan Roese [Wed, 9 Jul 2014 15:18:10 +0000 (17:18 +0200)]
ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c

These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
10 years agoARM: omap: Fix GPMC init for OMAP3 platforms
Stefan Roese [Wed, 9 Jul 2014 15:18:09 +0000 (17:18 +0200)]
ARM: omap: Fix GPMC init for OMAP3 platforms

Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.

Tested on TAO3530 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
10 years agotricorder: convert to generic board
Andreas Bießmann [Wed, 9 Jul 2014 15:10:34 +0000 (17:10 +0200)]
tricorder: convert to generic board

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Thomas Weber <thomas.weber@corscience.de>
10 years agoam335x_evm / gumstix pepper: Correct DDR settings
Tom Rini [Tue, 8 Jul 2014 01:40:16 +0000 (21:40 -0400)]
am335x_evm / gumstix pepper: Correct DDR settings

As noted by clang, we have been shifting certain values out of 32bit
range when setting some DDR registers.  Upon further inspection these
had been touching reserved fields (and having no impact).  These came in
from historical bring-up code and can be discarded.  Similarly, we had
been declaring some fields as 0 when they will be initialized that way.
Tested on Beaglebone White.

Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-By: Ash Charles <ashcharles@gmail.com>
10 years agok2hk_evm: add script to automate NAND flash process
Khoronzhuk, Ivan [Fri, 4 Jul 2014 12:03:27 +0000 (15:03 +0300)]
k2hk_evm: add script to automate NAND flash process

Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
10 years agokeystone: add support for NAND gpheader image
Khoronzhuk, Ivan [Fri, 4 Jul 2014 12:03:26 +0000 (15:03 +0300)]
keystone: add support for NAND gpheader image

Add support for NAND gpheader image. TI Keystone2 ROM bootloader
expects 8 bytes of trailing zeroes in the nand u-boot image.
So add zeros at the end of the nand gph image.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agomtd: nand: davinci: add opportunity to write keystone U-boot image
Khoronzhuk, Ivan [Fri, 4 Jul 2014 12:03:25 +0000 (15:03 +0300)]
mtd: nand: davinci: add opportunity to write keystone U-boot image

The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.

The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.

The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.

Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 years agotps65218/am43xx_evm: Add power framework support to TPS65218
Tom Rini [Mon, 23 Jun 2014 20:06:29 +0000 (16:06 -0400)]
tps65218/am43xx_evm: Add power framework support to TPS65218

Add in an init function for the drivers/power framework so we can dump
and read the registers via i2c.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
10 years agopower/pmic.h: Add prototype for power_init_board.
Tom Rini [Mon, 23 Jun 2014 20:06:28 +0000 (16:06 -0400)]
power/pmic.h: Add prototype for power_init_board.

As this is a weak function that we may override, provide a prototype for
it.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
10 years agoARM: dra7_evm: Add Ethernet support for dra72x platform
Mugunthan V N [Thu, 22 May 2014 09:07:12 +0000 (14:37 +0530)]
ARM: dra7_evm: Add Ethernet support for dra72x platform

Set the active_slave to 1 as slave 1 is pinned out in dra72x base board

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
10 years agoARM: DRA7xx: Add cpsw second port pinmux
Mugunthan V N [Thu, 22 May 2014 09:07:11 +0000 (14:37 +0530)]
ARM: DRA7xx: Add cpsw second port pinmux

Add cpsw second slave port pinmux to use it as primary ethernet port

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
10 years agodrivers: net: cpsw: add support for using second port as ethernet
Mugunthan V N [Thu, 22 May 2014 09:07:10 +0000 (14:37 +0530)]
drivers: net: cpsw: add support for using second port as ethernet

Add support for using the second slave port of cpsw
to be used as primary ethernet.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
10 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Fri, 25 Jul 2014 19:05:09 +0000 (15:05 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

10 years agoarm: rmobile: Add support Alt board
Nobuhiro Iwamatsu [Thu, 26 Jun 2014 01:23:30 +0000 (10:23 +0900)]
arm: rmobile: Add support Alt board

The alt board has R8A7794, 1GB DDR3-SDRAM, USB, Ethernet, QSPI,
MMC, SDHI and more.

This commit supports the following functions:
 - DDR3-SDRAM
 - SCIF
 - I2C
 - Ethernet
 - QSPI

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
10 years agoarm: rmobile: Add support R8A7794
Nobuhiro Iwamatsu [Tue, 24 Jun 2014 08:10:02 +0000 (17:10 +0900)]
arm: rmobile: Add support R8A7794

Renesas R8A7794 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
10 years agoserial: sh: Add support R8A7794
Nobuhiro Iwamatsu [Tue, 24 Jun 2014 08:03:20 +0000 (17:03 +0900)]
serial: sh: Add support R8A7794

This adds the preset value to register for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
10 years agonet: sh-eth: Add support R8A7794
Nobuhiro Iwamatsu [Tue, 24 Jun 2014 08:01:08 +0000 (17:01 +0900)]
net: sh-eth: Add support R8A7794

R8A7794 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
10 years agosh: unify sh2/sh3/sh4 linker scripts
Masahiro Yamada [Fri, 20 Jun 2014 07:40:14 +0000 (16:40 +0900)]
sh: unify sh2/sh3/sh4 linker scripts

The linker scripts of sh2/sh3/sh4 are almost the same.
The difference among them is essentially only one line.

They can be consolidated into a single file, arch/sh/cpu/u-boot.lds
by re-writing the diffrent line as follows:

KEEP(*/start.o (.text))

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
10 years agobuildman: Avoid retrying a build if it definitely failed
Simon Glass [Sun, 13 Jul 2014 20:03:41 +0000 (14:03 -0600)]
buildman: Avoid retrying a build if it definitely failed

After a build fails buildman will reconfigure and try again, if it did not
reconfigure before the build. However it doesn't actually keep track of
whether it did reconfigure on the previous attempt.

Fix that logic to avoid a pointless rebuild. This speeds things up quite a
bit for failing builds. Previously they would always be built twice.

Change-Id: Ib37f21320baa7c60bed98f4042c0b7ed7c0dc85e
Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agobuildman: Add -F flag to retry failed builds
Simon Glass [Sun, 13 Jul 2014 18:22:31 +0000 (12:22 -0600)]
buildman: Add -F flag to retry failed builds

Generally a build failure with a particular commit cannot be fixed except
by changing that commit. Changing the commit will automatically cause
buildman to retry when you run it again: buildman sees that the commit
hash is different and that it has no previous build result for the new
commit hash.

However sometimes the build failure is due to a toolchain issue or some
other environment problem. In that case, retrying failed builds may yield
a different result.

Add a flag to retry failed builds. This differs from the force rebuild
flag (-f) in that it will not rebuild commits which are already marked as
succeeded.

Series-to: u-boot

Change-Id: Iac4306df499d65ff0888b1c60f06fc162a6faad8

10 years agozynq: disable -Wstrict-prototypes option for ps7_init.c
Masahiro Yamada [Thu, 29 May 2014 05:46:13 +0000 (14:46 +0900)]
zynq: disable -Wstrict-prototypes option for ps7_init.c

The files ps7_init.c and ps7_init.h are supposed to be generated by
hw projects such as Vivado, PlanAhead and then to be copied into
board/xilinx/zynq directory.

But some prototypes in them cause annoying warning messages:

  CC      spl/board/xilinx/zynq/ps7_init.o
In file included from board/xilinx/zynq/ps7_init.c:50:0:
board/xilinx/zynq/ps7_init.h:137:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.h:138:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.h:139:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.h:145:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12602:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12723:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12742:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12761:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12854:6: warning: function declaration isn't a prototype [-Wstrict-prototypes]

The prototypes should be

  int ps7_init(void);
  int ps7_post_config(void);
  int ps7_debug(void);

rather than

  int ps7_init();
  int ps7_post_config();
  int ps7_debug();

We do not want to be bothered because of automatically generated files.
But we cannot touch the external projects for now.
What we can do is to disable -Wstrict-prototypes for ps7_init.c

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
10 years agoARM: zynq: Show ECC status on the same line as DRAM size
Michal Simek [Thu, 15 May 2014 07:40:14 +0000 (09:40 +0200)]
ARM: zynq: Show ECC status on the same line as DRAM size

Without this patch is DRAM size one line below DRAM:
which is not nice

Origin:
I2C:   ready
DRAM:  Memory: ECC disabled
1 GiB
MMC:   zynq_sdhci: 0

Fixed by this patch:
I2C:   ready
DRAM:  ECC disabled 1 GiB
MMC:   zynq_sdhci: 0

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
10 years agoARM: zynq: Enable generic board for Xilinx Zynq
Michal Simek [Thu, 8 May 2014 13:10:48 +0000 (15:10 +0200)]
ARM: zynq: Enable generic board for Xilinx Zynq

Enable CONFIG_SYS_GENERIC_BOARD for all Zynq boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board]
10 years agodm: Give the demo uclass a name
Simon Glass [Wed, 23 Jul 2014 12:55:24 +0000 (06:55 -0600)]
dm: Give the demo uclass a name

Uclasses should be named, so add a name for the demo uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Add dm_scan_other() to locate board-specific devices
Simon Glass [Wed, 23 Jul 2014 12:55:23 +0000 (06:55 -0600)]
dm: Add dm_scan_other() to locate board-specific devices

Some boards will have devices which are not in the device tree and do not
have platform data. They may be programnatically created, for example.
Add a hook which boards can use to bind those devices early in boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Improve errors and warnings in lists_bind_fdt()
Simon Glass [Wed, 23 Jul 2014 12:55:22 +0000 (06:55 -0600)]
dm: Improve errors and warnings in lists_bind_fdt()

Add a debug message for when a device tree node has no driver. Also reword
the warning when a device fails to bind, which was misleading.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Add child_pre_probe() and child_post_remove() methods
Simon Glass [Wed, 23 Jul 2014 12:55:21 +0000 (06:55 -0600)]
dm: Add child_pre_probe() and child_post_remove() methods

Some devices (particularly bus devices) must track their children, knowing
when a new child is added so that it can be set up for communication on the
bus.

Add a child_pre_probe() method to provide this feature, and a corresponding
child_post_remove() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Introduce per-child data for devices
Simon Glass [Wed, 23 Jul 2014 12:55:20 +0000 (06:55 -0600)]
dm: Introduce per-child data for devices

Some device types can have child devices and want to store information
about them. For example a USB flash stick attached to a USB host
controller would likely use this space. The controller can hold
information about the USB state of each of its children.

The data is stored attached to the child device in the 'parent_priv'
member. It can be auto-allocated by dm when the child is probed. To
do this, add a per_child_auto_alloc_size value to the parent driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Add functions to access a device's children
Simon Glass [Wed, 23 Jul 2014 12:55:19 +0000 (06:55 -0600)]
dm: Add functions to access a device's children

Devices can have childen that can be addressed by a simple index, the
sequence number or a device tree offset. Add functions to access a child
in each of these ways.

The index is typically used as a fallback when the sequence number is not
available. For example we may use a serial UART with sequence number 0 as
the console, but if no UART has sequence number 0, then we can fall back
to just using the first UART (index 0).

The device tree offset function is useful for buses, where they want to
locate one of their children. The device tree can be scanned to find the
offset of each child, and that offset can then find the device.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Provide a function to scan child FDT nodes
Simon Glass [Wed, 23 Jul 2014 12:55:18 +0000 (06:55 -0600)]
dm: Provide a function to scan child FDT nodes

At present only root nodes in the device tree are scanned for devices.
But some devices can have children. For example a SPI bus may have
several children for each of its chip selects.

Add a function which scans subnodes and binds devices for each one. This
can be used for the root node scan also, so change it.

A device can call this function in its bind() or probe() methods to bind
its children.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Tidy up some header file comments
Simon Glass [Wed, 23 Jul 2014 12:55:17 +0000 (06:55 -0600)]
dm: Tidy up some header file comments

Fix up the style of a few comments and add/clarify a few others.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agofdt: Add a function to get the node offset of an alias
Simon Glass [Wed, 23 Jul 2014 12:55:16 +0000 (06:55 -0600)]
fdt: Add a function to get the node offset of an alias

This simple function returns the node offset of a named alias.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Avoid accessing uclasses before they are ready
Simon Glass [Wed, 23 Jul 2014 12:55:15 +0000 (06:55 -0600)]
dm: Avoid accessing uclasses before they are ready

Don't allow access to uclasses before they have been initialised.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Allow a device to be found by its FDT offset
Simon Glass [Wed, 23 Jul 2014 12:55:14 +0000 (06:55 -0600)]
dm: Allow a device to be found by its FDT offset

Each device that was bound from a device tree has an node that caused it to
be bound. Add functions that find and return a device based on a device tree
offset.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Display the sequence number for each device
Simon Glass [Wed, 23 Jul 2014 12:55:13 +0000 (06:55 -0600)]
dm: Display the sequence number for each device

Add this information to 'dm tree' and 'dm uclass' commands.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Introduce device sequence numbering
Simon Glass [Wed, 23 Jul 2014 12:55:12 +0000 (06:55 -0600)]
dm: Introduce device sequence numbering

In U-Boot it is pretty common to number devices from 0 and access them
on the command line using this numbering. While it may come to pass that
we will move away from this numbering, the possibility seems remote at
present.

Given that devices within a uclass will have an implied numbering, it
makes sense to build this into driver model as a core feature. The cost
is fairly small in terms of code and data space.

With each uclass having numbered devices we can ask for SPI port 0 or
serial port 1 and receive a single device.

Devices typically request a sequence number using aliases in the device
tree. These are resolved when the device is probed, to deal with conflicts.
Sequence numbers need not be sequential and holes are permitted.

At present there is no support for sequence numbers using static platform
data. It could easily be added to 'struct driver_info' if needed, but it
seems better to add features as we find a use for them, and the use of -1
to mean 'no sequence' makes the default value somewhat painful.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Avoid activating devices in 'dm uclass' command
Simon Glass [Wed, 23 Jul 2014 12:55:11 +0000 (06:55 -0600)]
dm: Avoid activating devices in 'dm uclass' command

This command currently activates devices as it lists them. This is not
desirable since it changes the system state. Fix it and avoid printing
a newline if there are no devices in a uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Move device display into its own function
Simon Glass [Wed, 23 Jul 2014 12:55:10 +0000 (06:55 -0600)]
dm: Move device display into its own function

The device display for 'dm tree' and 'dm uclass' is mostly the same, so
move it into a common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agofdt: Add a function to get the alias sequence of a node
Simon Glass [Wed, 23 Jul 2014 12:55:09 +0000 (06:55 -0600)]
fdt: Add a function to get the alias sequence of a node

Aliases are used to provide U-Boot's numbering of devices, such as:

aliases {
spi0 = "/spi@12330000";
}

spi@12330000 {
...
}

This tells us that the SPI controller at 12330000 is considered to be the
first SPI controller (SPI 0). So we have a numbering for the SPI node.

Add a function that returns the numbering for a node assume that it exists
in the list of aliases.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Move uclass error checking/probing into a function
Simon Glass [Wed, 23 Jul 2014 12:55:08 +0000 (06:55 -0600)]
dm: Move uclass error checking/probing into a function

Several functions will use this same pattern, so bring it into a function.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agoAdd a flag indicating when the serial console is ready
Simon Glass [Wed, 23 Jul 2014 12:55:07 +0000 (06:55 -0600)]
Add a flag indicating when the serial console is ready

For sandbox we have a fallback console which is used very early in
U-Boot, before serial drivers are available. Rather than try to guess
when to switch to the real console, add a flag so we can be sure. This
makes sure that sandbox can always output a panic() message, for example,
and avoids silent failure (which is very annoying in sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agoconsole: Remove vprintf() optimisation for sandbox
Simon Glass [Wed, 23 Jul 2014 12:55:06 +0000 (06:55 -0600)]
console: Remove vprintf() optimisation for sandbox

If the console is not present, we try to reduce overhead by stopping any
output in vprintf(), before it gets to putc(). This is of dubious merit
in general, but in the case of sandbox it is incorrect since we have a
fallback console which reports errors very early in U-Boot. If this is
defeated U-Boot can hang or exit with no indication of what is wrong.

Remove the optimisation for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agostdio: Provide functions to add/remove devices using stdio_dev
Simon Glass [Wed, 23 Jul 2014 12:55:05 +0000 (06:55 -0600)]
stdio: Provide functions to add/remove devices using stdio_dev

The current functions for adding and removing devices require a device name.
This is not convenient for driver model, which wants to store a pointer to
the relevant device. Add new functions which provide this feature and adjust
the old ones to call these.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Support driver model prior to relocation
Simon Glass [Wed, 23 Jul 2014 12:55:04 +0000 (06:55 -0600)]
dm: Support driver model prior to relocation

Initialise devices marked 'pre-reloc' and make them available prior to
relocation. Note that this requires pre-reloc malloc() to be available.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Allow drivers to be marked 'before relocation'
Simon Glass [Wed, 23 Jul 2014 12:55:03 +0000 (06:55 -0600)]
dm: Allow drivers to be marked 'before relocation'

Driver model currently only operates after relocation is complete. In this
state U-Boot typically has a small amount of memory available. In adding
support for driver model prior to relocation we must try to use as little
memory as possible.

In addition, on some machines the memory has not be inited and/or the CPU
is not running at full speed or the data cache is off. These can reduce
execution performance, so the less initialisation that is done before
relocation the better.

An immediately-obvious improvement is to only initialise drivers which are
actually going to be used before relocation. On many boards the only such
driver is a serial UART, so this provides a very large potential benefit.

Allow drivers to mark themselves as 'pre-reloc' which means that they will
be initialised prior to relocation. This can be done either with a driver
flag or with a 'dm,pre-reloc' device tree property.

To support this, the various dm scanning function now take a 'pre_reloc_only'
parameter which indicates that only drivers marked pre-reloc should be
bound.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agosandbox: Remove all drivers before exit
Simon Glass [Wed, 23 Jul 2014 12:55:02 +0000 (06:55 -0600)]
sandbox: Remove all drivers before exit

Drivers are supposed to be able to close down cleanly. To set a good example,
make sandbox shut down its driver model drivers and remove them before exit.

It may be desirable to do the same more generally once driver model is more
widely-used. This could be done during bootm, before U-Boot jumps to the OS.
It seems far too early to make this change.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: Provide a way to shut down driver model
Simon Glass [Wed, 23 Jul 2014 12:55:01 +0000 (06:55 -0600)]
dm: Provide a way to shut down driver model

Add a new method which removes and unbinds all drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
10 years agodm: Make sure that the root device is probed
Simon Glass [Wed, 23 Jul 2014 12:55:00 +0000 (06:55 -0600)]
dm: Make sure that the root device is probed

The root device should be probed just like any other device. The effect of
this is to mark the device as activated, so that it can be removed (along
with its children) if required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
10 years agostdio: Pass device pointer to stdio methods
Simon Glass [Wed, 23 Jul 2014 12:54:59 +0000 (06:54 -0600)]
stdio: Pass device pointer to stdio methods

At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.

For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.

Instead, add a stdio_dev pointer to each of the stdio member functions.

Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.

Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.

22: stdio: Pass device pointer to stdio methods
       arm: (for 2/2 boards)  all +244.0  bss -4.0  text +248.0
   powerpc: (for 1/1 boards)  all +428.0  text +428.0

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
10 years agostdio: Remove redundant code around stdio_register() calls
Simon Glass [Wed, 23 Jul 2014 12:54:58 +0000 (06:54 -0600)]
stdio: Remove redundant code around stdio_register() calls

There is no point in setting a structure's memory to NULL when it has
already been zeroed with memset().

Also, there is no need to create a stub function for stdio to call - if the
function is NULL it will not be called.

This is a clean-up, with no change in functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
10 years agodm: Use an explicit expect value in core tests
Simon Glass [Wed, 23 Jul 2014 12:54:57 +0000 (06:54 -0600)]
dm: Use an explicit expect value in core tests

Rather than reusing the 'reg' property, use an explicit property for the
expected ping value used in testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agodm: gpio: Don't use the driver model uclass for SPL
Simon Glass [Wed, 23 Jul 2014 12:54:56 +0000 (06:54 -0600)]
dm: gpio: Don't use the driver model uclass for SPL

Driver model does not support SPL yet, so we should not use the GPIO
uclass for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agosandbox: Always enable malloc debug
Simon Glass [Fri, 11 Jul 2014 04:23:33 +0000 (22:23 -0600)]
sandbox: Always enable malloc debug

Tun on DEBUG in malloc(). This adds code space and slows things down but
for sandbox this is acceptable. We gain the ability to check for memory
leaks in tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agosandbox: config: Enable pre-relocation malloc()
Simon Glass [Fri, 11 Jul 2014 04:23:32 +0000 (22:23 -0600)]
sandbox: config: Enable pre-relocation malloc()

Enable this for sandbox so that we will be able to use driver model before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agosandbox: Support pre-relocation malloc()
Simon Glass [Fri, 11 Jul 2014 04:23:31 +0000 (22:23 -0600)]
sandbox: Support pre-relocation malloc()

Set up and zero global data before board_init_f() is called so that we can
remove the need for CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: Simon Glass <sjg@chromium.org>