oweals/u-boot.git
8 years agoarm64: sunxi: adjust default load addresses
Andre Przywara [Wed, 4 May 2016 21:15:32 +0000 (22:15 +0100)]
arm64: sunxi: adjust default load addresses

As arm64 has slightly different expectations about load addresses, lets
use a different set of default addresses for things like the kernel.
As arm64 kernels don't come with a decompressor right now, reserve some
more space for really big uncompressed kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoRevert "sunxi: Reserve ATF memory space on A64"
Andre Przywara [Wed, 4 May 2016 21:15:30 +0000 (22:15 +0100)]
Revert "sunxi: Reserve ATF memory space on A64"

The ARM Trusted Firmware (ATF) code now lives in SRAM on the Pine64/A64,
so we can claim the whole of DRAM for OS use.

This reverts commit 3ffe39ed2b66af71c7271d0cef2a248b5bf7dfdb.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Properly announce BOOT_DEVICE_BOARD as "FEL"
Bernhard Nortmann [Sun, 3 Apr 2016 11:58:00 +0000 (13:58 +0200)]
sunxi: Properly announce BOOT_DEVICE_BOARD as "FEL"

This addresses a cosmetic issue when booting a sunxi device
over USB (FEL mode), where the SPL currently would just print
"Trying to boot from ". The patch fixes that to properly read
"Trying to boot from FEL".

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Increase SPL header size to 64 bytes to avoid code corruption
Siarhei Siamashka [Sat, 14 May 2016 01:13:26 +0000 (04:13 +0300)]
sunxi: Increase SPL header size to 64 bytes to avoid code corruption

The current SPL header, created by the 'mksunxiboot' tool, has size
32 bytes. But the code in the boot ROM stores the information about
the boot media at the offset 0x28 before passing control to the SPL.
For example, when booting from the SD card, the magic number written
by the boot ROM is 0. And when booting from the SPI flash, the magic
number is 3. NAND and eMMC probably have their own special magic
numbers too.

Currently the corrupted byte is a part of one of the instructions in
the reset vectors table:

    b     reset
    ldr   pc, _undefined_instruction
    ldr   pc, _software_interrupt      <- Corruption happens here
    ldr   pc, _prefetch_abort
    ldr   pc, _data_abort
    ldr   pc, _not_used
    ldr   pc, _irq
    ldr   pc, _fiq

In practice this does not cause any visible problems, but it's still
better to fix it. As a bonus, the reported boot media type can be
later used in the 'spl_boot_device' function, but this is out of
the scope of this patch.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: power: add AXP809 support
Chen-Yu Tsai [Mon, 2 May 2016 02:28:15 +0000 (10:28 +0800)]
sunxi: power: add AXP809 support

The A80 uses the AXP809 as its primary PMIC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Implement poweroff support for axp818 pmic
Chen-Yu Tsai [Mon, 2 May 2016 02:28:14 +0000 (10:28 +0800)]
sunxi: Implement poweroff support for axp818 pmic

Adds poweroff support for axp818 pmic.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Enable AXP818 SW for Sinovoip BPI M3
Chen-Yu Tsai [Mon, 2 May 2016 02:28:13 +0000 (10:28 +0800)]
sunxi: Enable AXP818 SW for Sinovoip BPI M3

The SW output of the PMIC supplies the ethernet PHY with power.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: power: axp818: Add support for switch SW
Chen-Yu Tsai [Mon, 2 May 2016 02:28:12 +0000 (10:28 +0800)]
sunxi: power: axp818: Add support for switch SW

The AXP818 has a switchable output, SW. This is commonly used for
controlling power to the LCD backlight.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agopower: axp818: Fix typo for fldo2 Kconfig description
Chen-Yu Tsai [Mon, 2 May 2016 02:28:11 +0000 (10:28 +0800)]
power: axp818: Fix typo for fldo2 Kconfig description

Description said eldo2 instead of fldo2, a copy-paste error.

Fixes: 38491d9c6515 ("power: axp818: Add support for FLDOs")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agopower: axp221: Remove switch case to simplify axp_set_eldo
Chen-Yu Tsai [Mon, 2 May 2016 02:28:10 +0000 (10:28 +0800)]
power: axp221: Remove switch case to simplify axp_set_eldo

The ELDO enable bits and registers are contiguous for axp221. Instead
of a switch case testing against the index, just use the index to shift
the bit or register offset.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Disable VIDEO for SoCs without display support
Chen-Yu Tsai [Mon, 2 May 2016 02:28:09 +0000 (10:28 +0800)]
sunxi: Disable VIDEO for SoCs without display support

The newer chips use a newer display pipeline, which is not supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Add default MMC0 card detect pin for A83T, H3 and A64 SoCs
Chen-Yu Tsai [Mon, 2 May 2016 02:28:08 +0000 (10:28 +0800)]
sunxi: Add default MMC0 card detect pin for A83T, H3 and A64 SoCs

A83T, H3, and A64 have a dedicated pin for card detect on the PF
pingroup. This is used in all designs. Set it as the default.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: Sort SoC variants by family (sunXi) first, chip name second
Chen-Yu Tsai [Mon, 2 May 2016 02:28:07 +0000 (10:28 +0800)]
sunxi: Sort SoC variants by family (sunXi) first, chip name second

In most other places, we sort SoC descriptions by family (sunXi) first,
then by the chip name (A20).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agosunxi: make SoC variant choice mandatory
Chen-Yu Tsai [Mon, 2 May 2016 02:28:06 +0000 (10:28 +0800)]
sunxi: make SoC variant choice mandatory

The user should always select an SoC variant to support. Not choosing
one doesn't make sense for a bootloader.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 24 May 2016 17:42:03 +0000 (13:42 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-net
Tom Rini [Tue, 24 May 2016 15:59:02 +0000 (11:59 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-net

Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
drivers/net/zynq_gem.c

8 years agonet: phy: dp83867: Add SGMII helper for configuration
Dan Murphy [Mon, 2 May 2016 20:46:02 +0000 (15:46 -0500)]
net: phy: dp83867: Add SGMII helper for configuration

The code assumed that if the interface is not RGMII configured
then it must be SGMII configured.  This device has the ability
to support most of the MII interfaces.  Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: phy: Add phy_interface_is_sgmii to phy.h
Dan Murphy [Mon, 2 May 2016 20:46:01 +0000 (15:46 -0500)]
net: phy: Add phy_interface_is_sgmii to phy.h

Add a helper to phy.h to identify whether the
phy is configured for SGMII all variables.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: phy: Move is_rgmii helper to phy.h
Dan Murphy [Mon, 2 May 2016 20:46:00 +0000 (15:46 -0500)]
net: phy: Move is_rgmii helper to phy.h

Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.

This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: phy: ti: Allow the driver to be more configurable
Dan Murphy [Mon, 2 May 2016 20:45:59 +0000 (15:45 -0500)]
net: phy: ti: Allow the driver to be more configurable

Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree.  If the value is not set in the
devicetree then set the delay to the default.

If devicetree is not used then use the default defines within the
driver.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: phy: dp83867: Add device tree bindings and documentation
Dan Murphy [Mon, 2 May 2016 20:45:58 +0000 (15:45 -0500)]
net: phy: dp83867: Add device tree bindings and documentation

Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.

The original document was from:
    [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: zynq_gem: Add the passing of the phy-handle node
Dan Murphy [Mon, 2 May 2016 20:45:57 +0000 (15:45 -0500)]
net: zynq_gem: Add the passing of the phy-handle node

Add the ability to pass the phy-handle node offset
to the phy driver.  This allows the phy driver
to access the DT subnode's data and parse accordingly.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodrivers: net: cpsw: Add reading of DT phy-handle node
Dan Murphy [Mon, 2 May 2016 20:45:56 +0000 (15:45 -0500)]
drivers: net: cpsw: Add reading of DT phy-handle node

Add the ability to read the phy-handle node of the
cpsw slave.  Upon reading this handle the phy-id
can be stored based on the reg node in the DT.

The phy-handle also needs to be stored and passed
to the phy to access any phy data that is available.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodefconfig: dra74_evm: enable eth driver model
Mugunthan V N [Thu, 28 Apr 2016 10:06:13 +0000 (15:36 +0530)]
defconfig: dra74_evm: enable eth driver model

Enable eth driver model for dra74_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodefconfig: am437x_sk_evm: enable eth driver model
Mugunthan V N [Thu, 28 Apr 2016 10:06:12 +0000 (15:36 +0530)]
defconfig: am437x_sk_evm: enable eth driver model

Enable eth driver model for am437x_sk_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodefconfig: am437x_gp_evm: enable eth driver model
Mugunthan V N [Thu, 28 Apr 2016 10:06:11 +0000 (15:36 +0530)]
defconfig: am437x_gp_evm: enable eth driver model

Enable eth driver model for am437x_gp_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoarm: dts: dra7: fix ethernet name with proper device address
Mugunthan V N [Thu, 28 Apr 2016 10:06:10 +0000 (15:36 +0530)]
arm: dts: dra7: fix ethernet name with proper device address

Fix typo error for cpsw device name with proper device address

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoarm: dts: dra7: add syscon node to cpsw to read mac address
Mugunthan V N [Thu, 28 Apr 2016 10:06:09 +0000 (15:36 +0530)]
arm: dts: dra7: add syscon node to cpsw to read mac address

Add syscon node to cpsw device node to read mac address
from efuse.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoarm: dts: am4372: add syscon node to cpsw to read mac address
Mugunthan V N [Thu, 28 Apr 2016 10:06:08 +0000 (15:36 +0530)]
arm: dts: am4372: add syscon node to cpsw to read mac address

Add syscon node to cpsw device node to read mac address
from efuse.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodrivers: net: cpsw: add support for reading mac address from efuse
Mugunthan V N [Thu, 28 Apr 2016 10:06:07 +0000 (15:36 +0530)]
drivers: net: cpsw: add support for reading mac address from efuse

Different TI platforms has to read with different combination to
get the mac address from efuse. So add support to read mac address
based on machine/device compatibles.

The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c
done by Tony Lindgren.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodrivers: net: cpsw: fix get mdio base and gmii_sel reg from DT
Mugunthan V N [Thu, 28 Apr 2016 10:06:06 +0000 (15:36 +0530)]
drivers: net: cpsw: fix get mdio base and gmii_sel reg from DT

Since dra7x platforms address bus is define as 64 bits to support
LAPE, fdtdec_get_addr() returns a invalid address for mdio based
and gmii_sel register address. Fixing this by using
fdtdec_get_addr_size_auto_noparent() which will derive address
cell and size cell from its parent.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoARM: omap5: add platform specific ethernet phy modes configurations
Mugunthan V N [Thu, 28 Apr 2016 10:06:05 +0000 (15:36 +0530)]
ARM: omap5: add platform specific ethernet phy modes configurations

Add platforms specific phy mode configuration bits to be used
to configure phy mode in control module.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodrivers: net: cpsw: fix cpsw dp parse when num slaves as 1
Mugunthan V N [Thu, 28 Apr 2016 10:06:04 +0000 (15:36 +0530)]
drivers: net: cpsw: fix cpsw dp parse when num slaves as 1

On some boards number of slaves can be 1 when only one port
ethernet is pinned out. So do not break when slave_index and
num slaves check fails, instead continue to parse the next
child.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoti_omap5_common: eth: do not define DM_ETH for spl
Mugunthan V N [Thu, 28 Apr 2016 10:06:03 +0000 (15:36 +0530)]
ti_omap5_common: eth: do not define DM_ETH for spl

Since omap's spl doesn't support DM currently, do not define
DM_ETH for spl build.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodrivers: core: device: add support to check dt compatible for a device/machine
Mugunthan V N [Thu, 28 Apr 2016 10:06:02 +0000 (15:36 +0530)]
drivers: core: device: add support to check dt compatible for a device/machine

Provide an api to check whether the given device or machine is
compatible with the given compat string which helps in making
decisions in drivers based on device or machine compatible.

Idea taken from Linux.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: phy: Add PHY driver for mv88e61xx switches
Kevin Smith [Thu, 31 Mar 2016 19:33:12 +0000 (19:33 +0000)]
net: phy: Add PHY driver for mv88e61xx switches

The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot.  This is a complete
rework to support this device as a PHY.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: Remove unused mv88e61xx switch driver
Kevin Smith [Thu, 31 Mar 2016 19:33:12 +0000 (19:33 +0000)]
net: Remove unused mv88e61xx switch driver

No boards are using this driver.  Remove in preparation for a new
driver with integrated PHY support.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
8 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Tue, 24 May 2016 12:20:43 +0000 (08:20 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-microblaze

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-atmel
Tom Rini [Tue, 24 May 2016 11:22:55 +0000 (07:22 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel

8 years agoARM: zynq: Simplify zynq configuration
Michal Simek [Fri, 20 May 2016 12:59:33 +0000 (14:59 +0200)]
ARM: zynq: Simplify zynq configuration

Extending Kconfig for adding new platform is a lot of work
for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and
remove all dependencies on TARGET_ZYNQ_* options including SPL.
As a side-effect it also remove custom init folder for ps7_init_gpl.*
files. Folder is chosen based on device-tree file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agophy: marvell: Do not reset phy after negotiation
Michal Simek [Wed, 18 May 2016 12:46:28 +0000 (14:46 +0200)]
phy: marvell: Do not reset phy after negotiation

The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c358c3ecf5f394ff37def6a45eb26768c)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agophy: Wire return value from phy_config()
Michal Simek [Wed, 18 May 2016 12:37:23 +0000 (14:37 +0200)]
phy: Wire return value from phy_config()

Fix zynq_gem driver to handle error from phy_config correctly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoimage: Add boot_get_fpga() to load fpga with bootm
Michal Simek [Tue, 17 May 2016 12:03:50 +0000 (14:03 +0200)]
image: Add boot_get_fpga() to load fpga with bootm

Add function boot_get_fpga() which find and load bitstream to
programmable logic if fpga entry is present.
Function is supported on Xilinx devices for full and partial bitstreams
in BIN and BIT format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove additional blankline in image.h

8 years agonet: phy: Handle phy_startup() error codes properly
Michal Simek [Wed, 18 May 2016 10:46:12 +0000 (12:46 +0200)]
net: phy: Handle phy_startup() error codes properly

Propagate error code from genphy_update_link() to phy startup().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
8 years agophy: Return correct error code when timeout happens
Michal Simek [Wed, 18 May 2016 10:48:57 +0000 (12:48 +0200)]
phy: Return correct error code when timeout happens

Return -ETIMEDOUT if timeout happens.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
8 years agonet: xilinx: Handle error value from phy_startup()
Michal Simek [Wed, 18 May 2016 10:37:22 +0000 (12:37 +0200)]
net: xilinx: Handle error value from phy_startup()

Handle error returned by phy_startup() properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
8 years agomkimage: Report information about fpga
Michal Simek [Tue, 17 May 2016 11:58:44 +0000 (13:58 +0200)]
mkimage: Report information about fpga

Add FIT_FPGA_PROP that user can identify an optional
entry for fpga.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agofpga: Fix typo in function comment
Michal Simek [Tue, 17 May 2016 12:32:00 +0000 (14:32 +0200)]
fpga: Fix typo in function comment

Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable CLK framework
Michal Simek [Tue, 17 May 2016 11:33:11 +0000 (13:33 +0200)]
ARM64: zynqmp: Enable CLK framework

ZynqMP is using fixed clocks now that's why enabling it to be available
for drivers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add SPL support support
Michal Simek [Fri, 20 Nov 2015 12:17:22 +0000 (13:17 +0100)]
ARM64: zynqmp: Add SPL support support

Support RAM and MMC boot mode in SPL also with SPL_FIT images.

In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
 aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
 mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
 -d bl31.bin atf.ub
 cp spl/boot.bin <sdcard fat partition>
 cp atf.ub <sdcard fat partition>
 cp u-boot.bin <sdcard fat partition>

2) Boot flow with full U-Boot(EL3):
 cp spl/boot.bin <sdcard>
 cp u-boot*.img <sdcard>

3) emmc boot mode
 dd if=/dev/zero of=sd.img bs=1024 count=1024
 parted sd.img mktable msdos
 parted sd.img mkpart p fat32 0% 100%
 kpartx -a sd.img
 mkfs.vfat /dev/mapper/loop0p1
 mount /dev/mapper/loop0p1 /mnt/
 cp spl/boot.bin /mnt
 cp u-boot.img /mnt
 cp u-boot.bin /mnt
 cp atf.ub /mnt
 umount /dev/mapper/loop0p1
 kpartx -d sd.img
 cp sd.img /tftpboot/

 and program it via u-boot
 tftpb 10000 sd.img
 mmcinfo
 mmc write 10000 0 $filesize
 mmc rescan
 mmc part
 ls mmc 0

psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.

The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI
Michal Simek [Mon, 22 Feb 2016 08:57:27 +0000 (09:57 +0100)]
ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI

Add missing u-boot,dm-pre-reloc to get IPs initialized.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Align gic ranges for 64k in device tree
Alexander Graf [Thu, 12 May 2016 11:44:01 +0000 (13:44 +0200)]
ARM64: zynqmp: Align gic ranges for 64k in device tree

The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.

This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agotools: zynqmpimage: Add Xilinx ZynqMP boot header generation
Michal Simek [Wed, 27 Apr 2016 12:03:29 +0000 (14:03 +0200)]
tools: zynqmpimage: Add Xilinx ZynqMP boot header generation

Add support for the zynqmpimage to mkimage.
Only basic functionality is supported without encryption and register
initialization with one partition which is filled by U-Boot SPL.
For more detail information look at Xilinx ZynqMP TRM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoSPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode
Michal Simek [Thu, 28 Apr 2016 07:54:16 +0000 (09:54 +0200)]
SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode

Support loading FIT in SPL for RAM bootmode.
CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored
in memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: zynq: Call ps7_post_config() for SPL
Michal Simek [Tue, 10 May 2016 05:55:52 +0000 (07:55 +0200)]
ARM: zynq: Call ps7_post_config() for SPL

If ps7_post_config() is defined call it. It is enabling for example
level shifters for PL bitstreams.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable option to overwrite default variables
Michal Simek [Tue, 10 May 2016 07:50:35 +0000 (09:50 +0200)]
ARM64: zynqmp: Enable option to overwrite default variables

Enable overwriting variables out of main config file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agospl: Introduce new function spl_board_prepare_for_boot
Michal Simek [Tue, 10 May 2016 05:54:20 +0000 (07:54 +0200)]
spl: Introduce new function spl_board_prepare_for_boot

Call this function before passing control from SPL.
For fpga case it is necessary to enable for example level shifters
when bitstream is programmed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoARM64: zynqmp: Add debug uart for zc1751-dc1
Michal Simek [Wed, 4 May 2016 10:33:22 +0000 (12:33 +0200)]
ARM64: zynqmp: Add debug uart for zc1751-dc1

It is helpful for debugging.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108
Michal Simek [Thu, 17 Mar 2016 22:02:37 +0000 (23:02 +0100)]
ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108

Add missing SPI flash options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Remove CONFIG_PREBOOT
Michal Simek [Fri, 29 Apr 2016 11:04:02 +0000 (13:04 +0200)]
ARM64: zynqmp: Remove CONFIG_PREBOOT

CONFIG_PREBOOT variable is breaking ./test/py framework.
Remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: zynq: Add support for SPL_LOAD_FIT
Michal Simek [Tue, 3 May 2016 12:20:17 +0000 (14:20 +0200)]
ARM: zynq: Add support for SPL_LOAD_FIT

Enable minimal function to be able to compile SPL_LOAD_FIT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Wire up debug_uart setup
Michal Simek [Fri, 22 Apr 2016 06:50:45 +0000 (08:50 +0200)]
ARM64: zynqmp: Wire up debug_uart setup

It has to be enabled by debug_uart_init().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable eMMC boot partitions commands
Michal Simek [Tue, 26 Apr 2016 14:03:42 +0000 (16:03 +0200)]
ARM64: zynqmp: Enable eMMC boot partitions commands

Enable some additional features of the eMMC boot partitions.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add support for reading MAC from eeprom
Michal Simek [Fri, 22 Apr 2016 09:48:49 +0000 (11:48 +0200)]
ARM64: zynqmp: Add support for reading MAC from eeprom

Add support for on board eeprom with programmed MAC for using in u-boot
to have uniq address for every board.
Most of the time uniq MAC address is on a label on the board.
If address is not programmed use these command to program it.

On zcu102:
ZynqMP> mm.b 0
00000000: 00 ? 00
00000001: a0 ? 0a
00000002: 35 ? 35
00000003: 02 ? 02
00000004: 00 ? ef
00000005: 00 ? 67
00000006: 00 ? q
i2c dev 5
i2c write 0 54 20 6
i2c md 54 20

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable missing distro default options
Michal Simek [Fri, 22 Apr 2016 12:28:17 +0000 (14:28 +0200)]
ARM64: zynqmp: Enable missing distro default options

Enable all options which distros requires.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable HUSH parser for all zynqmp targets
Michal Simek [Fri, 22 Apr 2016 11:04:42 +0000 (13:04 +0200)]
ARM64: zynqmp: Enable HUSH parser for all zynqmp targets

Enable HUSH for all zynqmp boards which don't have it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus
Masahiro Yamada [Mon, 25 Apr 2016 03:14:43 +0000 (12:14 +0900)]
ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus

Commit 9f56917ab88a ("dm: core: make simple-bus compatible to
simple-mfd") made possible to import the following commit:

Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1

The SLCR (System-Level Control Registers) block is an MFD (Multi
Function Device) rather than a bus.

"simple-mfd" seems a more suitable compatible string than "simple-bus".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agogpio: zynq: Add support for reading gpio pin state
Michal Simek [Fri, 4 Mar 2016 14:56:50 +0000 (15:56 +0100)]
gpio: zynq: Add support for reading gpio pin state

Add zynq_gpio_get_function() which return status on gpio pin.
This function enables gpio status command.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or not
Masahiro Yamada [Wed, 13 Apr 2016 21:52:26 +0000 (06:52 +0900)]
ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or not

Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device
tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always
load u-boot.img whether CONFIG_OF_SEPARATE is defined or not.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: sama5d2: Implement boot device autodetection
Marek Vasut [Fri, 22 Apr 2016 19:56:21 +0000 (21:56 +0200)]
ARM: sama5d2: Implement boot device autodetection

Implement support for saving ARM register R4 early during boot using
save_boot_params . Implement support for decoding the stored register
R4 value in spl_boot_device() to obtain boot device from which the
SoC booted. This way, the SPL will always load U-Boot from the same
device from which the SPL itself booted instead of using hard-coded
boot device.

This functionality is useful for example when booting sama5d2-xplained
from SD card, where by default the SPL would try loading the U-Boot
from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1),
while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired
to always boot from BOOT_DEVICE_MMC1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoARM: atmel: Enable FIT image support for SAMA5Dx
Marek Vasut [Mon, 18 Apr 2016 16:30:41 +0000 (18:30 +0200)]
ARM: atmel: Enable FIT image support for SAMA5Dx

Enable the fitImage support for the entire SAMA5Dx lineup of CPUs.
The fitImage is superior image format to uImage and it is useful
to have it available.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebase on current ToT]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoboard: sama5d2_xplained: change SDHCI GCK's clock source to UPLL
Wenyou Yang [Mon, 11 Apr 2016 08:41:33 +0000 (16:41 +0800)]
board: sama5d2_xplained: change SDHCI GCK's clock source to UPLL

Change the clock source of the SDHCI's generated clock from PLLA to
UPLL clock to align to Linux driver.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoARM: at91: clock: complete the GCK's clock sources
Wenyou Yang [Mon, 11 Apr 2016 08:41:32 +0000 (16:41 +0800)]
ARM: at91: clock: complete the GCK's clock sources

Add the UPLL clock and master clock as a clock source for getting
the generated clock frequency to complete its clock sources support.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoARM: at91: clock: fix the GCK's clock source
Wenyou Yang [Mon, 11 Apr 2016 08:41:31 +0000 (16:41 +0800)]
ARM: at91: clock: fix the GCK's clock source

Before enabling a generated clock whose source is from the UPLL
clock, check and enable the UPLL clock.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoboard: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0
Wenyou Yang [Mon, 11 Apr 2016 06:07:17 +0000 (14:07 +0800)]
board: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0

Fix the missing pin config of the SDMMC0 interface.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoboard: atmel: add SAMA5D2 PTC Engineering board
Wenyou Yang [Fri, 26 Feb 2016 09:20:26 +0000 (17:20 +0800)]
board: atmel: add SAMA5D2 PTC Engineering board

The board supports following features:
 - Boot media support: NAND Flash/SPI Flash
 - Support ethernet
 - Support USB mass storage

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoARM: at91: sama5d2: add macro & field definitions
Wenyou Yang [Fri, 26 Feb 2016 09:20:25 +0000 (17:20 +0800)]
ARM: at91: sama5d2: add macro & field definitions

They will be used on SAMA5D2 PTC board.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Mon, 23 May 2016 22:32:47 +0000 (18:32 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-x86

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Sat, 21 May 2016 00:43:27 +0000 (20:43 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

8 years agoARM: fix ifdef in ARMv8 lowlevel_init() again
Masahiro Yamada [Fri, 20 May 2016 03:13:10 +0000 (12:13 +0900)]
ARM: fix ifdef in ARMv8 lowlevel_init() again

Commit 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY.

Fixes: 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoSPL: fat: Fix spl_parse_image_header() return value handling
Tom Rini [Mon, 23 May 2016 15:51:13 +0000 (11:51 -0400)]
SPL: fat: Fix spl_parse_image_header() return value handling

The spl_parse_image_header() can return 0 and it is not an error.
Only treat non-zero return value as an error.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoomap3: Fix SPI registers on am33xx and am43xx
Martin Hejnfelt [Thu, 19 May 2016 07:11:58 +0000 (09:11 +0200)]
omap3: Fix SPI registers on am33xx and am43xx

When the base registers are read from device tree the base is not
0x48030100 as the driver expects, but 0x48030000, resulting in
non functioning SPI. To deal with this, use same idea as how this
is done in the linux kernel (drivers/spi/spi-omap2-mcspi.c) and
add a structure with a field that is used to shift the registers
on these systems.

v2: Fixed commit subject line to correct cpu

Signed-off-by: Martin Hejnfelt <mh@newtec.dk>
8 years agokbuild: fixdep: Check fstat(2) return value
Tom Rini [Fri, 13 May 2016 14:54:04 +0000 (10:54 -0400)]
kbuild: fixdep: Check fstat(2) return value

Coverity has recently added a check that will find when we don't check
the return code from fstat(2).  Copy/paste the checking logic that
print_deps() has with an appropriate re-wording of the perror() message.

[ Linux commit : 46fe94ad18aa7ce6b3dad8c035fb538942020f2b ]

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
8 years agospl: Setup default value for OF_LIST
Michal Simek [Wed, 4 May 2016 13:14:11 +0000 (15:14 +0200)]
spl: Setup default value for OF_LIST

OF_LIST can't remain empty that's why setup it up to default DTB.

If it is empty u-boot.img is created without FDT partition:
For example:
  ./tools/mkimage -f auto -A arm -T firmware -C none -O u-boot -a
0x8000000 -e 0 -n "U-Boot 2016.05-rc3 ..." -E -b  -d u-boot-nodtb.bin u-boot.img
Can't set 'timestamp' property for '' node (FDT_ERR_NOSPACE)
FIT description: Firmware image with one or more FDT blobs
Created:         Wed May  4 15:02:52 2016
 Image 0 (firmware@1)
  Description:  U-Boot 2016.05-rc3-00080-gff2e12ae22a8-dirty for zynqmp
board
  Created:      Wed May  4 15:02:52 2016
  Type:         Firmware
  Compression:  uncompressed
  Data Size:    unavailable
  Architecture: ARM
  Load Address: 0x08000000
 Default Configuration: 'conf@1'
 Configuration 0 (conf@1)
  Description:  unavailable
  Kernel:       unavailable

And then image like this doesn't contain description and link to FDT and
can't boot.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agospl: fit: Print error message when FDT is not present
Michal Simek [Wed, 4 May 2016 13:08:00 +0000 (15:08 +0200)]
spl: fit: Print error message when FDT is not present

When FDT is not present in the image user doesn't get any error what's
wrong. Print error message if LIBCOMMON_SUPPORT is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Seris-cc: uboot
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agomkimage: Add a quiet mode
Simon Glass [Sun, 1 May 2016 19:55:38 +0000 (13:55 -0600)]
mkimage: Add a quiet mode

Some build systems want to be quiet unless there is a problem. At present
mkimage displays quite a bit of information when generating a FIT file. Add
a '-q' flag to silence this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoimage-fit: Don't display an error in fit_set_timestamp()
Simon Glass [Sun, 1 May 2016 19:55:37 +0000 (13:55 -0600)]
image-fit: Don't display an error in fit_set_timestamp()

This function returns an error code and its caller may be able to fix the
error. For example fit_handle_file() expands the device tree to fit if there
is a lack of space.

In this case the caller does not want an error displayed. It is confusing,
since it suggests that something is wrong, when it fact everything is fine.
Drop the error.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agomalloc: improve memalign fragmentation fix
Stephen Warren [Mon, 25 Apr 2016 21:55:42 +0000 (15:55 -0600)]
malloc: improve memalign fragmentation fix

Commit 4f144a416469 "malloc: work around some memalign fragmentation
issues" enhanced memalign() so that it can succeed in more cases where
heap fragmentation is present. However, it did not solve as many cases
as it could. This patch enhances the code to cover more cases.

The alignment code works by allocating more space than the user requests,
then adjusting the returned pointer to achieve alignment. In general, one
must allocate "alignment" bytes more than the user requested in order to
guarantee that alignment is possible. This is what the original code does.
The previous enhancement attempted a second allocation if the padded
allocation failed, and succeeded if that allocation just happened to be
aligned; a fluke that happened often in practice. There are still cases
where this could fail, yet where it is still possible to honor the user's
allocation request. In particular, if the heap contains a free region that
is large enough for the user's request, and for leading padding to ensure
alignment, but has no or little space for any trailing padding. In this
case, we can make a third(!) allocation attempt after calculating exactly
the size of the leading padding required to achieve alignment, which is
the minimal over-allocation needed for the overall memalign() operation to
succeed if the third and second allocations end up at the same location.

This patch isn't checkpatch-clean, since it conforms to the existing
coding style in dlmalloc.c, which is different to the rest of U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agox86: galileo: Override SMBIOS product name
Bin Meng [Sun, 22 May 2016 08:45:39 +0000 (01:45 -0700)]
x86: galileo: Override SMBIOS product name

Override the default product name U-Boot reports in the SMBIOS
table, to be compatible with the Intel provided UEFI BIOS, as
Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
it to do different board level configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Switch to use SMBIOS Kconfig options when writing SMBIOS tables
Bin Meng [Sun, 22 May 2016 08:45:38 +0000 (01:45 -0700)]
x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tables

Make use of the newly added Kconfig options of board manufacturer
and product name to write SMBIOS tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: kconfig: Add two options for SMBIOS manufacturer and product name
Bin Meng [Sun, 22 May 2016 08:45:37 +0000 (01:45 -0700)]
x86: kconfig: Add two options for SMBIOS manufacturer and product name

This introduces two Kconfig options to be used by SMBIOS tables:
board manufacturer and product name.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: galileo: Enable MP table generation
Bin Meng [Sun, 22 May 2016 08:45:36 +0000 (01:45 -0700)]
x86: galileo: Enable MP table generation

Now that we have added CPU uclass driver and fixed the IOAPIC ID
conflict, enable MP table generation so that IOAPIC can be used
by the Linux kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: broadwell: Correct I/O APIC ID
Bin Meng [Sun, 22 May 2016 08:45:35 +0000 (01:45 -0700)]
x86: broadwell: Correct I/O APIC ID

Currently ID 2 is assgined to broadwell I/O APIC, however per
chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change
I/O APIC ID to 4 to avoid conflict.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: quark: Assign a unique I/O APIC ID
Bin Meng [Sun, 22 May 2016 08:45:34 +0000 (01:45 -0700)]
x86: quark: Assign a unique I/O APIC ID

After power-on, both LAPIC and I/O APIC appear with the same APIC ID
zero, which creates an ID conflict. When generating MP table, U-Boot
reports zero as the LAPIC ID in the processor entry, and zero as the
I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment
entries. Such MP table confuses Linux kernel and finally a kernel
panic is seen during boot:

  BUG: unable to handle kernel paging request at ffff9000
  IP: [<c101d462>] native_io_apic_write+0x22/0x30
  *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000
  Oops: 0002 [#1]
  Modules linked in:
  Pid: 1, comm: swapper Tainted: G        W    3.8.7 #3 intel galileo/galileo
  EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0
  EIP is at native_io_apic_write+0x22/0x30
  ...
  Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Call lapic_setup() in interrupt_init()
Bin Meng [Sun, 22 May 2016 08:45:33 +0000 (01:45 -0700)]
x86: Call lapic_setup() in interrupt_init()

Let's configure LAPIC in a common place - interrupt_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Remove SMP limitation in lapic_setup()
Bin Meng [Sun, 22 May 2016 08:45:32 +0000 (01:45 -0700)]
x86: Remove SMP limitation in lapic_setup()

At present LAPIC is enabled and configured as virtual wire mode
in lapic_setup() only when CONFIG_SMP is on. This limitation is
however not necessary as for uniprocessor this is still needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Don't touch IA32_APIC_BASE MSR on Intel Quark
Bin Meng [Sun, 22 May 2016 08:45:31 +0000 (01:45 -0700)]
x86: Don't touch IA32_APIC_BASE MSR on Intel Quark

Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: galileo: Enable CPU driver
Bin Meng [Sun, 22 May 2016 08:45:30 +0000 (01:45 -0700)]
x86: galileo: Enable CPU driver

Add a cpu node in the device tree and enable CPU driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Use latest microcode for all BayTrail boards
Bin Meng [Mon, 23 May 2016 07:25:20 +0000 (15:25 +0800)]
x86: Use latest microcode for all BayTrail boards

Update board device tree to include latest microcode, and remove
the old no longer needed microcode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
8 years agox86: baytrail: Update to latest microcode
Bin Meng [Sun, 22 May 2016 08:45:28 +0000 (01:45 -0700)]
x86: baytrail: Update to latest microcode

Update BayTrail microcde to rev 325 (for CPUID 30673), rev 907
(for CPUID 30679).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>