oweals/u-boot.git
9 years agoarmv8/ls2085a: Enable "date" command for QDS and RDB
Priyanka Jain [Thu, 28 May 2015 09:23:56 +0000 (14:53 +0530)]
armv8/ls2085a: Enable "date" command for QDS and RDB

Enable "date" command for QDS and RDB boards

Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv8/ls2085ardb: add hwconfig setting for eSDHC
Yangbo Lu [Thu, 28 May 2015 09:23:55 +0000 (14:53 +0530)]
armv8/ls2085ardb: add hwconfig setting for eSDHC

Add hwconfig setting for eSDHC since it shares some pins with other
IP block.

Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv8/ls2085ardb: Add eth & phy firmware loading support
Prabhakar Kushwaha [Thu, 28 May 2015 09:23:54 +0000 (14:53 +0530)]
armv8/ls2085ardb: Add eth & phy firmware loading support

Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Wed, 15 Jul 2015 14:41:20 +0000 (10:41 -0400)]
Merge git://git.denx.de/u-boot-x86

9 years agopci: Disable expansion ROM address decoding when signature check fails
Bin Meng [Wed, 8 Jul 2015 05:06:41 +0000 (13:06 +0800)]
pci: Disable expansion ROM address decoding when signature check fails

We should not leave the expansion ROM address window open when there
is not a valid ROM.

Suggested-by: Matt Porter <mporter@konsulko.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agopci: Configure expansion ROM during auto config process
Bin Meng [Wed, 8 Jul 2015 05:06:40 +0000 (13:06 +0800)]
pci: Configure expansion ROM during auto config process

Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodrivers: block: Remove the ata_piix driver
Bin Meng [Sat, 16 May 2015 01:33:16 +0000 (09:33 +0800)]
drivers: block: Remove the ata_piix driver

This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Adjust config option order in defconfig for Crown Bay and Minnowmax
Bin Meng [Thu, 9 Jul 2015 10:37:40 +0000 (18:37 +0800)]
x86: Adjust config option order in defconfig for Crown Bay and Minnowmax

Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
result so that the config option order matches Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agotools: ifdtool: Write correct offset on 32-bit machine
Bin Meng [Mon, 6 Jul 2015 07:57:06 +0000 (15:57 +0800)]
tools: ifdtool: Write correct offset on 32-bit machine

On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff,
which is wrong for u-boot.rom components like u-boot-x86-16bit.bin.
Change to use strtoll() so that it works on both 32-bit and 64-bit
machines.

Reported-by: Fei Wang <wangfei.jimei@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add binary blob checksums for Minnowboard MAX
Simon Glass [Sat, 4 Jul 2015 00:28:28 +0000 (18:28 -0600)]
x86: Add binary blob checksums for Minnowboard MAX

To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: x86: baytrail: Correct PCI region 3 when driver model is used
Simon Glass [Sat, 4 Jul 2015 00:28:27 +0000 (18:28 -0600)]
dm: x86: baytrail: Correct PCI region 3 when driver model is used

Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: x86: minnowmax: Move PCI to use driver model
Simon Glass [Sat, 4 Jul 2015 00:28:26 +0000 (18:28 -0600)]
dm: x86: minnowmax: Move PCI to use driver model

Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: pci: Tidy up the generic x86 PCI driver
Simon Glass [Sat, 4 Jul 2015 00:28:25 +0000 (18:28 -0600)]
x86: pci: Tidy up the generic x86 PCI driver

This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Add ROM image description for minnowmax
Simon Glass [Sat, 4 Jul 2015 00:28:24 +0000 (18:28 -0600)]
x86: Add ROM image description for minnowmax

The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: spi: Enable environment for minnowmax
Simon Glass [Sat, 4 Jul 2015 00:28:23 +0000 (18:28 -0600)]
dm: spi: Enable environment for minnowmax

Enable a SPI environment and store it in a suitable place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
9 years agodm: spi: Correct BIOS protection logic for ICH9
Simon Glass [Sat, 4 Jul 2015 00:28:22 +0000 (18:28 -0600)]
dm: spi: Correct BIOS protection logic for ICH9

The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
9 years agodm: spi: Correct status register access width
Simon Glass [Sat, 4 Jul 2015 00:28:21 +0000 (18:28 -0600)]
dm: spi: Correct status register access width

The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
9 years agox86: Configure VESA parameters before loading Linux kernel
Bin Meng [Mon, 6 Jul 2015 08:31:36 +0000 (16:31 +0800)]
x86: Configure VESA parameters before loading Linux kernel

Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
9 years agox86: crownbay: Enable graphics support
Bin Meng [Mon, 6 Jul 2015 08:31:35 +0000 (16:31 +0800)]
x86: crownbay: Enable graphics support

Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove MARK_GRAPHICS_MEM_WRCOMB
Bin Meng [Mon, 6 Jul 2015 08:31:34 +0000 (16:31 +0800)]
x86: Remove MARK_GRAPHICS_MEM_WRCOMB

MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Move VGA option rom macros to Kconfig
Bin Meng [Mon, 6 Jul 2015 08:31:33 +0000 (16:31 +0800)]
x86: Move VGA option rom macros to Kconfig

Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: cmd_mtrr: Improve MTRR list information
Bin Meng [Mon, 6 Jul 2015 08:31:32 +0000 (16:31 +0800)]
x86: cmd_mtrr: Improve MTRR list information

Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: queensbay: Change CPU_ADDR_BITS to 32
Bin Meng [Mon, 6 Jul 2015 08:31:31 +0000 (16:31 +0800)]
x86: queensbay: Change CPU_ADDR_BITS to 32

Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Setup fixed range MTRRs for legacy regions
Bin Meng [Mon, 6 Jul 2015 08:31:30 +0000 (16:31 +0800)]
x86: Setup fixed range MTRRs for legacy regions

We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agovideo: Add 32-bit color depth support for VBE
Jian Luo [Mon, 6 Jul 2015 08:31:29 +0000 (16:31 +0800)]
video: Add 32-bit color depth support for VBE

The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: bios: Allow pci config read/write to host bridge in int1a_handler
Jian Luo [Mon, 6 Jul 2015 08:31:28 +0000 (16:31 +0800)]
x86: bios: Allow pci config read/write to host bridge in int1a_handler

We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: bios: Synchronize stack between real and protected mode
Jian Luo [Mon, 6 Jul 2015 08:42:06 +0000 (16:42 +0800)]
x86: bios: Synchronize stack between real and protected mode

PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agovideo: vesa_fb: Look up VGA device by class instead of id
Bin Meng [Mon, 6 Jul 2015 08:31:26 +0000 (16:31 +0800)]
video: vesa_fb: Look up VGA device by class instead of id

Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: pci: Correct bus number when scanning sub-buses
Simon Glass [Sun, 7 Jun 2015 14:50:41 +0000 (08:50 -0600)]
dm: pci: Correct bus number when scanning sub-buses

The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodm: pci: Use the correct hose when configuring devices
Simon Glass [Sun, 7 Jun 2015 14:50:40 +0000 (08:50 -0600)]
dm: pci: Use the correct hose when configuring devices

Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.

This corrects a failure to scan and configure devices when driver model is
enabled for PCI.

Also add a comment to explain the problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: queensbay: Change PCIe root ports' interrupt routing
Bin Meng [Tue, 23 Jun 2015 04:18:55 +0000 (12:18 +0800)]
x86: queensbay: Change PCIe root ports' interrupt routing

So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: crownbay: Enable writing MP table
Bin Meng [Tue, 23 Jun 2015 04:18:54 +0000 (12:18 +0800)]
x86: crownbay: Enable writing MP table

Enable writing MP table for Intel Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Update README.x86 for SMP support
Bin Meng [Tue, 23 Jun 2015 04:18:53 +0000 (12:18 +0800)]
x86: Update README.x86 for SMP support

Document U-Boot multi-processor support as well as configuration
tables like SFI and MP tables for SMP OS kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Generate a valid MultiProcessor (MP) table
Bin Meng [Tue, 23 Jun 2015 04:18:52 +0000 (12:18 +0800)]
x86: Generate a valid MultiProcessor (MP) table

Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.

Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add MultiProcessor (MP) table APIs
Bin Meng [Tue, 23 Jun 2015 04:18:51 +0000 (12:18 +0800)]
x86: Add MultiProcessor (MP) table APIs

The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove inline for lapic access routines
Bin Meng [Tue, 23 Jun 2015 04:18:50 +0000 (12:18 +0800)]
x86: Remove inline for lapic access routines

Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add I/O APIC register access routines
Bin Meng [Tue, 23 Jun 2015 04:18:49 +0000 (12:18 +0800)]
x86: Add I/O APIC register access routines

I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Clean up ioapic header file
Bin Meng [Tue, 23 Jun 2015 04:18:48 +0000 (12:18 +0800)]
x86: Clean up ioapic header file

Remove all the dead/unused macros from asm/ioapic.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Reduce PIRQ routing table size
Bin Meng [Tue, 23 Jun 2015 04:18:47 +0000 (12:18 +0800)]
x86: Reduce PIRQ routing table size

There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Ignore function number when writing PIRQ routing table
Bin Meng [Tue, 23 Jun 2015 04:18:46 +0000 (12:18 +0800)]
x86: Ignore function number when writing PIRQ routing table

In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Write correct bus number for the irq router
Bin Meng [Tue, 23 Jun 2015 04:18:45 +0000 (12:18 +0800)]
x86: Write correct bus number for the irq router

We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: queensbay: Correct Topcliff device irqs
Bin Meng [Tue, 23 Jun 2015 04:18:44 +0000 (12:18 +0800)]
x86: queensbay: Correct Topcliff device irqs

There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.

This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: crownbay: Enable DM RTC support
Bin Meng [Tue, 23 Jun 2015 04:18:43 +0000 (12:18 +0800)]
x86: crownbay: Enable DM RTC support

Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agocmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
Bin Meng [Tue, 23 Jun 2015 04:18:42 +0000 (12:18 +0800)]
cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C

Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
but it should be actually CONFIG_DM_RTC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: rtc: Support mc146818 driver in driver model
Bin Meng [Tue, 23 Jun 2015 04:18:41 +0000 (12:18 +0800)]
dm: rtc: Support mc146818 driver in driver model

Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: crownbay: Add MP initialization
Bin Meng [Wed, 17 Jun 2015 03:15:39 +0000 (11:15 +0800)]
x86: crownbay: Add MP initialization

Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(modified to remove error:
   overriding the value of OF_CONTROL. Old value: "y", new value: "y")

9 years agox86: Clean up lapic codes
Bin Meng [Wed, 17 Jun 2015 03:15:38 +0000 (11:15 +0800)]
x86: Clean up lapic codes

This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
  defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
  CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
  it is not apic related and only used by ivybridge
- Fix coding convention issues

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Move lapic_setup() call into init_bsp()
Bin Meng [Wed, 17 Jun 2015 03:15:37 +0000 (11:15 +0800)]
x86: Move lapic_setup() call into init_bsp()

Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Move MP initialization codes into a common place
Bin Meng [Wed, 17 Jun 2015 03:15:36 +0000 (11:15 +0800)]
x86: Move MP initialization codes into a common place

Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
Bin Meng [Wed, 17 Jun 2015 03:15:35 +0000 (11:15 +0800)]
x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS

Ivybridge is not ready for U-Boot MP initialization yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: cpu: Add a new get_count method to cpu uclass
Bin Meng [Wed, 17 Jun 2015 03:15:34 +0000 (11:15 +0800)]
dm: cpu: Add a new get_count method to cpu uclass

Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: kconfig: Fix minor nits in MAX_CPUS
Bin Meng [Fri, 12 Jun 2015 06:52:23 +0000 (14:52 +0800)]
x86: kconfig: Fix minor nits in MAX_CPUS

Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP
Bin Meng [Fri, 12 Jun 2015 06:52:22 +0000 (14:52 +0800)]
x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP

MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: dm: Clean up cpu drivers
Bin Meng [Fri, 12 Jun 2015 06:52:20 +0000 (14:52 +0800)]
x86: dm: Clean up cpu drivers

This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
  file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
  naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
  the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
  cpu_x86_bind()

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: cpu: Test against cpu_ops->get_info in cpu_get_info()
Bin Meng [Fri, 12 Jun 2015 06:52:19 +0000 (14:52 +0800)]
dm: cpu: Test against cpu_ops->get_info in cpu_get_info()

In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: cpu: Fix undefined ENOSYS build error
Bin Meng [Fri, 12 Jun 2015 06:52:18 +0000 (14:52 +0800)]
dm: cpu: Fix undefined ENOSYS build error

Include <errno.h> otherwise ENOSYS is undefined.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: spi: Correct minor nits in ICH driver
Simon Glass [Sun, 7 Jun 2015 14:50:33 +0000 (08:50 -0600)]
dm: spi: Correct minor nits in ICH driver

Tidy up three minor problems in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
9 years agospi: sf: Print the error code on failure
Simon Glass [Sun, 7 Jun 2015 14:50:32 +0000 (08:50 -0600)]
spi: sf: Print the error code on failure

Rather than just 'ERROR', display the error code, which may be useful, at
least with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
9 years agox86: fsp: Move FspInitEntry call to board_init_f()
Bin Meng [Sun, 7 Jun 2015 03:33:14 +0000 (11:33 +0800)]
x86: fsp: Move FspInitEntry call to board_init_f()

The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of init_sequence_f[] being called by board_init_f().
This way it looks and works better in the U-Boot initialization path.

Due to FSP's design, after calling FspInitEntry it will not return to
its caller, instead it jumps to a continuation function which is given
by bootloader with a new stack in system memory. The original stack in
the CAR is gone, but its content is perserved by FSP and described by
a bootloader temporary memory HOB. Technically we can recover anything
we had before in the previous stack, but that is way too complicated.
To make life much easier, in the FSP continuation routine we just
simply call fsp_init_done() and jump back to car_init_ret() to redo
the whole board_init_f() initialization, but this time with a non-zero
HOB list pointer saved in U-Boot's global data so that we can bypass
the FspInitEntry for the second time.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agox86: fsp: Load GDT before calling FspInitEntry
Bin Meng [Sun, 7 Jun 2015 03:33:13 +0000 (11:33 +0800)]
x86: fsp: Load GDT before calling FspInitEntry

Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is duplicated from BSP whose GDT is
now moved into CAR, and unfortunately FSP calls AP initialization
after it disables the CAR. So basically the BSP's GDT still refers
to the one in the CAR, whose content is no longer available, so
when AP starts up and loads its segment register, it blows up.

To resolve this, we load GDT before calling into FspInitEntry.
The GDT is the same one used in arch/x86/cpu/start16.S, which is
in the ROM and exists forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add Kconfig options to be used by arch/x86/cpu/config.mk
Bin Meng [Sun, 7 Jun 2015 03:33:12 +0000 (11:33 +0800)]
x86: Add Kconfig options to be used by arch/x86/cpu/config.mk

Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agobuilderthread.py: Keep 'SPL'
Tom Rini [Mon, 27 Apr 2015 15:34:38 +0000 (11:34 -0400)]
builderthread.py: Keep 'SPL'

On i.MX platforms the SPL binary is called "SPL" so make sure we keep
that.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Tue, 14 Jul 2015 18:13:23 +0000 (14:13 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

9 years agoRFC: Deprecate MAKEALL
Simon Glass [Thu, 28 Aug 2014 15:43:46 +0000 (09:43 -0600)]
RFC: Deprecate MAKEALL

Since buildman now includes most of the features of MAKEALL it is probably
time to talk about deprecating MAKEALL.

Comments welcome.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoPrepare v2015.07 v2015.07
Tom Rini [Tue, 14 Jul 2015 17:32:21 +0000 (13:32 -0400)]
Prepare v2015.07

Signed-off-by: Tom Rini <trini@konsulko.com>
9 years agoscsi: fix compiler warning with DEBUG and 48bit LBAs
Andre Przywara [Thu, 2 Jul 2015 00:04:23 +0000 (01:04 +0100)]
scsi: fix compiler warning with DEBUG and 48bit LBAs

Commit 2b42c9317db ("ahci: support LBA48 data reads for 2+TB drives")
introduced conditional code which triggers a warning when compiled
with DEBUG enabled:

In file included from common/cmd_scsi.c:12:0:
common/cmd_scsi.c: In function 'scsi_read':
include/common.h:109:4: warning: 'smallblks' may be used uninitialized in this function [-Wmaybe-uninitialized]
...

Since this is for debug only, take the easy way and initialize the
variable explicitly on declaration to avoid the warning.
(Fix a nearby whitespace error on the way.)

Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
9 years agoMerge git://git.denx.de/u-boot-samsung
Tom Rini [Fri, 10 Jul 2015 13:40:59 +0000 (09:40 -0400)]
Merge git://git.denx.de/u-boot-samsung

9 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Fri, 10 Jul 2015 13:40:48 +0000 (09:40 -0400)]
Merge git://git.denx.de/u-boot-marvell

9 years agomtd: fix false positive "Offset exceeds device limit" error
Masahiro Yamada [Wed, 1 Jul 2015 12:35:49 +0000 (21:35 +0900)]
mtd: fix false positive "Offset exceeds device limit" error

Since commit 09c3280754f8 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.

    => nand read 80000000 10000 10000

    NAND read: Offset exceeds device limit
    => nand erase 100000 100000

    NAND erase: Offset exceeds device limit

The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.

Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agoarm: mvebu: db-88f6820-gp: Add USB/EHCI support
Stefan Roese [Mon, 29 Jun 2015 12:58:16 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp: Add USB/EHCI support

This patch enabled the USB/EHCI support for the Marvell
DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agousb: Add EHCI support for Armada 38x (mvebu)
Stefan Roese [Mon, 29 Jun 2015 12:58:15 +0000 (14:58 +0200)]
usb: Add EHCI support for Armada 38x (mvebu)

This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.

Tested on DB-88F6280-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agoarm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) support
Stefan Roese [Mon, 29 Jun 2015 12:58:14 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) support

Configure and enable the SATA/SCSI (AHCI) support for the Marvell
DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agoarm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x
Stefan Roese [Mon, 29 Jun 2015 12:58:13 +0000 (14:58 +0200)]
arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x

This patch adds support for the common AHCI controller on the Marvell
Armada 38x.

Tested on the Marvell DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agoblock: ahci: Don't enable port interrupts
Stefan Roese [Mon, 29 Jun 2015 12:58:12 +0000 (14:58 +0200)]
block: ahci: Don't enable port interrupts

This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.

This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agoarm: mvebu: db-88f6820-gp: Add MMC/SDIO support
Stefan Roese [Mon, 29 Jun 2015 12:58:11 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp: Add MMC/SDIO support

This patch adds MMC/SDIO support to the Marvell DB-88F6820-GP board
configuration. Including support for the common partitions and
filesystems.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agoarm: mvebu: Add SDIO/SDHCI support for Armada A38x
Stefan Roese [Mon, 29 Jun 2015 12:58:10 +0000 (14:58 +0200)]
arm: mvebu: Add SDIO/SDHCI support for Armada A38x

Armada A38x implements an SDHCI compatible SDIO controller. This patch
enables the Marvell driver to support this SoC. And enables the
SDIO controller if selected by the board configuration.

Tested on Marvell DB-88F6820-GP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agommc: sdhci.c: Add config option to use a fixed buffer for transfers
Stefan Roese [Mon, 29 Jun 2015 12:58:09 +0000 (14:58 +0200)]
mmc: sdhci.c: Add config option to use a fixed buffer for transfers

While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.

This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.

Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agommc: sdhci: Use timer based timeout detection in sdhci_send_command()
Stefan Roese [Mon, 29 Jun 2015 12:58:08 +0000 (14:58 +0200)]
mmc: sdhci: Use timer based timeout detection in sdhci_send_command()

The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
9 years agoarm: mvebu: db-88f6820-gp: Add MAINTAINERS file
Stefan Roese [Wed, 1 Jul 2015 15:38:05 +0000 (17:38 +0200)]
arm: mvebu: db-88f6820-gp: Add MAINTAINERS file

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
9 years agoexynos: i2c: Correct bug in pinmux selection
Simon Glass [Fri, 3 Jul 2015 00:15:44 +0000 (18:15 -0600)]
exynos: i2c: Correct bug in pinmux selection

When driver model is not used the current code does not correctly select
the pinmux for the I2C bus. This bug was introduced by this commit:

8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoarm: adds the status info for odroid-xu3
Minkyu Kang [Thu, 2 Jul 2015 01:27:48 +0000 (10:27 +0900)]
arm: adds the status info for odroid-xu3

Adds the 'F:' entry for the board's defconfig

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoahci: Fix compiling warnings under 64bit platforms
Tang Yuantian [Thu, 9 Jul 2015 06:37:30 +0000 (14:37 +0800)]
ahci: Fix compiling warnings under 64bit platforms

When compling under 64bit platforms, there are lots of warnings,
like:

drivers/block/ahci.c:114:18: warning: cast to pointer from integer
 of different size [-Wint-to-pointer-cast]
  u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
                  ^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
 of different size [-Wpointer-to-int-cast]
   probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);

......

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
9 years agoarm: baltos: change USB ports functions
Yegor Yefremov [Thu, 9 Jul 2015 11:34:24 +0000 (13:34 +0200)]
arm: baltos: change USB ports functions

Baltos has USB0 connected to a USB hub and thus is host-only. USB1
is connected to microUSB connector and thus should use OTG mode.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
9 years agokeystone2: config: update default mtd
Michael Scherban [Fri, 26 Jun 2015 14:17:31 +0000 (09:17 -0500)]
keystone2: config: update default mtd

Because it is possible for the MTD number to change, causing a
filesystem mount failure, we should use the volume name instead
of the MTD number and let Linux resolve the correct one.

Signed-off-by: Mike Scherban <m-scherban@ti.com>
9 years agostm32f4: fix gpio description in comment
Antonio Borneo [Wed, 1 Jul 2015 08:04:14 +0000 (16:04 +0800)]
stm32f4: fix gpio description in comment

On STM32F429 gpio PC6/PC7 can be allocated for USART6, as
reported in the comment.
But current code in
drivers/serial/serial_stm32.c
uses a different gpio mapping (PG14/PG9) for USART6.

Fix the comment to match current code in the driver.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
9 years agostm32f4: fix minor typo in comment
Antonio Borneo [Wed, 1 Jul 2015 06:15:03 +0000 (14:15 +0800)]
stm32f4: fix minor typo in comment

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
9 years agostm32f4: fix MAINTAINERS file
Antonio Borneo [Wed, 1 Jul 2015 06:15:02 +0000 (14:15 +0800)]
stm32f4: fix MAINTAINERS file

When "scripts/get_maintainer.pl" parses "board/.../MAINTAINERS",
it uses the line containing board name as delimiter.
Without this line, the script happily mixes the lines from current
board MAINTAINERS file with lines from another file.

Fix it by adding a reasonable board name.

Tested by comparing output of:
cat board/st/stm32f429-discovery/MAINTAINERS
./scripts/get_maintainer.pl -f board/st/stm32f429-discovery

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl>
Cc: Tom Rini <trini@konsulko.com>
9 years agosiemens,am33x: adjust mtd partition
Egli, Samuel [Wed, 1 Jul 2015 15:57:39 +0000 (17:57 +0200)]
siemens,am33x: adjust mtd partition

Use one mtd partition for rootfs and configuration by
means of ubi volumes and get rid of configuration partition.
We can use partition layout for both 256MB and 512MB flash.

Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
9 years agoarm: baltos: fix NAND boot
Yegor Yefremov [Mon, 6 Jul 2015 15:28:36 +0000 (17:28 +0200)]
arm: baltos: fix NAND boot

Specify proper U-Boot offset, enable prefetch mode,
increase bootm size and add FIT fallback, if board_name
is not present in kernel-fit.itb image.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
9 years agoarm: baltos: drop I2C speed to 1000 Hz
Yegor Yefremov [Mon, 6 Jul 2015 15:28:35 +0000 (17:28 +0200)]
arm: baltos: drop I2C speed to 1000 Hz

This action is need to make I2C communication with PMIC
stable for low temperature. Print current I2C speed in
SPL for visual control.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
9 years agoarm: baltos: enable CMD_NET and FIT support in defconfig
Yegor Yefremov [Mon, 6 Jul 2015 15:28:34 +0000 (17:28 +0200)]
arm: baltos: enable CMD_NET and FIT support in defconfig

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agoarm: convert am3517_crane and am3517_evm to generic boards
Yegor Yefremov [Tue, 30 Jun 2015 07:59:47 +0000 (09:59 +0200)]
arm: convert am3517_crane and am3517_evm to generic boards

Add CONFIG_SYS_GENERIC_BOARD to board's config header.

Boot-tested on am3517_evm board.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
9 years agoARM: beagle_x15: prevent DCAN1 _wait_target_disable failure in kernel
Roger Quadros [Thu, 25 Jun 2015 07:25:50 +0000 (10:25 +0300)]
ARM: beagle_x15: prevent DCAN1 _wait_target_disable failure in kernel

If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.

"omap_hwmod: dcan1: _wait_target_disable failed"

This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.

The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.

DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.

Signed-off-by: Roger Quadros <rogerq@ti.com>
[trini: s/PULLUP/PULL_UP/ based on DRA7xx EVM version of this patch]
Signed-off-by: Tom Rini <trini@konsulko.com>
9 years agoARM: DRA7-evm: prevent DCAN1 _wait_target_disable failure in kernel
Roger Quadros [Wed, 24 Jun 2015 14:00:11 +0000 (17:00 +0300)]
ARM: DRA7-evm: prevent DCAN1 _wait_target_disable failure in kernel

If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.

"omap_hwmod: dcan1: _wait_target_disable failed"

This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.

The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.

DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.

Signed-off-by: Roger Quadros <rogerq@ti.com>
9 years agoMakefile:Add GCC flag -fno-delete-null-pointer-checks
Prabhakar Kushwaha [Thu, 2 Jul 2015 06:30:17 +0000 (12:00 +0530)]
Makefile:Add GCC flag -fno-delete-null-pointer-checks

-fdelete-null-pointer-checks flag controls global dataflow analyses and
eliminate useless checks for null pointers; It assume that if a pointer is
checked after it has already been dereferenced, it cannot be null.
This flag is enabled by default.

gcc v4.9 has more optimizations added to this option. Hence it is very
aggressive with GCC v4.9 series. Add -fno-delete-null-pointer-checks to
disable the optimization

Signed-off-by: Rohit Dharmakan <rohitarulraj@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
9 years agoti: Add SPDX license identifier to omap.h
Simon Glass [Tue, 30 Jun 2015 22:03:02 +0000 (16:03 -0600)]
ti: Add SPDX license identifier to omap.h

This also came from Linux - according to this thread it has a GPL v2
license like arch/arm/mach-omap2/mux.h:

http://lists.denx.de/pipermail/u-boot/2015-June/217827.html

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
9 years agoREADME.distro: fix typos
Masahiro Yamada [Tue, 7 Jul 2015 09:47:17 +0000 (18:47 +0900)]
README.distro: fix typos

The word "partition" is doubled.  Keep decent forms for the
following lines.

Also, fix some other typos while we are here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
9 years agoblackfin: Fix build regression due to image size
Joe Hershberger [Mon, 22 Jun 2015 22:57:37 +0000 (17:57 -0500)]
blackfin: Fix build regression due to image size

bf533-stamp, bf538f-ezkit, and cm-bf548 are very space limited.

This was introduced by:
6e0d26c0502e (net: Handle ethaddr changes as an env callback)
by enabling CONFIG_REGEX, which is too big for these boards.

This patch disables CONFIG_REGEX at the expense of working with more
than the first ethaddr.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agoAllow CONFIG_REGEX to be disabled when CONFIG_NET
Joe Hershberger [Mon, 22 Jun 2015 22:57:36 +0000 (17:57 -0500)]
Allow CONFIG_REGEX to be disabled when CONFIG_NET

Instead of selecting REGEX when NET is enabled, make it the default, but
allow boards that are tiny to disable it and lose functionality on all
but the first Ethernet adapter.

cm-bf548, bf538f-ezkit, and bf533-stamp need this. None appear to have
more than one Ethernet interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 8 Jul 2015 21:14:02 +0000 (17:14 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips