Mingkai Hu [Tue, 18 Aug 2015 21:06:26 +0000 (14:06 -0700)]
net: e1000: Support 64-bit physical address
High 32-bit address is needed when u-boot runs in 64-bit space.
Tested on armv8-based LS2085ARDB.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Pavel Machek [Tue, 18 Aug 2015 12:34:26 +0000 (14:34 +0200)]
tftp: adjust settings to be suitable for 100Mbit ethernet
Adjust timouts and retry counts to be suitable for loaded ethernet
network. With 5 seconds timeout, 10 retries maximum, tftp is
impossible even on local network with single full-speed TCP
connection.
100msec timeout should be suitable for most networks tftp is used on,
that is local ethernets. Timeout count really needs to be way higher,
as lost packets are normal when TCP is running over the same network.
Enforce 10msec minimum.
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Masahiro Yamada [Thu, 20 Aug 2015 01:20:55 +0000 (10:20 +0900)]
ARM: davinci: remove support for cam_enc_4xx
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Wed, 19 Aug 2015 22:04:48 +0000 (18:04 -0400)]
Merge git://git.denx.de/u-boot-usb
Marek Vasut [Wed, 12 Aug 2015 20:19:15 +0000 (22:19 +0200)]
usb: dwc2: Rename to dwc2_usb
This driver is not used only on exynos, but also on Altera SoCFPGA,
HiSilicon SoCs, RPi etc, so rename it accordingly to prevent confusion.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 12 Aug 2015 20:19:14 +0000 (22:19 +0200)]
usb: dwc2: Add original Synopsys compat string
Add the Synopsys compatible string. This is used in SoCFPGA DT files.
Signed-off-by: Marek Vasut <marex@denx.de>
Kishon Vijay Abraham I [Wed, 19 Aug 2015 08:19:48 +0000 (13:49 +0530)]
usb: gadget: ether: populate _reset_ callback
populate _reset_ callback to the USB ethernet gadget since UDC core
expects every gadget driver to have the reset callback. This shouldn't
be needed once the ethernet gadget driver is adapted to use the
composite driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Kishon Vijay Abraham I [Wed, 19 Aug 2015 08:19:47 +0000 (13:49 +0530)]
usb: host: xhci-omap: invoke board_usb_cleanup in xhci_hcd_stop
xhci omap driver has board_usb_init in xhci_hcd_init but doesn't have
the corresponding cleanup function in xhci_hcd_stop.
Fix it here by invoking board_usb_cleanup() in xhci_hcd_stop().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Kishon Vijay Abraham I [Wed, 19 Aug 2015 08:19:46 +0000 (13:49 +0530)]
usb: gadget: ether: Perform board initialization from ethernet gadget driver
Ethernet gadget driver can be used both by both SPL and u-boot. Since
usb_eth_init() is the entry point for ethernet gadget driver, perform
board initialization there. Also perform the cleanup in usb_eth_halt.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Sergey Temerkhanov [Mon, 17 Aug 2015 12:38:07 +0000 (15:38 +0300)]
usb: xhci: Fix a potential NULL pointer dereference
This patch fixes a potential NULL pointer dereference arising on
non-present/non-initialized xHCI controllers and adds some error
handling to xHCI code
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Stefan Roese [Tue, 18 Aug 2015 07:27:18 +0000 (09:27 +0200)]
usb: spear: Add support for both SPEAr600 EHCI controllers
USB EHCI on SPEAr600 has not been tested for a while. The base controller
addresses are missing. This patch adds the defines to the header. And adds
the missing code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Adrian Alonso [Thu, 6 Aug 2015 20:46:03 +0000 (15:46 -0500)]
imx: usb: ehci-mx6: wait_for_bit to check reg status
Add wait_for_bit to check reg bit status and replace unbounded
loops to check usb command status
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Thu, 6 Aug 2015 20:43:17 +0000 (15:43 -0500)]
imx: usb: ehci-mx6: add usb support for imx7d soc
Extend ehci-mx6 usb driver to support imx7d usb
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Thu, 6 Aug 2015 20:43:16 +0000 (15:43 -0500)]
imx: usb: ehci-mx6: document board specific functions
Document target board specific functions
board_ehci_hcd_init - override usb phy mode
board_ehci_hcd_init - set usb vbus voltage
board_ehci_power - enables/disables usb vbus voltage
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Thu, 6 Aug 2015 20:43:15 +0000 (15:43 -0500)]
imx: usb: ehci-mx6: reg accessor cleanups
Cleanup read/write register access, use clr/set bits_le32
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Michal Simek [Wed, 12 Aug 2015 10:58:54 +0000 (12:58 +0200)]
zynqmp: enable CONFIG_NET_RANDOM_ETHADDR
We have to set a MAC address to use network.
Otherwise, the tftpboot command fails with the following message:
Gem.
e000b000 Waiting for PHY auto negotiation to complete........ done
*** ERROR: `ethaddr' not set
Since commit
92ac52082140 ("net: Remove all references to
CONFIG_ETHADDR and friends"), we can not use CONFIG_ETHADDR.
The easiest way to set a MAC address is to enable
CONFIG_NET_RANDOM_ETHADDR.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 12 Aug 2015 09:25:05 +0000 (11:25 +0200)]
ARM: dts: Rename memory@0 to memory
zynq-7000.dtsi include skeleton.dtsi which contains memory node with
base address and size zero. If you add memory@0 node to the platform DTS
in final DTB there are two memory nodes and U-Boot works with the first
one (with zeros) which end up in failing in dram_init because size is
zero.
Platform memory node should rewrite default memory node setup from
skeleton.dtsi that's why platfroms needs to also use memory as node name
instead of memory@0.
Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Fri, 17 Jul 2015 11:26:06 +0000 (20:26 +0900)]
zynq: enable CONFIG_NET_RANDOM_ETHADDR
We have to set a MAC address to use network.
Otherwise, the tftpboot command fails with the following message:
Gem.
e000b000 Waiting for PHY auto negotiation to complete........ done
*** ERROR: `ethaddr' not set
Since commit
92ac52082140 ("net: Remove all references to
CONFIG_ETHADDR and friends"), we can not use CONFIG_ETHADDR.
The easiest way to set a MAC address is to enable
CONFIG_NET_RANDOM_ETHADDR.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2015 12:21:25 +0000 (14:21 +0200)]
zynq: Make CONFIG_OF_EMBED default case
Use embedded DTB to let users use u-boot instead of u-boot-dtb.bin.
And fix SPL to use this target.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 4 Aug 2015 07:33:26 +0000 (13:03 +0530)]
zynqmp: usb: Add usb dwc3 driver support for zynqmp
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Sat, 1 Aug 2015 07:39:54 +0000 (16:39 +0900)]
ARM: zynq: drop "optional" from board select in favor of ZC702
One disadvantage of commit
a26cd04920dc (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.
Rip off the "optional" again in favor of ZC702 as the default
target.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 4 Aug 2015 07:31:05 +0000 (13:01 +0530)]
board: Xilinx: zynqmp: Define checkboard() function
Define checkboard() function for zynqMP
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2015 11:19:39 +0000 (13:19 +0200)]
configs: zynqmp: Enable networking by default for EP108
Enable networking for EP108 by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 30 Jul 2015 10:50:26 +0000 (12:50 +0200)]
ARM: zynqmp_ep: Enable ethernet for EP
Enable gem0 and setup phy addr for EP.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 5 Aug 2015 05:50:16 +0000 (07:50 +0200)]
ARM: zynqmp: Add platform specific arch_get_page_table
Based on the patch:
"armv8: caches: Added routine to set non cacheable region"
(sha1:
dad17fd51027ad02ac8f02deed186d08109d61fd)
it is necessary to add platform specific hook.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 29 Jul 2015 11:10:02 +0000 (13:10 +0200)]
zynqmp: Enable U-Boot run in EL3
Enable Secure IOU setup to enable U-Boot to run in EL3 without
setting from ATF.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:55 +0000 (07:31 +0900)]
of: clean up OF_CONTROL ifdef conditionals
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:
#ifdef CONFIG_OF_CONTROL
# if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
# define OF_CONTROL 0
# else
# define OF_CONTROL 1
# endif
#else
# define OF_CONTROL 0
#endif
Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.
Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:54 +0000 (07:31 +0900)]
of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.
Now, there are three boards enabling OF_CONTROL on SPL:
- socfpga_arria5_defconfig
- socfpga_cyclone5_defconfig
- socfpga_socrates_defconfig
This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:53 +0000 (07:31 +0900)]
fdtdec: fix OF_CONTROL switch
There is no case where defined(SPL_DISABLE_OF_CONTROL) is true.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:52 +0000 (07:31 +0900)]
dm: drop CONFIG_DM_DEVICE_REMOVE from uncmd list
We do not want to compile the DM remove code for SPL. Currently,
we undef it in include/config_uncmd_spl.h (for C files) and in
scripts/Makefile.uncmd_spl (for Makefiles). This is really ugly.
This commit demonstrates how we can deprecate those two files.
Use $(SPL_) for the entry in the Makfile and CONFIG_IS_ENABLED()
in C files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:51 +0000 (07:31 +0900)]
led: unify obj-$(CONFIG_LED) and obj-$(CONFIG_SPL_LED) entries
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:50 +0000 (07:31 +0900)]
led: rename CONFIG_SPL_LED_SUPPORT to CONFIG_SPL_LED
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:49 +0000 (07:31 +0900)]
ram: unify obj-$(CONFIG_RAM) and obj-$(CONFIG_SPL_RAM) entries
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:48 +0000 (07:31 +0900)]
ram: rename CONFIG_SPL_RAM_SUPPORT to CONFIG_SPL_RAM
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:47 +0000 (07:31 +0900)]
clk: unify obj-$(CONFIG_CLK) and obj-$(CONFIG_SPL_CLK) entries
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:46 +0000 (07:31 +0900)]
clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLK
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:45 +0000 (07:31 +0900)]
dm: unify obj-$(CONFIG_DM) and obj-$(CONFIG_SPL_DM) entries
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:44 +0000 (07:31 +0900)]
spl: move SPL driver entries to driver/Makefile
Just preparing for upcoming cleaning.
The board-specific linker script board/vpac270/u-boot-spl.lds
has been touched to avoid build error. It does not change the
size of spl/u-boot-spl.bin for this board, so it should be OK.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:43 +0000 (07:31 +0900)]
linux/kconfig.h: add CPP macros useful for per-image config options
The previous commit introduced a useful macro used in makefiles,
in order to reference to different variables (CONFIG_... or
CONFIG_SPL_...) depending on the build context.
Per-image config option control is a PITA in C sources, too.
Here are some macros useful in C/CPP expressions.
CONFIG_IS_ENABLED(FOO) can be used as a shorthand for
(!defined(CONFIG_SPL_BUILD) && defined(CONFIG_FOO)) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FOO))
For example, it is useful to describe C code as follows,
#if CONFIG_IS_ENABLED(OF_CONTROL)
(device tree code)
#else
(board file code)
#endif
The ifdef conditional above is switched by CONFIG_OF_CONTROL during
the U-Boot proper building (CONFIG_SPL_BUILD is not defined), and by
CONFIG_SPL_OF_CONTROL during SPL building (CONFIG_SPL_BUILD is
defined).
The macro can be used in C context as well, so you can also write the
equivalent code as follows:
if (CONFIG_IS_ENABLED(OF_CONTROL)) {
(device tree code)
} else {
(board file code)
}
Another useful macro is CONFIG_VALUE().
CONFIG_VALUE(FOO) is expanded into CONFIG_FOO if CONFIG_SPL_BUILD is
undefined, and into CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
You can write as follows:
text_base = CONFIG_VALUE(TEXT_BASE);
instead of:
#ifdef CONFIG_SPL_BUILD
text_base = CONFIG_SPL_TEXT_BASE;
#else
text_base = CONFIG_TEXT_BASE;
#endif
This commit also adds slight hacking on fixdep so that it can
output a correct list of fixed dependencies.
If the fixdep finds CONFIG_IS_ENABLED(FOO) in a source file,
we want
$(wildcard include/config/foo.h)
in the U-boot proper building context, while we want
$(wildcard include/config/spl/foo.h)
in the SPL build context.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:42 +0000 (07:31 +0900)]
kbuild: add a makefile macro useful with per-image config options
Commit
e02ee2548afe ("kconfig: switch to single .config
configuration") made the configuration itself pretty simple,
instead, we lost the way to systematically enable/disable config
options for each image independently.
Our current strategy is, put entries into Makefile.spl for options
we need separate enabling, or once enable the options globally in
Kconfig and then undef them in Makefile.uncmd_spl if we do not want
to compile the features for SPL at all. Things are getting really
messy. Besides, "ifdef CONFIG_SPL_BUILD" are sprinkled everywhere
in makefiles.
This commit adds a variable to help describe makefile simpler.
$(SPL_) evaluates to "SPL_" during the SPL build, while to an empty
string during building U-boot proper.
So, you can write
obj-$(CONFIG_$(SPL_)FOO) += foo.o
instead of
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FOO) += foo.o
else
obj-$(CONFIG_FOO) += foo.o
endif
If CONFIG_SPL_FOO does not exist in Kconfig, it is equivalent to
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FOO) += foo.o
endif
This is the pattern we often see in our current makefiles.
To take advantage of this macro, we should prefix SPL_ for the SPL
version of the option when we need independent control between
U-boot and SPL. With this naming scheme, I hope our makefiles will
be much simplified.
It means we want to rename existing config options as follows
in the long run:
CONFIG_SPL_SERIAL_SUPPORT -> CONFIG_SPL_SERIAL
CONFIG_SPL_I2C_SUPPORT -> CONFIG_SPL_I2C
CONFIG_SPL_GPIO_SUPPORT -> CONFIG_SPL_GPIO
CONFIG_SPL_SPI_SUPPORT -> CONFIG_SPL_SPI
CONFIG_SPL_DISABLE_OF_CONTROL -> CONFIG_SPL_OF_CONTROL
(inverting the logic)
Then drivers/Makefile would be re-worked as follows:
obj-$(CONFIG_$(SPL_)SERIAL) += serial/
obj-$(CONFIG_$(SPL_)I2C) += i2c/
obj-$(CONFIG_$(SPL_)GPIO) += gpio/
obj-$(CONFIG_$(SPL_)SPI) += spi/
...
Eventually, SPL-specialized entries in Makefile.spl would go away.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 11 Aug 2015 22:31:41 +0000 (07:31 +0900)]
kbuild: fixdep: optimize code slightly
If the target string matches "CONFIG_", move the pointer p
forward. This saves several 7-chars adjustments.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Tue, 11 Aug 2015 04:45:14 +0000 (22:45 -0600)]
fs-test.sh: minor fixes
- Re-direct stderr into the log files, so any errors U-Boot emits are
visible in the logs. This is relevant if the "reset" shell command
attempts to report that it's not supported on the sandbox board.
- Fix test_fs_nonfs() to name the files it created differently for each
invocation. Otherwise, the logs from different tests overwrite
each-other.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Suriyan Ramasami <suriyan.r@gmail.com>
Vladimir Zapolskiy [Wed, 12 Aug 2015 17:22:13 +0000 (20:22 +0300)]
i2c: lpc32xx: correct sanity check for requested bus speed
LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones
and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit
wide. This means that if HCLK is 104MHz, then minimal configurable I2C
clock speed is about 51KHz.
Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in
assumption that peripheral clock is 13MHz it allows to set the minimal
bus speed about 25.5KHz.
Check for negative half clock value is removed since it is always false.
The change fixes the following problem for I2C busses 0 and 1:
=> i2c dev 0
Setting bus to 0
=> i2c speed 100000
Setting bus speed to 100000 Hz
Failure changing bus speed (-22)
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Vladimir Zapolskiy [Wed, 12 Aug 2015 17:32:08 +0000 (20:32 +0300)]
lpc32xx: add common USB OHCI defines for all LPC32xx boards
The change adds a number of macro definitions used by USB OHCI driver,
if CONFIG_USB_OHCI_LPC32XX is selected from a board config file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Thu, 13 Aug 2015 19:40:22 +0000 (15:40 -0400)]
usb: lpc32xx: add host USB driver
Incorporate USB driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx USB driver
- lpc3250 header file USB registers definition.
The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
Sylvain Lemieux [Tue, 4 Aug 2015 21:04:41 +0000 (17:04 -0400)]
i2c: lpc32xx: add support for OTG I2C
Updated the LPC32xx I2C driver to support
the OTG I2C that is part of the USB module.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Sylvain Lemieux [Thu, 13 Aug 2015 19:40:21 +0000 (15:40 -0400)]
nand: lpc32xx: add ECC layout for small page NAND
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)
This layout is matching the lpc32xx NAND SLC Linux Kernel driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Thu, 13 Aug 2015 19:40:20 +0000 (15:40 -0400)]
nand: lpc32xx: add hardware ECC support
Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250 header file missing SLC NAND registers definition
The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy [Tue, 11 Aug 2015 16:57:09 +0000 (19:57 +0300)]
lpc32xx: move common SLC NAND defines to arch/config.h
A number of LPC32xx SLC NAND defines is dictated by controller
hardware limits and OOB layout is defined by operating system, the
definitions are common for all users. Since those macro are used
in out of NAND SLC driver code (simple NAND SPL framework), they can
not be placed into the driver, therefore move them from board config
files to arch/config.h
The change also adds OOB layout details specific to small page NAND
devices taken from Linux kernel.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Mon, 10 Aug 2015 12:16:31 +0000 (08:16 -0400)]
dma: lpc32xx: add DMA driver
Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.
The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
Tom Rini [Tue, 18 Aug 2015 12:25:24 +0000 (08:25 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Tue, 18 Aug 2015 12:24:32 +0000 (08:24 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-samsung
Tom Rini [Mon, 17 Aug 2015 21:32:23 +0000 (17:32 -0400)]
Prepare v2015.10-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 17 Aug 2015 21:19:40 +0000 (17:19 -0400)]
Merge git://git.denx.de/u-boot-marvell
Simon Glass [Mon, 17 Aug 2015 15:28:44 +0000 (09:28 -0600)]
Revert "Align global_data to a 16-byte boundary"
This causes widespread breakage due to the operation of the low-level code
in crt0.S and cro0_64.S for ARM at least.
The fix is not complicated but it seems safer to revert this for now.
This reverts commit
2afddae07523f23f77acd066ad1719f53d289f98.
Signed-off-by: Simon Glass <sjg@chromium.org>
Vignesh R [Mon, 17 Aug 2015 07:59:57 +0000 (13:29 +0530)]
ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With
DMA enabled there is almost 3x improvement in read performance. This
helps in reducing boot time in qspiboot mode
Also add EDMA3 base address for DRA7XX and AM57XX.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Mon, 17 Aug 2015 09:50:13 +0000 (15:20 +0530)]
spi: ti_qspi: Use DMA to read from qspi flash
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Mon, 17 Aug 2015 07:59:55 +0000 (13:29 +0530)]
dma: ti-edma3: Add helper function to support edma3 transfer
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tom Rini [Mon, 17 Aug 2015 07:59:54 +0000 (13:29 +0530)]
sf: ops: Add spi_flash_copy_mmap function
When doing a memory mapped copy we may have DMA available and thus need
to have this copy abstracted so that the driver can do it, rather than a
simple memcpy.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Mon, 17 Aug 2015 07:59:53 +0000 (13:29 +0530)]
ARM: AM43XX: Add functions to enable and disable EDMA3 clocks
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Mon, 17 Aug 2015 07:59:52 +0000 (13:29 +0530)]
ARM: OMAP5: Add functions to enable and disable EDMA3 clocks
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Kishon Vijay Abraham I [Mon, 17 Aug 2015 07:59:51 +0000 (13:29 +0530)]
ARM: OMAP5: Add support for disabling clocks in uboot
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Kishon Vijay Abraham I [Mon, 17 Aug 2015 07:59:50 +0000 (13:29 +0530)]
ARM: AM43xx: Add support for disabling clocks in uboot
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Ravi Babu [Mon, 17 Aug 2015 07:59:49 +0000 (13:29 +0530)]
env: use cache line aligned memory for flash read
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Ravi Babu [Mon, 17 Aug 2015 07:59:48 +0000 (13:29 +0530)]
sf: allocate cache aligned buffers to copy from flash
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Jagan Teki <jteki@openedev.com>
vishalm@ti.com [Mon, 17 Aug 2015 15:47:51 +0000 (10:47 -0500)]
ti: qspi: set flash quad bit based on quad support flag
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Stefan Roese [Tue, 11 Aug 2015 10:50:58 +0000 (12:50 +0200)]
arm: mvebu: db-
88f6820-gp: Enable PCI support
This patch enabled the MVEBU PCIe support on the db-
88f6820-gp A38x
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Stefan Roese [Tue, 11 Aug 2015 07:36:15 +0000 (09:36 +0200)]
arm: mvebu: db-mv784mp-gp: Enable PCI support
This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Anton Schubert [Tue, 11 Aug 2015 09:54:01 +0000 (11:54 +0200)]
pci: mvebu: Add PCIe driver
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.
Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-
88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.
This port was done in cooperation with Anton Schubert.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Stefan Roese [Thu, 6 Aug 2015 12:43:13 +0000 (14:43 +0200)]
arm: mvebu: Add complete SDRAM ECC scrubbing
This patch introduces the SDRAM scrubbing for ECC enabled board
to fill/initialize the ECC bytes. This is done via the XOR engine
to speed up the process. The scrubbing is a 2-stage process:
1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot
2) U-Boot scrubs the remaining SDRAM area(s)
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 10 Aug 2015 13:11:27 +0000 (15:11 +0200)]
arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize()
Rework these functions so that dram_init_banksize() does not call
dram_init() again. It only needs to set the banksize values in the
bdinfo struct.
Make sure to also clip the size of the last bank if it exceeds the
maximum allowed value of 3 GiB (0xc000.0000). Otherwise other
address windows (e.g. PCIe) will overlap with this memory window.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 6 Aug 2015 12:27:36 +0000 (14:27 +0200)]
arm: mvebu: Move CONFIG_SYS_TEXT_BASE to an address < 16 MiB
This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada
XP / 38x boards in mainline U-Boot. This is done in preparation for
the ECC SDRAM scrubbing that needs to be done in the main U-Boot.
The SPL (previously bin_hdr) has already scrubbed the area:
0x0000.0000 - 0x0100.0000
In this area this main U-Boot needs to get loaded. The main U-Boot
then can scrub the remaining SDRAM area while running from this
location.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 3 Aug 2015 11:15:31 +0000 (13:15 +0200)]
arm: mvebu: Display ECC enabled / disabled upon bootup
This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM
bootup text. Making it easier for board with SPD DIMM's to see,
if ECC is enabled or not.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Anton Schubert [Thu, 23 Jul 2015 13:02:09 +0000 (15:02 +0200)]
arm: mvebu: add multiple usb-hostcontroller support for AXP
This patch adds support for multiple hostcontrollers to the ehci-marvell driver
and enables all 3 usb-hcs on the db-mv784mp-gp board.
It depends on the initial Armada XP usb support patch from Stefan.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 22 Jul 2015 16:05:43 +0000 (18:05 +0200)]
arm: mvebu: db-mv785mp-gp: Add USB/EHCI support
This patch enabled the USB/EHCI support for the Marvell
DB-MV784MP-GP Armada XP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 22 Jul 2015 16:26:13 +0000 (18:26 +0200)]
arm: mvebu: Enable USB EHCI support on Armada XP
This patch enables the USB EHCI support for the Marvell Armada XP (AXP)
SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure
the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done
this already in the bin_hdr (SPL U-Boot). Without this, accessing the
controller registers in U-Boot or Linux will hang the CPU.
Additionally, the AXP uses a different USB EHCI base address. This
patch also takes care of this by runtime SoC detection in the Marvell
EHCI driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 16 Jul 2015 08:40:05 +0000 (10:40 +0200)]
arm: mvebu: Enable NAND controller on MVEBU SoC's
This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.
As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 11:28:39 +0000 (13:28 +0200)]
arm: mvebu: Disable MBUS error propagation
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 11:23:52 +0000 (13:23 +0200)]
arm: mvebu: Flush caches and disable MMU only on A38x
Only with disabled MMU its possible to switch the base register address
on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also
not accessible, as its still locked to cache.
So to fully release / unlock this area from cache, we need to first
flush all caches, then disable the MMU and disable the L2 cache.
On Armada XP this does not seem to be needed. Even worse, with this
code added, I sometimes see strange input charactes loss from the
console.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 10:44:51 +0000 (12:44 +0200)]
arm: mvebu: Setup the MBUS bridge registers
With this patch, the MBUS bridge registers (base and size) are
configured upon each call to mbus_dt_setup_win(). This is needed, since
the board code can also call this function in later boot stages. As
done in the maxbcm board.
This is needed to fix a problem with the secondary CPU's not booting
in Linux on AXP.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 10:55:07 +0000 (12:55 +0200)]
arm: mvebu: Change MBUS base addresses and sizes
This patch changes the MBUS base addresses and sizes to use more
generic names and also adds defines for the sizes. It also moves
the base address to higher addresses.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 3 Aug 2015 10:13:09 +0000 (12:13 +0200)]
arm: mvebu: db-mv784mp-gp.h: Fix image creation - use correct offset
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Tue, 11 Aug 2015 15:08:01 +0000 (17:08 +0200)]
arm: mvebu: sdram: Enable ECC support on Armada XP
This is tested on the DB-MV784MP-GP eval board. To really enable ECC
support on this board the I2C EEPROM needs to get changed. As it
saves the enabling of ECC support internally. For this the following
commands can be used to enable ECC support on this board:
Its recommended for first save (print) the value(s) in this EEPROM
address:
=> i2c md 4e 0.1 2
0000: 05 00 ..
To enable ECC support you need to set bit 1 in the 2nd byte:
Marvell>> i2c mw 4e 1.1 02
Marvell>> i2c md 4e 0.1 2
0000: 05 02 ..
To disable ECC support again, please use this command:
Marvell>> i2c mw 4e 1.1 00
Marvell>> i2c md 4e 0.1 2
0000: 05 00 ..
On other AXP boards, simply plugging an ECC DIMM should be enough to
enable ECC support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 6 Aug 2015 08:23:52 +0000 (10:23 +0200)]
arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INIT
CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid
of all references here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Sylvain Lemieux [Mon, 27 Jul 2015 17:37:39 +0000 (13:37 -0400)]
i2c: lpc32xx: fix write timeout
Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when parameters alen = 0 and len = 0.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Mon, 27 Jul 2015 17:37:38 +0000 (13:37 -0400)]
i2c: lpc32xx: fix read timeout
Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when parameters alen != 0 and len = 0.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Mon, 27 Jul 2015 17:37:37 +0000 (13:37 -0400)]
i2c: lpc32xx: use api to get hclk instead of fix value
The HCLK is not constant and can take different value; use the api function to get the value of the HCLK for the I2C clock high and low computation.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Mon, 27 Jul 2015 17:37:36 +0000 (13:37 -0400)]
arm: lpc32xx: gpio macro for pin mapping
Add LPC32xx GPIO interface macro for pin mapping.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Mon, 27 Jul 2015 17:37:35 +0000 (13:37 -0400)]
lpc32xx: cpu: add support for soft reset
Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset).
To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Sylvain Lemieux [Mon, 27 Jul 2015 17:37:34 +0000 (13:37 -0400)]
arm: lpc32xx: mux: add missing registers
Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Marek Vasut [Sun, 2 Aug 2015 23:28:56 +0000 (01:28 +0200)]
sf: Make 4K sector support configurable
Make the support for 4K subpage I/O on a SPI NOR flash configurable.
A board which requires the SPI NOR to be accessed in larger 32KiB
or 64KiB pages can disable the 4K subpage support, but by default,
the support for 4K subpage I/O is enabled. The functionality of this
option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux.
This is extremely useful in case one uses UBI on a SPI NOR flash.
UBI needs at least 15k EBs and can not work on a flash which uses
4k ones, so disabling the support for 4k subpages lets UBI work on
such flash.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Thomas Abraham [Mon, 3 Aug 2015 12:28:01 +0000 (17:58 +0530)]
ARM: exynos: fix regression for Origen4210
The do_lowlevel_init() function includes certian CA15 specific L2 cache
configuration which is only applicable on Exynos5420 and members of its
family. Fix the regression on Origen4210 by skipping the Exynos5420
specific portions of the code.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Thomas Abraham [Mon, 3 Aug 2015 12:28:00 +0000 (17:58 +0530)]
ARM: exynos: move SoC sources to mach-exynos
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tom Rini [Fri, 14 Aug 2015 22:39:44 +0000 (18:39 -0400)]
Delete an accidentally added .rej file
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 14 Aug 2015 17:43:23 +0000 (13:43 -0400)]
Merge git://git.denx.de/u-boot-x86
Tom Rini [Fri, 14 Aug 2015 15:37:48 +0000 (11:37 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-pmic
Anatolij Gustschin [Fri, 14 Aug 2015 05:04:19 +0000 (07:04 +0200)]
powerpc: ipek01: convert to generic board
Also update maintainer info.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Anatolij Gustschin [Fri, 14 Aug 2015 05:01:15 +0000 (07:01 +0200)]
powerpc: inka4x0: convert to generic board
Also update maintainer info.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Anatolij Gustschin [Thu, 13 Aug 2015 21:58:01 +0000 (23:58 +0200)]
powerpc: socrates: convert to generic board
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: York Sun <yorksun@freescale.com>
Anatolij Gustschin [Thu, 13 Aug 2015 21:58:00 +0000 (23:58 +0200)]
powerpc: v38b: convert to generic board
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>