oweals/u-boot.git
13 years agosf: unify status polling for ready bit
Mike Frysinger [Mon, 10 Jan 2011 07:20:12 +0000 (02:20 -0500)]
sf: unify status polling for ready bit

All of the spi flash drivers implement the status register polling for
detecting the device ready state, so unify them all in a new helper
function -- spi_flash_wait_ready.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agosf: unify read/write helpers
Mike Frysinger [Mon, 10 Jan 2011 07:20:11 +0000 (02:20 -0500)]
sf: unify read/write helpers

These functions largely do the same exact thing, so unify them all
into one basic function.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Sun, 10 Apr 2011 19:24:40 +0000 (21:24 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

13 years agoMerge branch 'next' of git://git.denx.de/u-boot-nios
Wolfgang Denk [Sun, 10 Apr 2011 19:20:28 +0000 (21:20 +0200)]
Merge branch 'next' of git://git.denx.de/u-boot-nios

13 years agoMerge branch 'master' of git://git.denx.de/u-boot-blackfin
Wolfgang Denk [Sun, 10 Apr 2011 19:06:27 +0000 (21:06 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-blackfin

13 years agopowerpc/85xx: Removed clearing of L2-as-SRAM
Fabian Cenedese [Mon, 14 Feb 2011 11:59:33 +0000 (12:59 +0100)]
powerpc/85xx: Removed clearing of L2-as-SRAM

Removed clearing of L2 cache as SRAM as it is not necessary without ECC.
This also speeds up the booting process.

Signed-off-by: Fabian Cenedese <cenedese@indel.ch>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_esdhc: Deal with watermark level register related changes
Priyanka Jain [Wed, 9 Feb 2011 03:54:10 +0000 (09:24 +0530)]
fsl_esdhc: Deal with watermark level register related changes

P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:

9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add PBL boot from SPI flash support on P4080DS
Shaohui Xie [Wed, 16 Mar 2011 02:10:32 +0000 (10:10 +0800)]
powerpc/85xx: Add PBL boot from SPI flash support on P4080DS

PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.

Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Update default hwconfig on P1022DS
Jiang Yutang [Thu, 24 Feb 2011 08:11:55 +0000 (16:11 +0800)]
powerpc/85xx: Update default hwconfig on P1022DS

Set default configuration to have SDHC controller enabled,
AUDIO enabled(codec clock sources is 12MHz) and disable TDM.

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS
Jiang Yutang [Fri, 4 Mar 2011 02:25:54 +0000 (10:25 +0800)]
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS

For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Enable support for ATI graphics cards on P1022DS
Jiang Yutang [Mon, 24 Jan 2011 10:21:19 +0000 (18:21 +0800)]
powerpc/85xx: Enable support for ATI graphics cards on P1022DS

Make the support for ATI graphics cards mutually exclusive with DIU.

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agop4080ds: remove rev1-specific code for the SERDES8 erratum
Timur Tabi [Fri, 25 Mar 2011 20:10:00 +0000 (15:10 -0500)]
p4080ds: remove rev1-specific code for the SERDES8 erratum

Remove the SERDES8 erratum work-around code that only applied to P4080
rev1, which is not supported by this version of U-Boot.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agop4080ds: add README.p4080ds which documents the "serdes" hwconfig option
Timur Tabi [Fri, 25 Mar 2011 19:11:48 +0000 (14:11 -0500)]
p4080ds: add README.p4080ds which documents the "serdes" hwconfig option

Add documentation for the "serdes" hwconfig option, which is used to
specify the status of SerDes banks two and three for the SERDES8 erratum
work-around.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Drop CONFIG_VIDEO support on corenet_ds boards
Kumar Gala [Fri, 8 Apr 2011 07:46:39 +0000 (02:46 -0500)]
powerpc/85xx: Drop CONFIG_VIDEO support on corenet_ds boards

We don't really ever use Video cards on corenet_ds style boards and its
bloating our image which is close the its max size.  Drop support and
also kill some defines for non-PNP PCI which we never use.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agonios2: reset cfi flash before reading env
Thomas Chou [Tue, 18 Jan 2011 03:13:56 +0000 (11:13 +0800)]
nios2: reset cfi flash before reading env

Flash might be in unknown state when u-boot is started with jtag.
And got wrong env data. So reset it in board early init.

We cannot use generic cfi flash routines, because flash_init() is
not run yet.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
13 years agopowerpc/85xx: rename NAND prefixes to CONFIG_SYS
Matthew McClintock [Tue, 5 Apr 2011 19:39:33 +0000 (14:39 -0500)]
powerpc/85xx: rename NAND prefixes to CONFIG_SYS

renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM
and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more
appropriate CONFIG_SYS prefix as well as be consistent with 83xx.

Signed-off-by: Matthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoBlackfin: bf526-ezbrd: get MAC from flash
Mike Frysinger [Thu, 17 Mar 2011 21:32:51 +0000 (17:32 -0400)]
Blackfin: bf526-ezbrd: get MAC from flash

The MAC address is stored in the last flash sector rather than OTP.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf518f-ezbrd: get MAC from flash
Mike Frysinger [Thu, 17 Mar 2011 21:14:14 +0000 (17:14 -0400)]
Blackfin: bf518f-ezbrd: get MAC from flash

The MAC address is stored in the last flash sector rather than OTP.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf548-ezkit: move env sector
Mike Frysinger [Thu, 17 Mar 2011 21:07:47 +0000 (17:07 -0400)]
Blackfin: bf548-ezkit: move env sector

U-Boot itself takes up more than 0x40000 bytes, so we can't use that
sector for the environment.  Move it down a page.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: replace "bfin_reset_or_hang()" with "panic()"
Kyle Moffett [Mon, 7 Mar 2011 17:37:30 +0000 (12:37 -0500)]
Blackfin: replace "bfin_reset_or_hang()" with "panic()"

The bfin_reset_or_hang function unnecessarily duplicates the panic()
logic based on CONFIG_PANIC_HANG.

This patch deletes 20 lines of code and just calls panic() instead.
This also makes the following generic-restart conversion patch simpler.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: adi boards: enable CONFIG_MONITOR_IS_IN_RAM
Mike Frysinger [Mon, 10 Jan 2011 05:19:47 +0000 (00:19 -0500)]
Blackfin: adi boards: enable CONFIG_MONITOR_IS_IN_RAM

Our monitor is always in RAM, so enable this define for the CFI layer.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bfin_sdh: add support for multiblock operations
Sonic Zhang [Thu, 30 Dec 2010 08:38:00 +0000 (08:38 +0000)]
Blackfin: bfin_sdh: add support for multiblock operations

Don't forget to count full data size for the multiblock operation request.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bfin_sdh: set all timer bits before transfer
Cliff Cai [Mon, 7 Dec 2009 06:12:11 +0000 (06:12 +0000)]
Blackfin: bfin_sdh: set all timer bits before transfer

The timer register is 32bits, not 16bit, so 0xFFFF won't fill it.
Write out -1 to make sure to fill the whole thing.

Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: adi boards: enable ldrinfo
Mike Frysinger [Sun, 26 Dec 2010 17:35:21 +0000 (12:35 -0500)]
Blackfin: adi boards: enable ldrinfo

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: ldrinfo: new command
Mike Frysinger [Sun, 26 Dec 2010 17:34:49 +0000 (12:34 -0500)]
Blackfin: ldrinfo: new command

Simple command to decode/check an LDR image before we try to boot it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bootldr: use common defines
Mike Frysinger [Sun, 26 Dec 2010 17:34:08 +0000 (12:34 -0500)]
Blackfin: bootldr: use common defines

Now that the common bootrom.h sets up defines for us, switch to them
rather than our own local set.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bootrom.h: sync with toolchain
Mike Frysinger [Sun, 26 Dec 2010 17:33:35 +0000 (12:33 -0500)]
Blackfin: bootrom.h: sync with toolchain

We need the updated LDR bit defines for our LDR utils.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: adi boards: drop old ELF define
Mike Frysinger [Sun, 26 Dec 2010 17:26:09 +0000 (12:26 -0500)]
Blackfin: adi boards: drop old ELF define

This define isn't used anywhere anymore, so punt it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf506f-ezkit: new board port
Mike Frysinger [Fri, 17 Dec 2010 20:28:43 +0000 (15:28 -0500)]
Blackfin: bf506f-ezkit: new board port

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: default to L1 bank A when L1 bank B does not exist
Mike Frysinger [Sat, 25 Dec 2010 00:31:55 +0000 (19:31 -0500)]
Blackfin: default to L1 bank A when L1 bank B does not exist

Some parts lack Bank B in L1 data, so have the linker script fall back to
Bank A when that happens.  This way we can still leverage L1 data.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: turn off caches when self initializing
Mike Frysinger [Fri, 24 Dec 2010 19:46:12 +0000 (14:46 -0500)]
Blackfin: turn off caches when self initializing

When bootstrapping ourselves on the fly at runtime (via "go"), we need to
turn off the caches to avoid taking software exceptions.  Since caches
need CPLBs and CPLBs need exception handlers, but we're about to rewrite
the code in memory where those exception handlers live, we need to turn
off caches first.

This new code also encourages a slight code optimization by storing the
MMR bases in dedicated registers so we don't have to fully load up the
pointer regs multiple times.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: only check for os log when we have external memory
Mike Frysinger [Fri, 24 Dec 2010 18:19:25 +0000 (13:19 -0500)]
Blackfin: only check for os log when we have external memory

If the part has no external memory configured, then there will be no os
log for us to check, and any attempt to access that memory will trigger
hardware errors.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: BF537: unify duplicated headers
Mike Frysinger [Fri, 24 Dec 2010 23:28:31 +0000 (18:28 -0500)]
Blackfin: BF537: unify duplicated headers

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: BF52x: unify duplicated headers
Mike Frysinger [Fri, 24 Dec 2010 23:28:27 +0000 (18:28 -0500)]
Blackfin: BF52x: unify duplicated headers

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: drop duplicate system mmr and L1 scratch defines
Mike Frysinger [Fri, 24 Dec 2010 23:21:53 +0000 (18:21 -0500)]
Blackfin: drop duplicate system mmr and L1 scratch defines

Common code already takes care of setting up these defines when a port
hasn't specified them, so punt the duplicate values.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: BF50x: new processor port
Mike Frysinger [Fri, 17 Dec 2010 20:25:09 +0000 (15:25 -0500)]
Blackfin: BF50x: new processor port

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: fix bd_t handling
Mike Frysinger [Fri, 24 Dec 2010 17:48:16 +0000 (12:48 -0500)]
Blackfin: fix bd_t handling

The recent global data changes (making the size autogenerated) broke the
board info handling on Blackfin ports as we were lying and lumping the
bd_t size in with the gd_t size.  So use the new dedicated bd_t size to
setup its own address in memory.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf561-ezkit/ibf-dsp561: invert env offset/addr logic
Mike Frysinger [Thu, 23 Dec 2010 23:07:01 +0000 (18:07 -0500)]
Blackfin: bf561-ezkit/ibf-dsp561: invert env offset/addr logic

Have CONFIG_ENV_ADDR be based on CONFIG_ENV_OFFSET rather than the other
way around so that we can use CONFIG_ENV_OFFSET during build.  It also
avoids a little address duplication.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf537: fix L1 data defines
Mike Frysinger [Thu, 23 Dec 2010 20:30:14 +0000 (15:30 -0500)]
Blackfin: bf537: fix L1 data defines

The __BFIN_DEF_ADSP_BF537_proc__ define isn't setup anymore, so use
the one coming from the compiler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf537-minotaur/bf537-srv1: undefine nfs when net is disabled
Mike Frysinger [Thu, 23 Dec 2010 04:26:08 +0000 (23:26 -0500)]
Blackfin: bf537-minotaur/bf537-srv1: undefine nfs when net is disabled

Fixes a build error due to new partial linking logic.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: serial: clean up muxing a bit
Mike Frysinger [Fri, 17 Dec 2010 21:23:59 +0000 (16:23 -0500)]
Blackfin: serial: clean up muxing a bit

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf525-ucr2: new board port
Chong Huang [Tue, 30 Nov 2010 08:36:23 +0000 (03:36 -0500)]
Blackfin: bf525-ucr2: new board port

Signed-off-by: Chong Huang <chuang@ucrobotics.com>
Signed-off-by: Haitao Zhang <minipanda@linuxrobot.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: dnp5370: new board port
Andreas Schallenberg [Wed, 17 Nov 2010 18:51:33 +0000 (13:51 -0500)]
Blackfin: dnp5370: new board port

Info about the hardware can be found here:
http://www.dilnetpc.com/dnp0086.htm

Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf537-pnav/blackstamp/blackvme: drop empty config.mk files
Mike Frysinger [Thu, 23 Dec 2010 20:04:55 +0000 (15:04 -0500)]
Blackfin: bf537-pnav/blackstamp/blackvme: drop empty config.mk files

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf527-sdp: update custom CFLAGS paths
Mike Frysinger [Thu, 23 Dec 2010 20:03:53 +0000 (15:03 -0500)]
Blackfin: bf527-sdp: update custom CFLAGS paths

Looks like the filesystem shuffling missed the SDP board.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: move CONFIG_BFIN_CPU back to board config.h
Mike Frysinger [Thu, 23 Dec 2010 19:58:37 +0000 (14:58 -0500)]
Blackfin: move CONFIG_BFIN_CPU back to board config.h

This is a revert of 821ad16fa9900c as Wolfgang doesn't like the new code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: unify bootmode based LDR_FLAGS setup
Mike Frysinger [Thu, 23 Dec 2010 19:19:23 +0000 (14:19 -0500)]
Blackfin: unify bootmode based LDR_FLAGS setup

Unify this convention for all Blackfin boards.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: drop CONFIG_SYS_TEXT_BASE from boards
Mike Frysinger [Thu, 23 Dec 2010 19:13:41 +0000 (14:13 -0500)]
Blackfin: drop CONFIG_SYS_TEXT_BASE from boards

We don't want/use this value for Blackfin boards, so punt it and have the
common code error out when people try to use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: skip RAM display for 0 mem systems
Mike Frysinger [Mon, 20 Dec 2010 10:18:55 +0000 (05:18 -0500)]
Blackfin: skip RAM display for 0 mem systems

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agoBlackfin: bf518f-ezbrd: don't require SPI logic all the time
Mike Frysinger [Fri, 3 Dec 2010 05:31:48 +0000 (00:31 -0500)]
Blackfin: bf518f-ezbrd: don't require SPI logic all the time

Only the first run of boards had a ksz switch on it, so if building for a
newer silicon rev or SPI is disabled, don't bother checking for the ksz.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
13 years agomtd, cfi: introduce void flash_protect_default(void)
Heiko Schocher [Mon, 4 Apr 2011 06:10:21 +0000 (08:10 +0200)]
mtd, cfi: introduce void flash_protect_default(void)

collect code which protects default sectors in a function, called
flash_protect_default. So boardspecific code can call it too.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
13 years agocfi_flash: use AMD fixups for AMIC (e.g. A29L160A series) too
Mario Schuknecht [Mon, 21 Feb 2011 12:13:14 +0000 (13:13 +0100)]
cfi_flash: use AMD fixups for AMIC (e.g. A29L160A series) too

Signed-off-by: Mario Schuknecht <m.schuknecht@dresearch.de>
Signed-off-by: Steffen Sledz <sledz@dresearch.de>
Signed-off-by: Stefan Roese <sr@denx.de>
13 years agopowerpc/85xx: Add some defines & registers in immap_85xx.h
Zhao Chenhui [Thu, 27 Jan 2011 11:02:47 +0000 (19:02 +0800)]
powerpc/85xx: Add some defines & registers in immap_85xx.h

* Added SDHCDCR register to GUR struct
* Added SDHCDCR_CD_INV define related to SDHCDCR
* Added Pin Muxing define related to TDM on P102x

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add P1021 specific QE and UEC support
Haiying Wang [Fri, 11 Feb 2011 07:25:30 +0000 (01:25 -0600)]
powerpc/85xx: Add P1021 specific QE and UEC support

P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode.  QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.

Also added relevant QE support defines unique to P1021.

The P1021 QE is shared on P1012, P1016, and P1025.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT
Zhao Chenhui [Fri, 28 Jan 2011 09:58:37 +0000 (17:58 +0800)]
powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Tue, 5 Apr 2011 10:24:20 +0000 (12:24 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Conflicts:
drivers/usb/host/ehci-pci.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
13 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Wolfgang Denk [Tue, 5 Apr 2011 10:17:38 +0000 (12:17 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

13 years agopowerpc: clean up DIU macro definitions for Freescale reference boards
Timur Tabi [Tue, 15 Feb 2011 23:09:19 +0000 (17:09 -0600)]
powerpc: clean up DIU macro definitions for Freescale reference boards

Clean up the macro defintions used to enable DIU (video) support on the
MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS,
which is newer.  Add software cursor support to all three boards.

Also document the CONFIG_FSL_DIU_FB in the README.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Enable eSDHC boot support on P2020 DS
Jerry Huang [Mon, 24 Jan 2011 17:09:54 +0000 (17:09 +0000)]
powerpc/85xx: Enable eSDHC boot support on P2020 DS

We implement our own mmc_get_env_addr since the environment variables are
written to just after the u-boot image on SDCard, so we must read the MBR
to get the start address and code length of the u-boot image, then
calculate the address of the env.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoenv_mmc: Allow board code to override the environment address
Mingkai Hu [Mon, 24 Jan 2011 17:09:55 +0000 (17:09 +0000)]
env_mmc: Allow board code to override the environment address

On some boards the environment may not be located at a fixed address in
the MMC/SDHC card.  This allows those boards to implement their own
means to report what address the environment is located at.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Fix typo for address hashing message
Kumar Gala [Fri, 18 Mar 2011 16:53:06 +0000 (11:53 -0500)]
powerpc/8xxx: Fix typo for address hashing message

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agompc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements
Kyle Moffett [Mon, 28 Mar 2011 15:35:48 +0000 (11:35 -0400)]
mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements

The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header.  This dramatically improves the
readability of the switch statments.

In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC
Kyle Moffett [Tue, 15 Mar 2011 15:23:47 +0000 (11:23 -0400)]
fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC

The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.

Since all of the inputs to this are 32-bit (nanoseconds, clock cycles,
and DDR frequencies), we can easily restructure the computation to use
the "do_div()" function to perform 64-bit/32-bit divide operations.

On 64-bit this change is basically a no-op, because do_div is
implemented as a literal 64-bit divide operation and the instruction
scheduling works out almost the same.

On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is
over 1.1kB of code and thousands of heavily dependent cycles to compute,
all of which is linked from libgcc.  Another 1.2kB of code comes in for
the function __umoddi3.

It should be noted that nothing else in U-Boot or the Linux kernel seems
to require a full 64-bit divide on my 32-bit PowerPC.

Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: York Sun <yorksun@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020
Laurentiu TUDOR [Tue, 15 Mar 2011 14:37:36 +0000 (16:37 +0200)]
powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020

We utilize the compatible string to find the node to add fsl,liodn
property to.  However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.

Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness.  On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.

Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add 36-bit address map support to P1022DS
Jiang Yutang [Mon, 24 Jan 2011 10:21:15 +0000 (18:21 +0800)]
powerpc/85xx: Add 36-bit address map support to P1022DS

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agotsec: add AR8021 PHY support
Li Yang [Thu, 27 Jan 2011 11:02:50 +0000 (19:02 +0800)]
tsec: add AR8021 PHY support

Signed-off-by: Li Yang <leoli@freescale.com>
13 years agopowerpc/85xx: Update timer-frequency prop in ptp_timer node of device tree
bhaskar upadhaya [Wed, 2 Feb 2011 14:44:28 +0000 (14:44 +0000)]
powerpc/85xx: Update timer-frequency prop in ptp_timer node of device tree

Fix up the device tree property associated with the IEEE 1588 timer
source frequency.  Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support).  The eTSEC clock is ccb_clk/2.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Fix determining Fman freq on P1023
Kumar Gala [Thu, 10 Mar 2011 12:09:20 +0000 (06:09 -0600)]
powerpc/85xx: Fix determining Fman freq on P1023

On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2
of it.  Also we only have one Fman so no need for the code to deal with
a second.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Fixup determining PME, FMan freq
Kumar Gala [Wed, 16 Feb 2011 08:03:29 +0000 (02:03 -0600)]
powerpc/85xx: Fixup determining PME, FMan freq

On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.

We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)

On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL.  On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.

On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV.  On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add support for ULI1575 PCI EHCI module on MPC8572DS
Zhao Chenhui [Fri, 4 Mar 2011 08:31:41 +0000 (16:31 +0800)]
powerpc/85xx: Add support for ULI1575 PCI EHCI module on MPC8572DS

MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage
device support using PCI EHCI module.

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Disable ECC in considering performance on MPC8572DS
Zhao Chenhui [Wed, 2 Mar 2011 08:44:52 +0000 (16:44 +0800)]
powerpc/85xx: Disable ECC in considering performance on MPC8572DS

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Replace memctl_intlv_ctl with hwconfig on MPC8572DS
Zhao Chenhui [Wed, 2 Mar 2011 08:44:36 +0000 (16:44 +0800)]
powerpc/85xx: Replace memctl_intlv_ctl with hwconfig on MPC8572DS

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB
Poonam Aggrwal [Wed, 9 Feb 2011 20:05:29 +0000 (20:05 +0000)]
powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB

Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB
Poonam Aggrwal [Mon, 7 Feb 2011 11:47:28 +0000 (17:17 +0530)]
powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB

Changed the following DDR timing parameters for 800Mt/s:
tRRT    BL/2+1 to  BL/2
tWWT    BL/2+1 to  BL/2
tWRT    BL/2+1 to  BL/2
tRWT    BL/2+1 to  BL/2
REFINT  6500ns to  7800ns

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Removed P1/P2 RDB RevB support
Poonam Aggrwal [Wed, 9 Feb 2011 17:54:11 +0000 (23:24 +0530)]
powerpc/85xx: Removed P1/P2 RDB RevB support

RevB boards never really made it outside of Freescale and have been
replaced with RevC & RevD which had various board bug fixes.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Read board switch settings on p1_p2_rdb
Priyanka Jain [Tue, 8 Feb 2011 07:48:34 +0000 (13:18 +0530)]
powerpc/85xx: Read board switch settings on p1_p2_rdb

PCA9557 is parallel I/O expansion device on I2C bus which stores various
board switch settings like NOR Flash-Bank selection, SD Data width.

On board:
switch SW5[6] is to select width for eSDHC
        ON  - 4-bit [Enable eSPI]
        OFF - 8-bit [Disable eSPI]

switch SW4[8] is to select NOR Flash Bank for Booting
        OFF - Primary Bank
        ON  - Secondary Bank

Read board switch settings on p1_p2_rdb and configure corresponding
eSDHC width.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb
Priyanka Jain [Tue, 8 Feb 2011 07:43:15 +0000 (13:13 +0530)]
powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb

Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash
boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
  size of image that could be loaded in SRAM mode and would require three
  stage boot loader (TPL).

Changes done:
 1. CONFIG_SYS_TEXT_BASE to 0x11000000
 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1
Timur Tabi [Wed, 9 Feb 2011 02:00:09 +0000 (02:00 +0000)]
fsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1

The NXID EEPROM format comes in two versions, v0 and v1.  The only
difference is in the number of MAC addresses that can be stored.  NXID v0
supports eight addresses, and NXID v1 supports 23.

Rather than allow a board to choose which version to support, NXID v0 is
now considered deprecated.  The EEPROM code is updated to support only
NXID v1, but it can still read EEPROMs formatted with v0.  In these cases,
the EEPROM data is loaded and the CRC is verified, but the data is stored
into a v1 data structure.  If the EEPROM data is written back, it is
written in v1 format.  This allows existing v0-formatted EEPROMs to
continue providing MAC addresses, but any changes to the data will force
an upgrade to the v1 format, while retaining all data.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE
Kumar Gala [Fri, 4 Feb 2011 06:43:34 +0000 (00:43 -0600)]
powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE

CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in
config_mpc85xx.h for those parts with a Frame Manager.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Corrected sdhc clock value for P1010
Priyanka Jain [Tue, 8 Feb 2011 10:15:25 +0000 (15:45 +0530)]
powerpc/85xx: Corrected sdhc clock value for P1010

SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Adds some P1010/P1014 SoC configuration defines
Poonam Aggrwal [Sun, 6 Feb 2011 06:01:44 +0000 (11:31 +0530)]
powerpc/85xx: Adds some P1010/P1014 SoC configuration defines

Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR
and SDHC erratum.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Support for Freescale P1024/P1025 processor
Kumar Gala [Sat, 5 Feb 2011 19:45:07 +0000 (13:45 -0600)]
powerpc/85xx: Support for Freescale P1024/P1025 processor

Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.

P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.

Added comments in config_mpc85xx.h to denote single core versions of
processors.

Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agoechi: add ULI1575 PCI ID
Zhao Chenhui [Sun, 13 Mar 2011 15:00:40 +0000 (10:00 -0500)]
echi: add ULI1575 PCI ID

Add ULI1575 EHCI controller to the list of the supported devices.

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: load ucode from nand flash before qe_init
Haiying Wang [Mon, 7 Feb 2011 21:14:15 +0000 (16:14 -0500)]
powerpc/85xx: load ucode from nand flash before qe_init

In the case the QE's microcode is stored in nand flash, we need to load it from
NAND flash to ddr first then the qe_init can get the ucode correctly.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_ddr: Adds 16 bit DDR Data width option
Poonam Aggrwal [Mon, 7 Feb 2011 09:39:51 +0000 (15:09 +0530)]
fsl_ddr: Adds 16 bit DDR Data width option

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB
Poonam Aggrwal [Mon, 7 Feb 2011 09:38:29 +0000 (15:08 +0530)]
powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Display DIMM model
York Sun [Fri, 4 Feb 2011 21:58:00 +0000 (13:58 -0800)]
powerpc/8xxx: Display DIMM model

Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Update fixed DDR3 timing table for P4080DS
York Sun [Fri, 4 Feb 2011 21:57:59 +0000 (13:57 -0800)]
powerpc/85xx: Update fixed DDR3 timing table for P4080DS

Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Fix LAW init to respect pre-initialized entries
Kumar Gala [Thu, 3 Feb 2011 15:02:13 +0000 (09:02 -0600)]
powerpc/8xxx: Fix LAW init to respect pre-initialized entries

If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.

In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agofsl_pci: Add support for FSL PCIe controllers v2.x
Prabhakar Kushwaha [Fri, 4 Feb 2011 03:30:43 +0000 (09:00 +0530)]
fsl_pci: Add support for FSL PCIe controllers v2.x

FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x

Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window

FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register

Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.

To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Refactor Qman/Portal support to be shared between SoCs
Haiying Wang [Thu, 20 Jan 2011 22:26:31 +0000 (22:26 +0000)]
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs

There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.

* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
  (features doesn't exist on P1023/P1017)

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Add support for Freescale P1023/P1017 Processors
Roy Zang [Fri, 4 Feb 2011 04:14:19 +0000 (22:14 -0600)]
powerpc/85xx: Add support for Freescale P1023/P1017 Processors

Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
  (fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPL
Kumar Gala [Fri, 4 Feb 2011 02:21:42 +0000 (20:21 -0600)]
powerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPL

Slim down NAND SPL build a bit as we don't need read_tlbcam_entry.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc: Add cpu_secondary_init_r to allow for initialization post env setup
Kumar Gala [Wed, 2 Feb 2011 17:23:50 +0000 (11:23 -0600)]
powerpc: Add cpu_secondary_init_r to allow for initialization post env setup

We can simplify some cpu/SoC level initialization by moving it to be
after the environment and non-volatile storage is setup as there might
be dependancies on such things in various boot configurations.

For example for FSL SoC's with QE if we boot from NAND we need it setup
to extra the ucode image to initialize the QE.  If we always do this
after environment & non-volatile storage is working we can have the code
be the same regardless of NOR, NAND, SPI, MMC boot.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Cleanup some QE related defines
Kumar Gala [Tue, 1 Feb 2011 05:09:25 +0000 (23:09 -0600)]
powerpc/85xx: Cleanup some QE related defines

Move some processor specific QE defines into config_mpc85xx.h and use
QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct.

Also fixed up some comment style issues in immap_qe.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board
Kumar Gala [Tue, 1 Feb 2011 04:18:47 +0000 (22:18 -0600)]
powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board

Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing.  The only variations are in how many
controllers or DIMMs per controller exist.  To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.

We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()
Kumar Gala [Tue, 1 Feb 2011 02:36:02 +0000 (20:36 -0600)]
powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()

Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq().  If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Remove config.mk for nand linker script
Kumar Gala [Mon, 31 Jan 2011 21:57:01 +0000 (15:57 -0600)]
powerpc/85xx: Remove config.mk for nand linker script

Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc: Move cpu specific lmb reserve to arch_lmb_reserve
Kumar Gala [Mon, 31 Jan 2011 21:51:20 +0000 (15:51 -0600)]
powerpc: Move cpu specific lmb reserve to arch_lmb_reserve

We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems.  We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
13 years agopowerpc/85xx: Update P2020DS default env settings
Li Yang [Mon, 24 Jan 2011 17:09:52 +0000 (17:09 +0000)]
powerpc/85xx: Update P2020DS default env settings

Read MAC address from EEPROM. Add hwconfig settings.

Modified the default othbootargs to include the cache-sram-size
parameter. This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.

Also cleanup some of the boot commands.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>