Tom Rini [Fri, 11 May 2018 18:54:57 +0000 (14:54 -0400)]
SPDX: Correct SPDX tags from recent xilinx merge
Correct the SPDX tag format.
Fixes:
3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 11 May 2018 15:45:28 +0000 (11:45 -0400)]
Merge tag 'xilinx-for-v2018.07' of git://denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING
zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation
mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode
nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params
scsi:
- convert ceva sata to UCLASS_AHCI
timer:
- Add Cadence TTC for ZynqMP r5
watchdog:
- Minor cadence driver cleanup
Tom Rini [Fri, 11 May 2018 11:09:21 +0000 (07:09 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:10 +0000 (12:37 +0530)]
arm64: zynqmp: Enable UHS support for ZCU102 Rev1.0 board
This patch enables UHS support for ZynqMP zcu102 rev 1.0
board.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:09 +0000 (12:37 +0530)]
mmc: zynq_sdhci: Add support for SD3.0
This patch adds support of SD3.0 for ZynqMP.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:08 +0000 (12:37 +0530)]
mmc: sdhci: Read capabilities register1 and update host caps
This patch reads the capabilities register1 and update the host
caps accordingly for mmc layer usage. This patch mainly reads
for UHS capabilities inorder to support SD3.0.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:07 +0000 (12:37 +0530)]
mmc: sdhci: Invoke platform specific tuning and delay routines
This patch adds support to invoke any platform specific tuning
and delay routines if available.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:06 +0000 (12:37 +0530)]
sdhci: Add new sdhci ops for platform specific tuning and delays
This patch adds new hooks for any platform specific tuning and
tap delays programing. These are needed for supporting
SD3.0.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:05 +0000 (12:37 +0530)]
mmc: sdhci: Handle execute tuning command in sdhci_send_command
This patch upadted sdhci_send_command to handle execute tuning
command.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:04 +0000 (12:37 +0530)]
mmc: sdhci: Add support for disabling clock
This patch adds support to disable clock if clk_disable
was set and then enable or set clock if the clock was changed
or clock was disabled when clock needs to be enabled.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Thu, 3 May 2018 06:50:54 +0000 (12:20 +0530)]
mmc: Changed the datatype of the variable to handle 64-bit arch
This patch changed the datatype of variable "start" from uint to ulong
to work properly on 64-bit machines as well. Also the return type of
get_timer() function is ulong.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Apr 2018 15:39:46 +0000 (17:39 +0200)]
arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.
This configuration with uart1 was tested on zcu100-revC.
U-Boot
2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)
Model: Xilinx ZynqMP R5
DRAM: 512 MiB
WARNING: Caches not enabled
MMC:
In: serial@
ff010000
Out: serial@
ff010000
Err: serial@
ff010000
Net: Net Initialization Skipped
No ethernet found.
ZynqMP r5>
There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb
20000000 u-boot-r5.elf
setenv autostart no && bootelf -p
20000000
cpu 4 disable && cpu 4 release
10000000 lockstep
or
cpu 4 disable && cpu 4 release
10000000 split
2. Load via jtag when directly to R5
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:52 +0000 (14:18 +0200)]
tools: zynqmpimage: Add bif support
The officially described way to generate boot.bin files for ZynqMP is to
describe the contents of the target binary using a file of the "bif"
format. This file then links to other files that all get packed into a
bootable image.
This patch adds support to read such a .bif file and generate a respective
ZynqMP boot.bin file that can include the normal image and pmu files, but
also supports image partitions now. This makes it a handy replacement for
the proprietary "bootgen" utility that is currently used to generate
boot.bin files with FSBL.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:51 +0000 (14:18 +0200)]
MAINTAINERS: Declare tools/zynqmp* as Xilinx maintained
The zynqmpimage.c and the new zynqmpbif.c files are all maintained by
Xilinx for the Zynq platforms. Let's match them accordingly
in the MAINTAINERS file.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:50 +0000 (14:18 +0200)]
tools: zynqmpimage: Move defines to header
We will add support for ZynqMP bif input files later, so let's move
all structure definitions into a header file that can be used by that
one as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:49 +0000 (14:18 +0200)]
tools: zynqmpimage: Add partition read support
The zynqmp image format has support for inline partitions which are
used by FSBL to describe payloads that are loaded by FSBL itself.
While we can't create images that contain partitions (yet), we should
still at least be able to examine them and show the user what's inside
when we analyze an image created by bootgen.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 30 Apr 2018 07:26:47 +0000 (09:26 +0200)]
arm64: zynqmp: Show model information instead of custom IDENT_STRING
DISPLAY_BOARDINFO in OF case show model identification string from DT.
Enable this feature instead of custom IDENT_STRING which does the same
thing.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Michal Simek [Wed, 25 Apr 2018 09:10:34 +0000 (11:10 +0200)]
arm64: zynqmp: Simplify boot_target variable composition
Call calloc for space allocation only at one location and include if/else
to sprintf. This will simplify run time device adding based on id aliases.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Nitin Jain [Fri, 20 Apr 2018 07:00:40 +0000 (12:30 +0530)]
arm64: zynqmp: Setup MMU map for DDR at run time
This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.
The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.
Signed-off-by: Nitin Jain <nitin.jain@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 13:43:50 +0000 (15:43 +0200)]
arm64: zynqmp: Enable cadence WDT for zcu100
Enable watchdog on zcu100 to make sure if there is a bug in the u-boot
there is proper reset.
Watchdog expires and PMU fw is informed and based on setting proper
action is taken.
The patch is enabling reset-on-timeout feature and also fixing fixed
clock rate for watchdog where 100MHz is max (and also default) clock value.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 13:43:38 +0000 (15:43 +0200)]
arm64: zynqmp: Wire watchdog internals
Enable watchdog in full U-Boot.
Similar changes were done by:
"arm: zynq: Wire watchdog internals"
(sha1:
e6cc3b25d721c3001019f8b44bfaae2a57255162)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 13:22:04 +0000 (15:22 +0200)]
watchdog: cadence: Show used timeout value
Debug message was showing timeout value which was passed to start
function but there is a checking if this value can be setup.
The patch is moving this debug printf function below checking.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 12:41:11 +0000 (14:41 +0200)]
arm64: zynqmp: Reset FPD Watchdog on zcu100
Low level configuration didn't reset FPD Watchdog that's why accessing
it caused u-boot hang.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 25 May 2017 06:45:24 +0000 (12:15 +0530)]
nand: zynq: Send address cycles as per onfi parameter page
Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 25 May 2017 08:55:55 +0000 (14:25 +0530)]
nand: zynq: Add support for 16-bit buswidth
This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 18 Apr 2018 13:00:43 +0000 (15:00 +0200)]
MAINTAINERS: zynqmp: Point to proper zynqmp folder
Point to Zynqmp arm64 cpu folder not to Zynq arm32.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 18 Apr 2018 10:52:48 +0000 (12:52 +0200)]
serial: zynq: Remove header depedency on arm header structure
There is no need to have arm hardware header in this driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 17 Apr 2018 11:40:46 +0000 (13:40 +0200)]
timer: Add Cadence TTC timer counter support
This driver was tested on Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Wed, 3 Jan 2018 07:45:29 +0000 (13:15 +0530)]
microblaze: Dont enable UBI support by default
This patch removes UBI support from defconfig and it can
be enabled from menuconfig as per need.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Wed, 11 Apr 2018 08:43:05 +0000 (14:13 +0530)]
arm64: zynqmp: Add new defconfig for zc1275 revB
This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Apr 2018 11:32:52 +0000 (13:32 +0200)]
scsi: ceva: Convert driver to use UCLASS_AHCI instead of SCSI
In v2018 the patch
"dm: ahci: Correct uclass private data"
(sha1:
bfc1c6b4838501d10aa48c0e92eaf70976f4b2dd)
was causing an issue for ceva_sata.
But this issue is not in v2018.05-rc1 but still converting to
UCLASS_AHCI would make more sense.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 28 Feb 2018 08:50:07 +0000 (09:50 +0100)]
arm: zynq: Remove checkboard and enable DISPLAY_CPUINFO
Now that showing silicon version is part of the CPU
info display, let's remove checkboard().
Note that the generic show_board_info() will still
show the DT 'model' property. For instance:
U-Boot
2018.05-rc2-00025-g611b3ee0159b (Apr 19 2018 - 11:23:12 +0200)
CPU: Zynq 7z045
Silicon: v1.0
Model: Zynq ZC706 Development Board
I2C: ready
Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>,
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
mini configuration doesn't need to show this information.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 17 Jan 2018 13:56:22 +0000 (10:56 -0300)]
arm: zynq: Rework FPGA initialization
This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.
Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 10:36:48 +0000 (12:36 +0200)]
arm: zynq: Enable debug_uart_init in spl when enabled
In past this code was commented and was used for debug purpose.
But there is no reason not to enabled it based on macros.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Fri, 11 May 2018 02:57:41 +0000 (22:57 -0400)]
Merge git://git.denx.de/u-boot-socfpga
Tom Rini [Mon, 7 May 2018 21:02:21 +0000 (17:02 -0400)]
SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed. These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict. This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.
Fixes:
83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style")
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Heinrich Schuchardt [Mon, 7 May 2018 21:00:22 +0000 (23:00 +0200)]
tools/file2include: avoid incorrect comments
Avoid creating incorrect comments like /* ...*/... */ by printing
'.' instead of '*' inside comments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 7 May 2018 20:18:27 +0000 (22:18 +0200)]
include: update log2 header from the Linux kernel
Without the patch gcc 8 produces:
warning: ignoring attribute ‘noreturn’ because it conflicts with
attribute ‘const’ [-Wattributes]
int ____ilog2_NaN(void);
So let's update the include from Linux kernel v4.16.
This removes static checks of ilog2() arguments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 7 May 2018 19:59:34 +0000 (21:59 +0200)]
xyz-modem: va_start() must be matched by va_end()
Every va_start() call must be matched by a va_end() call.
scripts/checkpatch.pl required reformatting the complete function
zm_dprintf().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 7 May 2018 18:38:24 +0000 (20:38 +0200)]
tools/file2include: create Linux style SPDX header
file2include is used to convert a binary file to a C include.
With the patch the SPDX header is written to the first line as
expected by scripts/checkpatch.pl.
Cf. https://www.kernel.org/doc/html/v4.16/process/license-rules.html
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Hannes Schmelzer [Fri, 4 May 2018 08:49:11 +0000 (10:49 +0200)]
bootm: fix 'memory-fixup' for vxWorks boot
The check for having a memory node within the fdt blob is made wrong, we
fix this here.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Alex Kiernan [Thu, 3 May 2018 11:45:08 +0000 (11:45 +0000)]
Fix Ymodem build when DEBUG and CONFIG_USE_TINY_PRINTF are selected
Attempting to build with both DEBUG and CONFIG_USE_TINY_PRINTF along
with CONFIG_SPL_YMODEM_SUPPORT fails at link time:
common/built-in.o: In function `zm_dprintf':
common/xyzModem.c:190: undefined reference to `vsprintf'
Disable Ymodem debug if we don't have full vsprintf support.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Fabio Estevam [Wed, 2 May 2018 23:12:07 +0000 (20:12 -0300)]
board/freescale: Remove invalid fsl email addresses
These fsl email addresses are no longer valid and they do not have a
correspondent nxp.com entry.
Remove all invalid fsl email addresses and mark the boards as orphan.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Wed, 2 May 2018 23:12:06 +0000 (20:12 -0300)]
p1022ds: Change Timur's email address
timur@freescale.com is not a valid email for quite some time, so change
it to Timur's updated email.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Timur Tabi <timur@tabi.org>
Lukasz Majewski [Wed, 2 May 2018 14:10:56 +0000 (16:10 +0200)]
bootcount: display5: config: Enable boot count feature in the display5 board
The boot count is enabled in both SPL and proper u-boot.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Lukasz Majewski [Wed, 2 May 2018 14:10:55 +0000 (16:10 +0200)]
bootcount: display5: spl: Extend DISPLAY5 board SPL to support bootcount checking
This patch is necessary for providing basic bootcount checking in the case
of using "falcon" boot mode in that board.
It forces u-boot proper boot, when we exceed the number of errors.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Lukasz Majewski [Wed, 2 May 2018 14:10:54 +0000 (16:10 +0200)]
bootcount: spl: Extend SPL to support bootcount incrementation
This patch adds support for incrementation of the bootcount in SPL.
Such feature is necessary when we do want to use this feature with
'falcon' boot mode (which loads OS directly in SPL).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lukasz Majewski [Wed, 2 May 2018 14:10:53 +0000 (16:10 +0200)]
bootcount: Rewrite autoboot to use wrapper functions from bootcount.h
The code has been refactored to use common wrappers from bootcount.h
header.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
Lukasz Majewski [Wed, 2 May 2018 14:10:52 +0000 (16:10 +0200)]
bootcount: Add function wrappers to handle bootcount increment and error checking
Those two functions can be used to provide easy bootcount management.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Lukasz Majewski [Wed, 2 May 2018 14:10:51 +0000 (16:10 +0200)]
bootcount: Add include guards into bootcount.h file
This patch adds missing include guards for bootcount.h file.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
Lukasz Majewski [Wed, 2 May 2018 14:10:50 +0000 (16:10 +0200)]
bootcount: spl: Enable bootcount support in SPL
New, SPL related config option - CONFIG_SPL_BOOTCOUNT_LIMIT has been
added to allow drivers/bootcount code re-usage in SPL.
This code is necessary to use and setup bootcount in SPL in the case of
falcon boot mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Alex Kiernan <alex.kiernan@gmail.com>
Tom Rini [Thu, 10 May 2018 11:17:14 +0000 (07:17 -0400)]
Merge git://git.denx.de/u-boot-ubi
Tom Rini [Wed, 9 May 2018 16:58:06 +0000 (12:58 -0400)]
Merge git://git.denx.de/u-boot-sunxi
Yogesh Gaur [Wed, 9 May 2018 05:22:17 +0000 (10:52 +0530)]
driver: net: fsl-mc: updated copyright info
Updated copyright info for the issues reported after running
check-legal test.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Jagdish Gediya [Tue, 1 May 2018 19:50:57 +0000 (01:20 +0530)]
mtd: nand: fsl_ifc: Fix nand waitfunc return value
As per the IFC hardware manual, Most significant byte in nand_fsr
register is the outcome of NAND READ STATUS command.
So status value need to be shifted as per the nand framework
requirement.
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Wed, 25 Apr 2018 06:25:42 +0000 (14:25 +0800)]
armv8/fsl-lsch2: make the workaround for PIN MUX erratum
A010539 robust
Mask HRESET_B after cleared the the RCW_SRC, because in the workaround
we override the RCW_SRC and if HRESET_B is issued after the override
then SoC cannot find valid RCW as the RCW_SRC was overwritten and
result in hang. So we need to mask HRESET_B in case user asserts it,
and the PORESET_B should be asserted which leads to resampling of
cfg_rcw_src pins and loading of correct RCW_SRC.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Wed, 25 Apr 2018 08:28:44 +0000 (16:28 +0800)]
armv8/fsl-lsch2: correct QMAN clock
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Mon, 23 Apr 2018 21:53:28 +0000 (03:23 +0530)]
armv8: sec_firmware: Add support for multiple loadables
Enable support for multiple loadable images in SEC firmware FIT image.
Also add example "sec_firmware_ppa.its" file.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Takuma Ueba [Mon, 23 Apr 2018 04:27:33 +0000 (13:27 +0900)]
powerpc: mpc85xx: Improve Work-around for Erratum
A005125
Work-around for Erratum
A005125 must be applied to all cores.
Signed-off-by: Yoshihisa Morizumi <yoshi.morizumi@jp.fujitsu.com>
Signed-off-by: Takuma Ueba <ueba.takuma@jp.fujitsu.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Wed, 18 Apr 2018 05:07:24 +0000 (10:37 +0530)]
armv8: ls1088: Update 1900MT/s DDR timing to bring consistency
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Fri, 13 Apr 2018 06:58:45 +0000 (12:28 +0530)]
armv8: ls1088aqds: Enable mdio commands on u-boot prompt
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ruchika Gupta [Thu, 12 Apr 2018 10:54:35 +0000 (16:24 +0530)]
armv8: sec_firmware: Remove JR3 from device tree node in all cases
JR3 was getting removed from device tree only if random number
generation was successful. However, if SEC firmware is present,
JR3 should be removed from device tree node irrespective of the
random seed generation as SEC firmware reserves it for it's use.
Not removing it in case of random number generation failure causes
the kernel to crash.
Random number generation was being called twice. This is not
required. If SEC firmware is running, SIP call can be made to the SEC
firmware to get the random number. This call itself would return
failure if function is not supported. Duplicate calling of random
number generation function has been removed.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Mon, 26 Mar 2018 09:32:41 +0000 (15:02 +0530)]
armv8: ls1088a: Move CONFIG_BOOTARGS and CONFIG_CMD_GREPENV to defconfig
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sriram Dash [Mon, 26 Mar 2018 08:52:43 +0000 (14:22 +0530)]
armv8: layerscape: Avoid code duplication for TZASC Instantiation
TZASC controller configurations are similar. Put them in a macro and
avoid code duplication.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Jagdish Gediya [Fri, 23 Mar 2018 21:25:51 +0000 (02:55 +0530)]
mtd: nand: fsl_ifc: Fix eccstat array overflow for IFC ver >= 2.0.0
Number of ECC status registers i.e. (ECCSTATx) has been increased in
IFC version 2.0.0 due to increase in SRAM size. This is causing
eccstat array to over flow.
So, replace eccstat array with u32 variable to make it fail-safe and
independent of number of ECC status registers or SRAM size.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Rajat Srivastava [Thu, 22 Mar 2018 08:00:55 +0000 (13:30 +0530)]
spi: fsl_qspi: Introduce is_controller_busy function
Some SoCs have different endianness of QSPI IP if compared
to endianness of core. The function is_controller_busy()
checks if the QSPI controller is busy or not, considering
the endianness of the QSPI IP.
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Patrice Chotard [Fri, 27 Apr 2018 13:51:23 +0000 (15:51 +0200)]
ubifs: avoid assert failed in ubifs.c
This patch solves assert failed displayed in the console during a boot.
The root cause is that the ubifs_inode is not already allocated when
ubifs_printdir and ubifs_finddir functions are called.
Trace showing the issue:
feed 'boot.scr.uimg', ino 94, new f_pos 0x17b40ece
dent->ch.sqnum '7132', creat_sqnum
3886945402880
UBIFS assert failed in ubifs_finddir at 436
INODE ALLOCATION: creat_sqnum '7129'
Found U-Boot script /boot.scr.uimg
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tom Rini [Tue, 1 May 2018 16:32:37 +0000 (12:32 -0400)]
bootm.c: Correct the flush_len used in bootm_load_os()
In do_bootm_states when doing BOOTM_STATE_LOADOS we use load_end
uninitialized and Coverity notes this now. This however leads down
another interesting path. We pass this pointer to bootm_load_os and
that in turn uses this uninitialized value immediately to calculate the
flush length, and is wrong. We do not know what load_end will be until
after bootm_decomp_image is called, so we must only set flush_len after
that. All of this also makes it clear that the only reason we pass a
pointer for load_end to bootm_load_os is so that we can call lmb_reserve
on success. Rather than initialize load_end to 0 in do_bootm_states we
can just call lmb_reserve ourself.
Reported-by: Coverity (CID: 175572)
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Clément Péron [Mon, 30 Apr 2018 09:06:40 +0000 (11:06 +0200)]
image: fit: Show signatures and hashes for configurations
The signature/hash information are displayed for images but nor for
configurations.
Add subnodes printing in fit_conf_print() like it's done in fit_image_print()
Signed-off-by: Clément Péron <peron.clem@gmail.com>
[trini: Add guards around fit_conf_print to avoid warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
Grygorii Strashko [Sat, 28 Apr 2018 00:58:49 +0000 (19:58 -0500)]
arm: bitops: fix find_next_zero_bit() for case size < 32
find_next_zero_bit() incorrectly handles cases when:
- total bitmap size < 32
- rest of bits to process
static inline int find_next_zero_bit(void *addr, int size, int offset)
{
unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
[1]
goto found_first;
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size & ~31UL) {
tmp = *(p++);
if (~tmp)
goto found_middle;
result += 32;
size -= 32;
}
[2]
if (!size)
return result;
tmp = *p;
found_first:
[3] tmp |= ~0UL >> size;
^^^ algo can reach above line from from points:
[1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1
[2] size < 32 - rest of bits to process
in both cases bits to search are tmp[size-1..0], but line [3] will simply
set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail.
example: bitmap size = 16, offset = 0, bitmap is empty.
code will go through the point [2], tmp = 0x0
after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16.
found_middle:
return result + ffz(tmp);
}
Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3].
Fixes:
81e9fe5a2988 ("arm: implement find_next_zero_bit function")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Neil Armstrong [Fri, 27 Apr 2018 13:17:57 +0000 (15:17 +0200)]
cmd: add ADC cli commands
Add an 'adc' cli command to get information from adc devices and to read
"single shot" data.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Mario Six [Fri, 27 Apr 2018 12:53:37 +0000 (14:53 +0200)]
pci: Don't use pci_indirect when DM is active
Declaration of indirect PCI bridges is not compatible with DM: Both
define PCI operations, but in different ways. Hence, don't use indirect
bridges if DM is active.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mario Six [Fri, 27 Apr 2018 12:53:33 +0000 (14:53 +0200)]
gdsys: drivers: Add gdsys_rxaui_ctrl driver
Add a driver for RXAUI control on IHS FPGAs.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mario Six [Fri, 27 Apr 2018 12:53:15 +0000 (14:53 +0200)]
clk: Add ICS8N3QV01 driver
Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Fri, 27 Apr 2018 12:52:10 +0000 (14:52 +0200)]
ihs_mdio: Make DM-compatible
Make the ihs_mdio driver DM-compatible, while retaining the old
functionality for not-yet-converted boards.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Fri, 27 Apr 2018 12:52:09 +0000 (14:52 +0200)]
ihs_mdio: Encapsulate register access
To prepare for DM conversion, encapsulate all register accesses in
function calls.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Ramon Fried [Fri, 20 Apr 2018 19:39:50 +0000 (22:39 +0300)]
db410c: set clk node to be probed before relocation
The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that the msm-serial driver can actually
use the clock node.
Signed-off-by: Ramon Fried <ramon.fried@linaro.org>
Patrice Chotard [Fri, 20 Apr 2018 07:53:55 +0000 (09:53 +0200)]
ARM: dts: sti: Add stih410-b2260-u-boot.dtsi
STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs.
As currently no U-boot driver is available for the USB3 PHY and to avoid
issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY
using stih410-b2260-u-boot.dtsi file.
Fixes:
2fd4242cc50e ("ubs: xhci-dwc3: Enable USB3 PHY when available")
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Sam Protsenko [Thu, 19 Apr 2018 20:57:30 +0000 (23:57 +0300)]
arm: ti: boot: Extract PARTS_DEFAULT to boot.h
Eliminate code duplication: the same PARTS_DEFAULT was defined in
am57xx_evm.h and in dra7xx_evm.h. Extract it to environment/boot.h and
use in all OMAP5-based boards.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Marek Vasut [Sun, 15 Apr 2018 13:21:09 +0000 (15:21 +0200)]
spl: socfpga: Generate Arria10 SFP header V1
Generate SoCFPGA boot header version 1 instead of version 0 for Arria10.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Marek Vasut [Sun, 15 Apr 2018 11:15:33 +0000 (13:15 +0200)]
tools: socfpga: Add SFP image V1 support
Add support for the SoCFPGA header v1 , which is used on Arria 10.
Thus far the mkimage-socfpga image only supported header format v0
used on Cyclone V and Arria V, but is not supported on Arria 10.
The layout of the v0 and v1 header is similar, yet there are a few
differences, see the patch body for details.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Marek Vasut [Sun, 15 Apr 2018 11:38:49 +0000 (13:38 +0200)]
tools: socfpga: Stop using global struct socfpga_image
The structure is passed around correctly, create local instances
where necessary and zap the global struct socfpga_image instance.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Marek Vasut [Sun, 15 Apr 2018 11:15:33 +0000 (13:15 +0200)]
image: socfpga: Add SFP image version 1 definition
Add support for the SoCFPGA header v1, which is used on Arria 10.
The layout of the v0 and v1 header is similar, yet there are a few
differences which make it incompatible with previous v0 header, so
add a new entry.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Marek Vasut [Sun, 15 Apr 2018 11:15:33 +0000 (13:15 +0200)]
ARM: socfpga: Add boot trampoline for Arria10
The Arria10 uses slightly different boot image header than the Gen5 SoCs,
in particular the header itself contains an offset from the start of the
header to which the Arria10 jumps. This offset must not be negative, yet
the header is placed at offset 0x40 of the bootable binary. Therefore, to
jump into U-Boot, add a trampoline just past the Arria10 boot header and
point to this trampoline at fixed offset from the header generated using
the mkimage -T socfpgaimage_v1 . Note that it is not needed to jump back
to offset 0x0 of the image, it is possible to jump directly at the reset
label and save processing two instructions.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Tom Rini [Tue, 8 May 2018 17:47:39 +0000 (13:47 -0400)]
Merge git://git.denx.de/u-boot-mmc
Tom Rini [Tue, 8 May 2018 17:47:26 +0000 (13:47 -0400)]
Merge git://git.denx.de/u-boot-uniphier
Tom Rini [Tue, 8 May 2018 12:52:17 +0000 (08:52 -0400)]
lib/Kconfig: Mark OF_LIBFDT_OVERLAY as depending on OF_LIBFDT
The overlay code is only useful when OF_LIBFDT is set, so mark it as
depending on that first.
Signed-off-by: Tom Rini <trini@konsulko.com>
Neil Armstrong [Mon, 23 Apr 2018 14:19:23 +0000 (16:19 +0200)]
adc: add Amlogic Meson SAR ADC driver
This patch adds the driver for the Amlogic Meson Successive Approximation
Register (SAR) A/D Converter based on the Linux IIO driver thanks to the
great work of Martin Blumenstingl.
The driver has been adapted to U-Boot and the ADC UClass.
This patch depends on the regmap "regmap: add regmap_update_bits() helper"
patch and has been tested using the newly introducted "adc" CLI command
in the "cmd: add ADC cli commands" patch.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 27 Apr 2018 09:56:15 +0000 (11:56 +0200)]
test: regmap: add read/modify/write test
Add calls to regmap_read/modify_bits/write even if the proper memory
read/write calls are not executed in sandbox.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Neil Armstrong [Fri, 27 Apr 2018 09:56:14 +0000 (11:56 +0200)]
regmap: add regmap_update_bits() helper
Add the regmap_update_bits() to simply the read/modify/write of registers
in a single command. The function is taken from Linux regmap
implementation.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Thu, 26 Apr 2018 15:00:49 +0000 (17:00 +0200)]
ARM: dts: stm32mp157: Add vrefbuf DT node
Add vrefbuf device tree node. This allows to get
a voltage reference for ADCs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Fabrice Gasnier [Thu, 26 Apr 2018 15:00:48 +0000 (17:00 +0200)]
configs: stm32mp15: Enable STM32_VREFBUF flag
Enable vrefbuf on stm32mp15, to be used by ADC.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Fabrice Gasnier [Thu, 26 Apr 2018 15:00:47 +0000 (17:00 +0200)]
clk: stm32mp1: Add VREF clock gating
Add VREF clock gating, that may be used by STM32 VREFBUF regulator.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Fabrice Gasnier [Thu, 26 Apr 2018 15:00:46 +0000 (17:00 +0200)]
power: regulator: Add support for stm32-vrefbuf
Add regulator driver for STM32 voltage reference buffer which can be
used as voltage reference for ADCs, DACs and external components through
dedicated VREF+ pin.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Thu, 26 Apr 2018 15:13:12 +0000 (17:13 +0200)]
configs: stm32mp15_basic: Set regulator relative flags
Enable DM_REGULATOR_STPMU1 flag to activate regulator
driver for STM32MP15 SoC and CMD_REGULATOR flag to be
able to set/get regulator state int U-boot command line.
Disable PMIC_CHILDREN as this flag is not needed in SPL
for STM32MP1.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Thu, 26 Apr 2018 15:13:11 +0000 (17:13 +0200)]
ARM: dts: stm32mp157c-ed1: Add regulator node
Add regulator nodes needed by stpmu1 regulator driver
Add vmmc-supply and vqmmc-supply regulator property for
sdmmc1 and sdmmc2.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Thu, 26 Apr 2018 15:13:10 +0000 (17:13 +0200)]
power: pmic: stpmu1: Add regulator bindings
Add regulator bindings to get access to regulator managed
by drivers/power/regulator/stpmu1.c regulator driver.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Christophe Kerello [Thu, 26 Apr 2018 15:13:09 +0000 (17:13 +0200)]
power: regulator: stpmu1: Introduce stpmu1 driver
Enable support for the regulator functions of the STPMU1X PMIC. The
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Thu, 26 Apr 2018 14:45:19 +0000 (16:45 +0200)]
ARM: dts: stm32mp157: Add SoC pwr regulator entry
Add SoC power regulator entry for reg11, reg18 and usb33
regulator.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 26 Apr 2018 14:45:18 +0000 (16:45 +0200)]
stm32mp: regulator: add SoC pwr regulator support
This driver binds and manages the following regulator of
SoC's PWR block :
- reg11
- reg18
- usb33
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>