oweals/u-boot.git
8 years agobzlib: Try another way to fix an unused variable
Simon Glass [Sat, 30 Jan 2016 22:45:18 +0000 (15:45 -0700)]
bzlib: Try another way to fix an unused variable

Use __maybe_unused which should avoid the Coverity error.

Reported-by: Coverity (CID: 134900)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agovideo: test: Adjust order of file closure
Simon Glass [Sat, 30 Jan 2016 22:45:17 +0000 (15:45 -0700)]
video: test: Adjust order of file closure

Close the file earlier to hopefully fix a Coverity error.

Reported-by: Coverity (CID: 134901)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agovideo: Use 'int' for loop variables instead of short
Simon Glass [Sat, 30 Jan 2016 22:45:16 +0000 (15:45 -0700)]
video: Use 'int' for loop variables instead of short

Using short doesn't save anything and is confusing when the width and height
variables are ulong.

This may fix Coverity CID134902 but I doubt it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agocmd: Fix control bmp_display()
Simon Glass [Sat, 30 Jan 2016 22:45:15 +0000 (15:45 -0700)]
cmd: Fix control bmp_display()

All paths should share the same return.

Reported-by: Coverity (CID:134903)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agomicroblaze: Correct build error in eth-uclass.c
Simon Glass [Sat, 30 Jan 2016 22:45:14 +0000 (15:45 -0700)]
microblaze: Correct build error in eth-uclass.c

This fixes the following error when building microblaze-generic:

net/eth-uclass.c: In function 'eth_post_probe':
net/eth-uclass.c:466:18: error: 'gd' undeclared (first use in this function)
    ops->start += gd->reloc_off;

Fixes: db9391e1 ("net: Move driver-model code into its own file")

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoUse correct spelling of "U-Boot"
Bin Meng [Sat, 6 Feb 2016 03:30:11 +0000 (19:30 -0800)]
Use correct spelling of "U-Boot"

Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Thu, 4 Feb 2016 11:56:23 +0000 (06:56 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Thu, 4 Feb 2016 11:56:20 +0000 (06:56 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

8 years agoRevert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"
Dinh Nguyen [Tue, 19 Jan 2016 15:16:21 +0000 (09:16 -0600)]
Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"

Apparently, the logic for the FPGA global bit is not universal between Gen5
and Gen10 devices is not the same. Disabling this bit, while applicable to
Gen10 devices, will break FPGA programming on Gen5 devices.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
8 years agousb: gadget: dwc2_udc_otg: modified the check condition for max packet size of ep_in...
Frank Wang [Wed, 27 Jan 2016 20:39:40 +0000 (12:39 -0800)]
usb: gadget: dwc2_udc_otg: modified the check condition for max packet size of ep_in in high speed

In current high speed fastboot, fs_ep_in.wMaxPacketSize is configured 64 bytes
as default, as a result, it failed to match the size at initialization stage in
usb controller.
Actually, hardware can support less than or equal to 512 bytes in high speed mode,
so I changed the condition from  '!=' to '>' to fix this issue.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Tested-by: Steve Rae <srae@broadcom.com>
8 years agoimx: mx6: implement board_mmc_get_env_dev
Peng Fan [Thu, 28 Jan 2016 08:51:27 +0000 (16:51 +0800)]
imx: mx6: implement board_mmc_get_env_dev

Implement board_mmc_get_env_dev for the boards.

Following is examples:
SD1/SD2/SD3: return devno;
SD2/SD3: return devno - 1;
SD2/SD4: if (devno == 2), return dev - 2; return dev - 1;

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
8 years agoimx: mx6: implement mmc_get_env_dev
Peng Fan [Thu, 28 Jan 2016 08:51:26 +0000 (16:51 +0800)]
imx: mx6: implement mmc_get_env_dev

Implement mmc_get_env_dev, devno can be got from smbr1 of SRC.
Introduce a weak function board_mmc_get_env_dev, different
boards can implement it according to different sdhc controllers
that used by the board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
8 years agoimx: mx7dsabresd: move mmc_get_env_devno to soc code
Peng Fan [Thu, 28 Jan 2016 08:51:25 +0000 (16:51 +0800)]
imx: mx7dsabresd: move mmc_get_env_devno to soc code

Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
8 years agodm: vybrid_gpio: Drop legacy code
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:53 +0000 (10:31 +0530)]
dm: vybrid_gpio: Drop legacy code

All boards using this driver are with device tree support,
hence drop the legacy code in driver to have a pure DT solution.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: lpuart: Drop the legacy code
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:52 +0000 (10:31 +0530)]
dm: lpuart: Drop the legacy code

All boards using this driver are with device tree support,
hence drop the legacy code in driver to have a pure DT solution.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoarm: vybrid: Drop enabling GPIO, SPI and UART in legacy mode
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:51 +0000 (10:31 +0530)]
arm: vybrid: Drop enabling GPIO, SPI and UART in legacy mode

Remove the legacy way of enabling GPIO, SPI and UART on Vybrid
based boards since these driver's now only supports DT mode.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoarm: vybrid: Update defconfig's
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:50 +0000 (10:31 +0530)]
arm: vybrid: Update defconfig's

Let's go with pure DT solution for board's
based on NXP/Freescale Vybrid platform.

- Merge the DT defconfig with non-DT defconfig for Toradex
  Colibri VF50/VF61 and drop the non-DT defconfig.
- Update the legacy defconfigs for NXP/Freescale VF610 Tower
  Board with DT.
- Update the legacy defconfigs for Phytec phyCORE-vybrid
  Board with DT.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoarm: pcm052: Add device tree file's
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:49 +0000 (10:31 +0530)]
arm: pcm052: Add device tree file's

- Add device tree files for Phytec phyCORE-Vybrid Board.
- Enable lpuart support for Phytec phyCORE-Vybrid Board.
- Use UART1 for stdout.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoarm: vf610-twr: Add device tree file's
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:48 +0000 (10:31 +0530)]
arm: vf610-twr: Add device tree file's

- Add device tree files for NXP/Freescale VF610 Tower Board.
- Enable lpuart support on NXP/Freescale VF610 Tower Board.
- Use UART1 as stdout.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoarm: colibri-vf: Enable serial support
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:47 +0000 (10:31 +0530)]
arm: colibri-vf: Enable serial support

- Enable lpuart support on Toradex Colibri VF50/VF61
- Use UART0 for stdout.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoarm: vybrid: Update the license string
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:46 +0000 (10:31 +0530)]
arm: vybrid: Update the license string

Since SPDX license is already there, drop the full one.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoarm: vybrid: Enable lpuart support
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:45 +0000 (10:31 +0530)]
arm: vybrid: Enable lpuart support

Add device tree node's for lpuart on Vybrid platform

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoimx: mx6sxsabresd: Add MCIMX28LCD display support
Ye Li [Tue, 26 Jan 2016 14:09:40 +0000 (22:09 +0800)]
imx: mx6sxsabresd: Add MCIMX28LCD display support

The i.MX6SX SABRESD board supports MCIMX28LCD (800x480x24) at LCDIF1
port, enable this display feature by adding relevant BSP codes
and configurations.

Signed-off-by: Ye Li <ye.li@nxp.com>
8 years agoimx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation
Ye Li [Tue, 26 Jan 2016 14:01:58 +0000 (22:01 +0800)]
imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation

The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
8 years agoimx: mx6sx: Fix issue in LCDIF clock enablement
Ye Li [Tue, 26 Jan 2016 14:01:57 +0000 (22:01 +0800)]
imx: mx6sx: Fix issue in LCDIF clock enablement

Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always
enter the -EINVAL return.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
8 years agomx6slevk: Remove CONFIG_ETHPRIME option
Fabio Estevam [Mon, 1 Feb 2016 16:24:56 +0000 (14:24 -0200)]
mx6slevk: Remove CONFIG_ETHPRIME option

As mx6slevk has only one Ethernet port, we don't need
to declare CONFIG_ETHPRIME, so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agoimx: MX6DQ{P}/DL:SABRESD Fix bmode eMMC failure
Ye Li [Sat, 30 Jan 2016 03:53:42 +0000 (11:53 +0800)]
imx: MX6DQ{P}/DL:SABRESD Fix bmode eMMC failure

The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card.
Fixed the value to correct one.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agotqma6_wru4: Fix the reset delay for the the LAN8720 PHY
Fabio Estevam [Mon, 1 Feb 2016 13:19:59 +0000 (11:19 -0200)]
tqma6_wru4: Fix the reset delay for the the LAN8720 PHY

According to the LAN8720 datasheet tpurstd (time that reset line should
stay asserted) is 25ms.

So do as suggested by the LAN8720 datasheet.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agomx6slevk: Fix the reset delay for the the LAN8720 PHY
Fabio Estevam [Mon, 1 Feb 2016 13:15:10 +0000 (11:15 -0200)]
mx6slevk: Fix the reset delay for the the LAN8720 PHY

Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.

This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.

According to the LAN8720 datasheet tpurstd (time that reset line should
stay asserted) is 25ms.

So do as suggested in order to have Ethernet working again.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agoimx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board
Ye Li [Mon, 1 Feb 2016 02:41:32 +0000 (10:41 +0800)]
imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board

Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.

Signed-off-by: Ye Li <ye.li@nxp.com>
8 years agomx6: soc: Add ENET2 mac address support
Ye Li [Mon, 1 Feb 2016 02:41:31 +0000 (10:41 +0800)]
mx6: soc: Add ENET2 mac address support

The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.

Signed-off-by: Ye Li <ye.li@nxp.com>
8 years agotools: mxsboot: Use more portable cpu_to_le32()
Bin Meng [Mon, 25 Jan 2016 03:38:32 +0000 (19:38 -0800)]
tools: mxsboot: Use more portable cpu_to_le32()

Currently when building mxsboot on certain machines it reports:

  HOSTCC  tools/mxsboot
  tools/mxsboot.c: In function 'mx28_create_sd_image':
  tools/mxsboot.c:560: warning: implicit declaration of function 'htole32'
  /tmp/cchLIV6q.o: In function 'main':
  mxsboot.c:(.text+0x6d8): undefined reference to 'htole32'
  mxsboot.c:(.text+0x6e7): undefined reference to 'htole32'
  mxsboot.c:(.text+0x6f6): undefined reference to 'htole32'
  mxsboot.c:(.text+0x705): undefined reference to 'htole32'
  mxsboot.c:(.text+0x711): undefined reference to 'htole32'
  /tmp/cchLIV6q.o:mxsboot.c:(.text+0x71d): more undefined references to
  'htole32' follow
  collect2: ld returned 1 exit status
  make[1]: *** [tools/mxsboot] Error 1
  make: *** [tools] Error 2

The solution is to use cpu_to_le32() instead which is more portable,
just like other U-Boot tools [1] do.

[1] http://lists.denx.de/pipermail/u-boot/2014-October/192919.html

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
8 years agowandboard: fix variable name so PXE boot works
Peter Robinson [Wed, 20 Jan 2016 10:00:16 +0000 (10:00 +0000)]
wandboard: fix variable name so PXE boot works

All boards that support PXE booting use the pxefile_addr_r variable. Standardise
wandboard with this variable as pxe_addr_r isn't used anywhere else so it's a
typo.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
8 years agoarm: imx6: Enable DDR calibration on Novena
Marek Vasut [Wed, 16 Dec 2015 14:40:07 +0000 (15:40 +0100)]
arm: imx6: Enable DDR calibration on Novena

Enable the DDR calibration functionality on Novena to deal with the
memory SoDIMM on this board. Moreover, tweak the initial DDR DRAM
parameters so the calibration works properly.

Signed-off-by: Marek Vasut <marex@denx.de>
8 years agoarm: imx6: Add DDR3 calibration code for MX6 Q/D/DL
Marek Vasut [Wed, 16 Dec 2015 14:40:06 +0000 (15:40 +0100)]
arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
8 years agoPrepare v2016.03-rc1 v2016.03-rc1
Tom Rini [Tue, 2 Feb 2016 16:29:50 +0000 (11:29 -0500)]
Prepare v2016.03-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-atmel
Tom Rini [Tue, 2 Feb 2016 12:24:52 +0000 (07:24 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 2 Feb 2016 11:51:05 +0000 (06:51 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agoboard: atmel: sama5d2_xplained: add SPL support
Wenyou Yang [Mon, 1 Feb 2016 10:18:21 +0000 (18:18 +0800)]
board: atmel: sama5d2_xplained: add SPL support

The sama5d2 Xplained SPL supports the boot medias: spi flash
and SD Card.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: at91/spl: mpddrc: use IP version to check configuration
Wenyou Yang [Mon, 1 Feb 2016 10:12:17 +0000 (18:12 +0800)]
arm: at91/spl: mpddrc: use IP version to check configuration

To remove the unnecessary #ifdef-endif, use the mpddrc IP version
to check whether or not the interleaved decoding type is supported.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
Wenyou Yang [Mon, 1 Feb 2016 10:12:16 +0000 (18:12 +0800)]
arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization

The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.

Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoarm: at91/spl: mpddrc: add struct atmel_mpddrc_config
Wenyou Yang [Mon, 1 Feb 2016 10:12:15 +0000 (18:12 +0800)]
arm: at91/spl: mpddrc: add struct atmel_mpddrc_config

Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoatmel_nand: Add 32 bit ecc support for sama5d2 chip
Josh Wu [Tue, 24 Nov 2015 08:34:01 +0000 (16:34 +0800)]
atmel_nand: Add 32 bit ecc support for sama5d2 chip

Also if minimum ecc requirment is bigger then what we support, then just
use our maxium pmecc support.
But it is not safe, so we'll output a warning about this.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoatmel_nand_ecc: update pmecc registers according to sama5d2 chip
Josh Wu [Tue, 24 Nov 2015 08:34:00 +0000 (16:34 +0800)]
atmel_nand_ecc: update pmecc registers according to sama5d2 chip

1. add the pmecc register mapping for sama5d2.
2. add the pmecc error location register mapping for sama5d2.
3. add some new field that is different from old ip.
4. add sama5d2 pmecc ip version number.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
8 years agoMakefile: Drop unnecessary -dtb suffixes
Simon Glass [Mon, 1 Feb 2016 01:10:55 +0000 (18:10 -0700)]
Makefile: Drop unnecessary -dtb suffixes

When OF_CONTROL is enabled, u-boot-dtb.* files are the same as u-boot.*
files. So we can use the latter for simplicity.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agoMakefile: Make u-boot.img the same as u-boot-dtb.img
Simon Glass [Mon, 1 Feb 2016 01:10:54 +0000 (18:10 -0700)]
Makefile: Make u-boot.img the same as u-boot-dtb.img

Create u-boot.img even when OF_CONTROL is enabled, so that this file can be
used in both cases.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agosocfpga: Simplify Makefile filenames
Simon Glass [Mon, 1 Feb 2016 01:10:53 +0000 (18:10 -0700)]
socfpga: Simplify Makefile filenames

We don't need the -dtb suffix anymore, so drop it.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agotegra: Always build a boot image with the same filename
Simon Glass [Mon, 1 Feb 2016 01:10:52 +0000 (18:10 -0700)]
tegra: Always build a boot image with the same filename

Adjust the Makefile to build u-boot-tegra.bin which contains a device tree
if OF_SEPARATE is enabled, and does not if not. This mirrors U-Boot's new
approach of using u-boot.bin to handle both cases.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agofdt: Build an SPL binary without device tree
Simon Glass [Mon, 1 Feb 2016 01:10:51 +0000 (18:10 -0700)]
fdt: Build an SPL binary without device tree

At present u-boot-spl.bin holds the plain SPL binary without the device
tree. This is somewhat annoying since you need either u-boot-spl.bin or
u-boot-spl-dtb.bin depending on whether device tree is used.

Adjust the build such that u-boot-spl.bin includes a device tree
(if enabled), and the plain binary is in u-boot-spl-nodtb.bin. For now
u-boot-spl-dtb.bin remains the same.

Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agofdt: Build a U-Boot binary without device tree
Simon Glass [Mon, 1 Feb 2016 01:10:50 +0000 (18:10 -0700)]
fdt: Build a U-Boot binary without device tree

At present u-boot.bin holds the plain U-Boot binary without the device tree.
This is somewhat annoying since you need either u-boot.bin or u-boot-dtb.bin
depending on whether device tree is used.

Adjust the build such that u-boot.bin includes a device tree (if enabled),
and the plain binary is in u-boot-nodtb.bin. For now u-boot-dtb.bin remains
the same.

This should be acceptable since:

- without OF_CONTROL, u-boot.bin still does not include a device tree
- with OF_CONTROL, u-boot-dtb.bin does not change

The main impact is build systems which are set up to use u-boot.bin as
the output file and then add a device tree. These will have to change to use
u-boot-nodtb.bin instead.

Adjust tegra rules so it continues to produce the correct files.

Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agotegra: Clarify generation of -nodtb file with OF_CONTROL
Simon Glass [Mon, 1 Feb 2016 01:10:49 +0000 (18:10 -0700)]
tegra: Clarify generation of -nodtb file with OF_CONTROL

Fix the ALL-y logic in the Makefile so that is clear that we always want
the -nodtb file.

Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agomailmap: fix Ricardo's entry
Masahiro Yamada [Fri, 29 Jan 2016 02:42:53 +0000 (11:42 +0900)]
mailmap: fix Ricardo's entry

Commit df48b23428e9 (".mailmap: Add all the mail alias for Ricardo
Ribalda") assigned two different proper names for the email address
"ricardo.ribalda@uam.es".  This is a completely wrong usage as the
mailmap feature exists for coalescing together commits by the same
person whose name is sometimes spelled differently.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agommc: add missing prototype for mmc_get_env_dev
Clemens Gruber [Tue, 26 Jan 2016 15:20:38 +0000 (16:20 +0100)]
mmc: add missing prototype for mmc_get_env_dev

This is a follow-up patch to e92029c0f4 and adds a prototype for
the weak mmc_get_env_dev function.

Cc: Tom Rini <trini@konsulko.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
8 years agomalloc: work around some memalign fragmentation issues
Stephen Warren [Mon, 25 Jan 2016 21:03:42 +0000 (14:03 -0700)]
malloc: work around some memalign fragmentation issues

Use of memalign can trigger fragmentation issues such as:

// Internally, this needs to find a free block quite bit larger than s.
// Once the free region is found, any unaligned "padding" immediately
// before and after the block is marked free, so that the allocation
// takes only s bytes (plus malloc header overhead).
p = memalign(a, s);
// If there's little fragmentation so far, this allocation is likely
// located immediately after p.
p2 = malloc(x);
free(p);
// In theory, this should return the same value for p. However, the hole
// left by the free() call is only s in size (plus malloc header overhead)
// whereas memalign searches for a larger block in order to guarantee it
// can adjust the returned pointer to the alignment requirements. Hence,
// the pointer returned, if any, won't be p. If there's little or no space
// left after p2, this allocation will fail.
p = memalign(a, s);

In practice, this issue occurs when running the "dfu" command repeatedly
on NVIDIA Tegra boards, since DFU allocates a large 32M data buffer, and
then initializes the USB controller. If this is the first time USB has
been used in the U-Boot session, this causes a probe of the USB driver,
which causes various allocations, including a strdup() of a GPIO name
when requesting the VBUS GPIO. When DFU is torn down, the USB driver
is left probed, and hence its memory is left allocated. If "dfu" is
executed again, allocation of the 32M data buffer fails as described
above.

In practice, there is a memory hole exactly large enough to hold the 32M
data buffer than DFU needs. However, memalign() can't know that in a
general way. Given that, it's particularly annoying that the allocation
fails!

The issue is that memalign() tries to allocate something larger to
guarantee the ability to align the returned pointer. This patch modifies
memalign() so that if the "general case" over-sized allocation fails,
another allocation is attempted, of the exact size the user desired. If
that allocation just happens to be aligned in the way the user wants,
(and in the case described above, it will be, since the free memory
region is located where a previous identical allocation was located),
the pointer can be returned.

This patch is somewhat related to 806bd245b1ab "dfu: don't keep
freeing/reallocating". That patch worked around the issue by removing
repeated free/memalign within a single execution of "dfu". However,
the same technique can't be applied across multiple invocations, since
there's no reason to keep the DFU buffer allocated while DFU isn't
running. This patch addresses the root-cause a bit more directly.

This problem highlights some of the disadvantages of dynamic allocation
and deferred probing of devices.

This patch isn't checkpatch-clean, since it conforms to the existing
coding style in dlmalloc.c, which is different to the rest of U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
8 years ago.travis.yml: rework according to new travis-ci infra
Roger Meier [Mon, 25 Jan 2016 19:22:41 +0000 (20:22 +0100)]
.travis.yml: rework according to new travis-ci infra

- install using addons.apt
- remove MAKEALL
- split mpc85xx boards
- remove TEST_CONFIG_CMD, just info
- fetch mips toolchain via buildman
- remove --list-error-boards param
- conditional script
- use TOOLCHAIN instead of INSTALL_TOOLCHAIN
- add aarch64
- enable notifications via email

Signed-off-by: Roger Meier <r.meier@siemens.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Andreas Färber <afaerber@suse.de>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
8 years agoarm8: ls2080: Move the core errata defines out of board specific file
Ashish kumar [Fri, 29 Jan 2016 11:10:08 +0000 (16:40 +0530)]
arm8: ls2080: Move the core errata defines out of board specific file

Valid for core A57

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Mon, 1 Feb 2016 21:58:46 +0000 (16:58 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

8 years agoarmv8: ls2080a: Implement workaround for core errata 829520, 833471
Ashish kumar [Wed, 27 Jan 2016 12:39:32 +0000 (18:09 +0530)]
armv8: ls2080a: Implement workaround for core errata 829520, 833471

829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.

833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: Enable ethernet, tftpboot support to pic32mzdask board.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:22 +0000 (15:30 +0530)]
board: Enable ethernet, tftpboot support to pic32mzdask board.

This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
8 years agodrivers: net: Add ethernet driver for Microchip PIC32.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:21 +0000 (15:30 +0530)]
drivers: net: Add ethernet driver for Microchip PIC32.

This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
8 years agodrivers: net: phy: add SMSC LAN8740 Phy support.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:20 +0000 (15:30 +0530)]
drivers: net: phy: add SMSC LAN8740 Phy support.

Add SMSC LAN8740 Phy support required for PIC32MZDA devices.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agoboard: add SDHCI support for PIC32MZDASK board.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:19 +0000 (15:30 +0530)]
board: add SDHCI support for PIC32MZDASK board.

Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
8 years agodrivers: mmc: add driver for Microchip PIC32 SDHCI controller.
Andrei Pistirica [Thu, 28 Jan 2016 10:00:18 +0000 (15:30 +0530)]
drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.

Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoboard: Add Microchip PIC32MZ[DA]-Starter-Kit board.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:17 +0000 (15:30 +0530)]
board: Add Microchip PIC32MZ[DA]-Starter-Kit board.

This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoMIPS: Add support for Microchip PIC32MZ[DA] SoC family.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:16 +0000 (15:30 +0530)]
MIPS: Add support for Microchip PIC32MZ[DA] SoC family.

Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agodrivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:15 +0000 (15:30 +0530)]
drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agodrivers: serial: add driver for Microchip PIC32 UART controller.
Paul Thacker [Thu, 28 Jan 2016 10:00:14 +0000 (15:30 +0530)]
drivers: serial: add driver for Microchip PIC32 UART controller.

This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agodrivers: gpio: add driver for Microchip PIC32 GPIO controller.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:13 +0000 (15:30 +0530)]
drivers: gpio: add driver for Microchip PIC32 GPIO controller.

In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agodrivers: pinctrl: Add pinctrl driver for Microchip PIC32.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:12 +0000 (15:30 +0530)]
drivers: pinctrl: Add pinctrl driver for Microchip PIC32.

In PIC32 pin-controller is a combined gpio-controller, pin-mux and
pin-config module. Remappable peripherals are assigned pins through
per-pin based muxing logic. And pin configuration are performed on
specific port registers which are shared along with gpio controller.
Note, non-remappable peripherals have default pins assigned thus
require no muxing.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agodrivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:11 +0000 (15:30 +0530)]
drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoMIPS: initial infrastructure for Microchip PIC32 architecture
Purna Chandra Mandal [Thu, 28 Jan 2016 10:00:10 +0000 (15:30 +0530)]
MIPS: initial infrastructure for Microchip PIC32 architecture

Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agomalta: Use I/O accessors for SuperI/O controller
Paul Burton [Fri, 29 Jan 2016 13:54:54 +0000 (13:54 +0000)]
malta: Use I/O accessors for SuperI/O controller

Rather than passing the I/O port base address to the Super I/O code,
switch it to using outb such that it makes use of the I/O port base
address automatically.

Drop the extern keyword to satisfy checkpatch whilst here.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agomalta: Set I/O port base early
Paul Burton [Fri, 29 Jan 2016 13:54:53 +0000 (13:54 +0000)]
malta: Set I/O port base early

Set the I/O port base earlier, from board_early_init_f, in preparation
for it being used by the serial driver.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Support dynamic I/O port base address
Paul Burton [Fri, 29 Jan 2016 13:54:52 +0000 (13:54 +0000)]
MIPS: Support dynamic I/O port base address

The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Remove SLOW_DOWN_IO
Paul Burton [Fri, 29 Jan 2016 13:54:51 +0000 (13:54 +0000)]
MIPS: Remove SLOW_DOWN_IO

CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in
the SLOW_DOWN_IO macro. This is done in preparation for changes to
mips_io_port_base which can be avoided in this path by removing it
entirely.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agomips: cache: Bulletproof the code against cornercases
Marek Vasut [Wed, 27 Jan 2016 02:13:59 +0000 (03:13 +0100)]
mips: cache: Bulletproof the code against cornercases

This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.

The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
8 years agoMIPS: start.S: fix and optimize instructions
Daniel Schwierzeck [Sat, 9 Jan 2016 21:24:47 +0000 (22:24 +0100)]
MIPS: start.S: fix and optimize instructions

Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as
32 Bit register. Use 64 Bit register access for clearing gd_data
and copying U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoMIPS: initialize board_init_f() argument to zero.
Purna Chandra Mandal [Thu, 21 Jan 2016 14:32:51 +0000 (20:02 +0530)]
MIPS: initialize board_init_f() argument to zero.

Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoarmv8/ls1043aqds: fix DSPI/QSPI node in dts file
Qianyu Gong [Mon, 1 Feb 2016 05:09:16 +0000 (13:09 +0800)]
armv8/ls1043aqds: fix DSPI/QSPI node in dts file

Fix the lost dts info when merging patches.

Fix DSPI node for 'commit e0579a5852b3 ("armv8/ls1043aqds: add DSPI
support")' and QSPI node for 'commit 166ef1e90ce4 ("armv8/ls1043aqds:
add QSPI support in SD boot")'.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: net: fsl-mc: Update print to reflect correct string
Prabhakar Kushwaha [Wed, 20 Jan 2016 06:34:37 +0000 (12:04 +0530)]
driver: net: fsl-mc: Update print to reflect correct string

Update printf with dpbp_exit to match with previous function call.

Signed-off-by: Itai Katz <itai.katz@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: net: fsl-mc: Memset dprc_cfg before configuring
Prabhakar Kushwaha [Wed, 20 Jan 2016 06:34:19 +0000 (12:04 +0530)]
driver: net: fsl-mc: Memset dprc_cfg before configuring

All fields of struct dprc_cfg are not being configured while creating
child container. "Not" configured fields are assumed to be 0.

So memset dprc_cfg before configuring the fields.

Signed-off-by: Itai Katz <itai.katz@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv7: ls102xa: Increase the supported kernel size
Alison Wang [Fri, 15 Jan 2016 07:29:32 +0000 (15:29 +0800)]
armv7: ls102xa: Increase the supported kernel size

Increase the kernel size supported for LS1021A platform. Define
CONFIG_SYS_BOOTM_LEN to 64M.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: ls2085aqds: Update kernel_size env variable
Prabhakar Kushwaha [Wed, 6 Jan 2016 05:00:18 +0000 (10:30 +0530)]
board: ls2085aqds: Update kernel_size env variable

kernel_size env variable is defined as 0x28000000, it is beyond NOR
flash range. Update kernel_size with 40MB kernel size.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarm: novena: Fix EEPROM i2c configuration
Marek Vasut [Tue, 24 Nov 2015 23:36:44 +0000 (00:36 +0100)]
arm: novena: Fix EEPROM i2c configuration

On Novena, the DRAM SPD is connected to i2c1 while the Utility EEPROM
is connected to i2c3. Now that the EEPROM handling in U-Boot is fixed,
also fix this bit on Novena.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Stefano Babic <sbabic@denx.de>
8 years agoarm: config: enforce -fno-pic for gcc
Peng Fan [Sat, 30 Jan 2016 04:10:49 +0000 (12:10 +0800)]
arm: config: enforce -fno-pic for gcc

Android's tool chain enable the -mandroid at default.
This option will enable the -fpic, which cause uboot compilation
failure:
"
 LD      u-boot
 u-boot contains unexpected relocations: R_ARM_ABS32
 R_ARM_RELATIVE
"

In my testcase, arm-linux-androideabi-gcc-4.9 internally
enables '-fpic', so when compiling code, there will be
relocation entries using type R_ARM_GOT_BREL and .got
section. When linking all the built-in.o using ld, there
will be R_ARM_ABS32 relocation entry and .got section
in the final u-boot elf image. This can not be handled
by u-boot, since u-boot only expects R_ARM_RELATIVE
relocation entry.
arm-poky-linux-gnueabi-gcc-4.9 default does not enable '-fpic',
so there is not .got section and R_ARM_GOT_BREL in built-in.o.
And in the final u-boot elf image, all relocation entries are
R_ARM_RELATIVE.

we can pass '-fno-pic' to xxx-gcc to disable pic. whether
the toolchain internally enables or disables pic, '-fno-pic'
can work well.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
Wang Dongsheng [Mon, 18 Jan 2016 03:02:40 +0000 (11:02 +0800)]
ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined

"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.

Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460

60141140  00000017 R_ARM_RELATIVE
46 _secure_monitor:
47 #ifdef CONFIG_ARMV7_PSCI
48      ldr     r5, =_psci_vectors

60141194  00000017 R_ARM_RELATIVE
6014119c  00000017 R_ARM_RELATIVE
601411a4  00000017 R_ARM_RELATIVE
601411ac  00000017 R_ARM_RELATIVE
64 _psci_table:
66 .word psci_cpu_suspend
...
72 .word psci_migrate

60141344  00000017 R_ARM_RELATIVE
6014145c  00000017 R_ARM_RELATIVE
202 ldr     r5, =psci_text_end

Solutions:
1. Change absolute address to RelAdr.
   Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.

2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
   If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: cache: Implement cache range check for v7
Marek Vasut [Mon, 27 Jul 2015 20:34:17 +0000 (22:34 +0200)]
arm: cache: Implement cache range check for v7

Add code to aid tracking down cache alignment issues.
In case DEBUG is defined in the cache.c, this code will
check alignment of each attempt to flush/invalidate data
cache and print a warning if the alignment is incorrect.
If DEBUG is not defined, this code is optimized out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
8 years agoarmv7: add cacheline sizes where missing
Albert ARIBAUD [Wed, 27 Jan 2016 07:46:11 +0000 (08:46 +0100)]
armv7: add cacheline sizes where missing

Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: Remove S bit from MMU section entry
Marek Vasut [Tue, 29 Dec 2015 18:44:02 +0000 (19:44 +0100)]
arm: Remove S bit from MMU section entry

Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
8 years agoarm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7
Marek Vasut [Tue, 29 Dec 2015 18:44:01 +0000 (19:44 +0100)]
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7

The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.

The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.

The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
correct because the code which added the test(s) for CONFIG_ARMV7 was added
shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
not adjusted correctly to reflect that change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
8 years agovideo: Correct 'tor' typo in comment
Simon Glass [Fri, 15 Jan 2016 01:10:52 +0000 (18:10 -0700)]
video: Correct 'tor' typo in comment

This should be 'rot', not 'tor'.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: test: Add console tests for truetype
Simon Glass [Fri, 15 Jan 2016 01:10:51 +0000 (18:10 -0700)]
video: test: Add console tests for truetype

This adds tests for the different character types, line wrap, scrolling and
backspace.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: sandbox: Enable truetype fonts for sandbox
Simon Glass [Fri, 15 Jan 2016 01:10:50 +0000 (18:10 -0700)]
video: sandbox: Enable truetype fonts for sandbox

Enable this feature so that truetype fonts can be used on the sandbox
console. Update the tests to select the normal/rotated console when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
8 years agovideo: sandbox: Allow selection of font size and console name
Simon Glass [Fri, 15 Jan 2016 01:10:49 +0000 (18:10 -0700)]
video: sandbox: Allow selection of font size and console name

For testing it is useful to be able to select the font size and the console
driver for sandbox. Add this information to platform data and copy it to
the video device when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: Allow selection of the driver and font size
Simon Glass [Fri, 15 Jan 2016 01:10:48 +0000 (18:10 -0700)]
video: Allow selection of the driver and font size

Provide a way for the video console driver to be selected. This is
controlled by the video driver's private data. This can be set up when the
driver is probed so that it is ready for the video_post_probe() method.

The font size is provided as well. The console driver may or may not support
this depending on its capability.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
8 years agoLicense: Add the Open Font License
Simon Glass [Fri, 15 Jan 2016 01:10:47 +0000 (18:10 -0700)]
License: Add the Open Font License

This is used by two of the font files. Add this license to permit tracking
of this. The copyright text cannot be added to the .ttf files, so put it
here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
8 years agovideo: Add the Cantoraone decorative font
Simon Glass [Fri, 15 Jan 2016 01:10:46 +0000 (18:10 -0700)]
video: Add the Cantoraone decorative font

This font is a little more ornate than normal. Example uses are on security
screens where a feeling of formality is required.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: Add the Rufscript handwriting font
Simon Glass [Fri, 15 Jan 2016 01:10:45 +0000 (18:10 -0700)]
video: Add the Rufscript handwriting font

This can be used when a a friendly 'hand-writing' font is needed. It helps
to make the device feel familiar.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: Add the AnkaCoder mono-spaced font
Simon Glass [Fri, 15 Jan 2016 01:10:44 +0000 (18:10 -0700)]
video: Add the AnkaCoder mono-spaced font

This can be used when a mono-space font is needed, but the console font
is too small (such as with high-DPI displays).

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: Add the Nimbus sans font
Simon Glass [Fri, 15 Jan 2016 01:10:43 +0000 (18:10 -0700)]
video: Add the Nimbus sans font

This provides a good-looking font for user prompts.

Signed-off-by: Simon Glass <sjg@chromium.org>