Simon Glass [Wed, 29 Apr 2015 02:11:32 +0000 (20:11 -0600)]
x86: fsp: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port on boards that use a Firmware Support Package (FSP).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 29 Apr 2015 02:11:31 +0000 (20:11 -0600)]
x86: quark: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 29 Apr 2015 02:11:30 +0000 (20:11 -0600)]
x86: ivybridge: Use reset_cpu()
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 29 Apr 2015 02:11:29 +0000 (20:11 -0600)]
x86: Implement reset_cpu() correctly for modern CPUs
The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.
We can use port 0xcf9 to initiate reset on more modern hardware (say in the
last 10 years). Update the reset_cpu() function to do this, and add a new
'full reset' function to perform a full power cycle.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 20 Apr 2015 13:07:03 +0000 (07:07 -0600)]
x86: link: Add PCH driver to support SPI Flash
U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 20 Apr 2015 04:05:37 +0000 (22:05 -0600)]
x86: Update chromebook_link instructions for binary blob
The MRC image is incorrect, or at least this one now does not seem to
work. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Gabriel Huau [Sat, 25 Apr 2015 15:13:11 +0000 (08:13 -0700)]
x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 28 Apr 2015 10:37:03 +0000 (18:37 +0800)]
x86: Correct the typo in write_tables()
It should be #ifdef instead of #if.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Apr 2015 15:22:28 +0000 (23:22 +0800)]
x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONS
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
the text base address. Since it is deprecated, just remove it and use
CONFIG_SYS_TEXT_BASE directly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Apr 2015 15:22:27 +0000 (23:22 +0800)]
x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/Kconfig
Since all x86 boards have been converted to use DM_SPI and
DM_SPI_FLASH, move them to arch/Kconfig x86 section.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Apr 2015 15:22:26 +0000 (23:22 +0800)]
x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmetics
Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
fix the indention of its help text.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Apr 2015 15:22:25 +0000 (23:22 +0800)]
x86: Kconfig: Move platform options forward
Move platform-specific options under in arch/x86/Kconfig forward right
after the board-specific options but before any architecture-specific
options. When it comes to the same Kconfig option, board-specific one
takes take the highest precedence, then platform-specific one, and
finally architecture-specific one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Apr 2015 15:22:24 +0000 (23:22 +0800)]
x86: Kconfig: Divide the target selection to vendor/model
Let arch/x86/Kconfig prompt board vendor first, then select
the board model under that vendor. This way arch/x86/Kconfig
only needs concern board vendor and leave the supported target
list to board/<vendor>/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Apr 2015 06:16:02 +0000 (14:16 +0800)]
x86: quark: Turn on legacy segments decode
By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Apr 2015 06:16:01 +0000 (14:16 +0800)]
x86: Check PIRQ routing table sanity in the F segment
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final table in the F segment as this one is
the one seen by the OS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Gabriel Huau [Sat, 25 Apr 2015 20:16:57 +0000 (13:16 -0700)]
x86: minnowmax: add GPIO banks in the device tree
There are 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Gabriel Huau [Sat, 25 Apr 2015 20:16:03 +0000 (13:16 -0700)]
x86: baytrail: fix the GPIOBASE address
The correct GPIOBASE address on the baytrail is 0x48
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Apr 2015 17:46:43 +0000 (11:46 -0600)]
x86: Correct Minnowboard instructions to use the right descriptor
The descriptor provided with the FSP does not seem to work. Update the
instructions to use the descriptor from the original Intel firmware.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 24 Apr 2015 07:48:05 +0000 (15:48 +0800)]
biosemu: Do not free vga_info->BIOSImage when it is 0xc0000
For x86, vga_info->BIOSImage points to 0xc0000 which cannot be freed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 24 Apr 2015 07:48:04 +0000 (15:48 +0800)]
pci: Remove parameter 'class' of pci_rom_load()
pci_rom_load() does not use its parameter 'class', so remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 24 Apr 2015 07:48:03 +0000 (15:48 +0800)]
pci: Option rom class is a 24-bit number
We should pass a u32 class number to pci_rom_probe() instead of a u16.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 24 Apr 2015 10:10:06 +0000 (18:10 +0800)]
x86: queensbay: Implement PIRQ routing
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 24 Apr 2015 10:10:05 +0000 (18:10 +0800)]
x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).
We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 24 Apr 2015 10:10:04 +0000 (18:10 +0800)]
x86: Write configuration tables in last_stage_init()
We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 24 Apr 2015 10:10:03 +0000 (18:10 +0800)]
x86: Add a function to assign IRQ numbers to PCI device
Add a function to assign an IRQ number to PCI device's interrupt
line register in its configuration space, so that the PCI device
can have its interrupt working under PIC mode after OS boots up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 21 Apr 2015 04:21:36 +0000 (12:21 +0800)]
x86: Install a default e820 table in the __weak install_e820_map()
Create a default e820 table with 3 entries which is enough to boot
a Linux kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 21 Apr 2015 04:21:35 +0000 (12:21 +0800)]
x86: Clean up arch/x86/include/asm/e820.h
There are lots of unused codes defined in e820.h, clean it up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 15 Apr 2015 04:00:11 +0000 (12:00 +0800)]
x86: Add alias for SPI node in the board dts
Since Intel ICH SPI driver has been converted to driver model, we need
add an alias for SPI node in the board dts files otherwise SPI flash
won't be detected due to 'invalid bus' error.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 31 Mar 2015 03:25:03 +0000 (11:25 +0800)]
x86: Set serial port IRQ for SMSC LPC47M
For starting a Linux console on the superio serial port under
interrupt mode, the IRQ number must be configured.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 31 Mar 2015 03:51:04 +0000 (11:51 +0800)]
x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.h
Since all x86 boards use spi flash as its bootloader storage media,
it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option.
So far only minnowmax board does not support it so undefine it in
its board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 13 Apr 2015 11:03:42 +0000 (19:03 +0800)]
x86: queensbay: Avoid using PCH prefix
The prefix PCH was taken from ivybridge port. However Queensbay
platform official document does not mention PCH. It is composed
of TunnelCreek processor and Topcliff IOH chipset. For accuracy,
avoid using PCH prefix in the macro.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 13 Apr 2015 11:05:02 +0000 (19:05 +0800)]
x86: Remove the old VGA driver
CONFIG_VIDEO_VGA is no longer needed thus remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 13 Apr 2015 11:05:22 +0000 (19:05 +0800)]
x86: minnowmax: Remove CONFIG_VIDEO_X86 in the defconfig
CONFIG_VIDEO_X86 has been replaced by CONFIG_VIDEO_VESA.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 29 Apr 2015 10:46:33 +0000 (06:46 -0400)]
Merge branch 'zynq' of git://denx.de/git/u-boot-microblaze
Tom Rini [Wed, 29 Apr 2015 10:46:03 +0000 (06:46 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-microblaze
Masahiro Yamada [Mon, 16 Mar 2015 07:43:24 +0000 (16:43 +0900)]
ARM: zynq: rename CONFIG_ZYNQ to CONFIG_ARCH_ZYNQ
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Mon, 16 Mar 2015 07:43:23 +0000 (16:43 +0900)]
ARM: zynq: move SoC headers to mach-zynq/include/mach
Move arch/arm/include/asm/arch-zynq/*
-> arch/arm/mach-zynq/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Mon, 16 Mar 2015 07:43:22 +0000 (16:43 +0900)]
ARM: zynq: move SoC sources to mach-zynq
Move arch/arm/cpu/armv7/zynq/* -> arch/arm/mach-zynq/*
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Mon, 16 Mar 2015 07:43:21 +0000 (16:43 +0900)]
ARM: zynq: pass "-mfpu=neon" only to lowlevel_init.S
The comment line in arch/arm/cpu/armv7/zynq/config.mk says that
the option "-mfpu=neon" is necessary for compiling lowlevel_init.S.
We do not have to give it to all the source files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Apr 2015 13:21:37 +0000 (15:21 +0200)]
zynqmp: Enable SDHCI0 options
Enable SDHCI0 for zynqmp.
Add empty gpio.h because of sdhci requirement.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Fri, 13 Mar 2015 12:13:49 +0000 (17:43 +0530)]
zynqmp: Enable FS_GENERIC option
Provide an option to write filesystem independend commands.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Wed, 15 Apr 2015 06:18:48 +0000 (11:48 +0530)]
zynqmp: Add SPI driver support for ZynqMP
Added the SPI driver support for ZynqMP
The controller is same as zynq SPI controller
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Siva Durga Prasad Paladugu [Tue, 3 Mar 2015 09:31:44 +0000 (15:01 +0530)]
zynqmp: i2c: Enable i2c driver for zynqMP
Enable the i2c driver for ZynqMP
Also enable the eeprom for read and writes
to eeprom on ZynqMP
ZynqMP uses the same i2c controller as in Zynq
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Apr 2015 13:02:28 +0000 (15:02 +0200)]
zynqmp: Add support for EMMC bootmode
Add support for EMMC bootmode.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Apr 2015 12:59:19 +0000 (14:59 +0200)]
zynqmp: Add support for emulation platform - Veloce
Add support for Veloce - zynqmp emulation platform.
Platform doesn't support SDHCI.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Mon, 13 Apr 2015 05:27:04 +0000 (10:57 +0530)]
zynq: timer: Fix wrong timer calculation
Fix wrong timer calculation in get_timer_masked incase of
overflow.
This fixes the issue of getting wrong time from get_timer()
calls.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 8 Jul 2014 10:01:04 +0000 (15:31 +0530)]
zynqmp: sdhci: Remove the quirk SDHCI_QUIRK_NO_CD
Remove the quirk SDHCI_QUIRK_NO_CD as it is not
required.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Apr 2015 11:36:40 +0000 (13:36 +0200)]
zynqmp: Add support for R5 sw loading
Add support for loading sw for R5 with enabling for zynqmp.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Siva Durga Prasad Paladugu [Sat, 6 Dec 2014 07:27:51 +0000 (12:57 +0530)]
zynqmp: caches: Enable dcache for zynqmp
Define the mmu table till 2MB granularity
enable dcaches for zynqmp.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Mon, 2 Mar 2015 10:33:46 +0000 (16:03 +0530)]
zynq: slcr: Disable all level shifters
Disable all level shifters before enabling
the PS-to-PL level shifters as it would
be good to disable all level shifters before
enabling the PS-to-PL in order to ensure that
it is in proper state
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Tue, 14 Apr 2015 07:50:50 +0000 (16:50 +0900)]
ARM: zynq: drop legacy ps7_init.c/h support
We are about to change the location for ps7_init files, breaking the
current work-flows. It is good time to drop the legacy ps7_init.c/h
support.
Going forward, please use ps7_init_gpl.c/h all the time.
If you are still using old Xilinx tools that are only able to
generate ps7_init.c/h, rename them into ps7_init_gpl.c/h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nathan Rossi [Tue, 14 Apr 2015 04:58:10 +0000 (14:58 +1000)]
zynq: Add Zynq PicoZed board support
The PicoZed is a System-on-Module board which is marketed as part of
the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000
processor.
This patch adds support that covers all the variants of the PicoZed
including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This
patch set however only covers support for the System-on-Module and does
not cover any extra components that are available on carrier boards
(except those that are fanned out of the module itself).
More information on this board, its variants and available carrier
boards is available at: http://zedboard.org/product/picozed
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Apr 2015 11:05:06 +0000 (13:05 +0200)]
serial: zynq: Add support for slow emulation platform
On slow platforms not all baudrate setting is valid.
Check it directly in the driver and setup maximum possible
frequency.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 25 Mar 2015 12:35:04 +0000 (13:35 +0100)]
zynq: Enable GPIO driver and GPIO commands
Enable GPIO driver and GPIO commands.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Andrea Scian [Fri, 20 Mar 2015 15:00:25 +0000 (16:00 +0100)]
gpio: add Xilinx Zynq PS GPIO driver
Most of the code is taken (and adapted) from Linux kernel driver.
Just add CONFIG_ZYNQ_GPIO to you config to enable it
Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nathan Rossi [Tue, 14 Apr 2015 06:16:39 +0000 (16:16 +1000)]
microblaze: Fix EMAC Lite initialization
It is possible for CONFIG_XILINX_EMACLITE to be defined without
XILINX_EMACLITE_BASEADDR being defined as the EMAC Lite driver support
OF init. Check that the driver is enabled and the base address is
available before initializing with a static base address.
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Wed, 29 Apr 2015 00:48:43 +0000 (20:48 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-socfpga
Tom Rini [Tue, 28 Apr 2015 23:37:20 +0000 (19:37 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-dm
Simon Glass [Sat, 25 Apr 2015 04:33:07 +0000 (22:33 -0600)]
dm: core: Correct bug introduced in uclass_first/next_device()
These functions now rely on uclass_find_first/next_device() and assume that
they will either return failure (-ve error code) or a device. In fact,
coming to the end of a list is not considered failure and they return 0
in that case.
The logic to deal with this was replaced in commit
acb9ca2a with just using
uclass_get_device_tail(). Add back the missing logic. This bug was
caught by unit tests but since they were broken for other reasons at the
time, this was not noticed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Axel Lin [Sat, 25 Apr 2015 02:53:14 +0000 (10:53 +0800)]
serial: ns16550: Remove hard-coded baud_divisor setting
This was accidentally added by commit
dd0b0122bacc
"serial: ns16550: Add an option to specify the debug UART register shift".
Remove it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 24 Apr 2015 08:28:40 +0000 (17:28 +0900)]
dm: core: drop device removal error path correctly
Trivial bug fix for commit
5a87c4174d18 (dm: core: Drop device
removal error path when not supported).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 28 Apr 2015 16:15:13 +0000 (12:15 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Tom Rini [Tue, 28 Apr 2015 11:28:43 +0000 (07:28 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
Jagannadha Sutradharudu Teki [Mon, 27 Apr 2015 15:34:15 +0000 (21:04 +0530)]
sf: Fix to compute proper sector_size
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Bug report (from Bin Meng):
=> sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at
ffe00000
=> sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OK
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 24 Apr 2015 11:51:10 +0000 (19:51 +0800)]
dm: sf: Make SST flash write op work again
With SPI flash moving to driver model, commit
fbb0991 "dm: Convert
spi_flash_probe() and 'sf probe' to use driver model" ignored the
SST flash-specific write op (byte program & word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
SST flash-specific handling in the spi_flash_std_write().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Bin Meng [Tue, 28 Apr 2015 07:59:54 +0000 (13:29 +0530)]
dm: sf: Save flash flags to struct spi_flash
Add a new member 'flags' in struct spi_flash to store the flash flags
during spi_flash_validate_params().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
David Dueck [Wed, 1 Apr 2015 12:20:24 +0000 (14:20 +0200)]
spi: omap3: Fix timeout handling
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
"Spansion SPI flash read timeout with AM335x"
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Stefan Roese <sr@denx.de>
CC: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Fabio Estevam [Sat, 25 Apr 2015 21:47:21 +0000 (18:47 -0300)]
mx6cuboxi: Load the correct 'fdtfile' variable
Instead of hardcoding the 'fdtfile' variable, let's detect the SoC and
board variant on the fly and change the dtb name.
Based on the scheme done on am335x board.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabio Estevam [Sat, 25 Apr 2015 21:47:20 +0000 (18:47 -0300)]
mx6cuboxi: Use more standard namings for fdt variables
README file suggests to use 'fdtfile' for the dtb file name and
'fdt_addr_r' for the dtb address in RAM, so do as suggested.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabio Estevam [Sat, 25 Apr 2015 21:47:19 +0000 (18:47 -0300)]
mx6cuboxi: Differentiate Cubox-i and Hummingboard
Introduce is_hummingboard() function that reads GPIOs that can distinguish
between Cubox-i and Hummingboard.
Print the board name accordingly.
Based on a patch from Rabeeh Khoury.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabio Estevam [Sat, 25 Apr 2015 21:47:18 +0000 (18:47 -0300)]
mx6cuboxi: Introduce multi-SoC support
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad. Add support for the different SoC/memory sizes
combinations.
DDR initialization values were extracted from Solid-run internal U-boot.
Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabio Estevam [Sat, 25 Apr 2015 21:47:17 +0000 (18:47 -0300)]
mx6cuboxi: Prepare for multi SoC support
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad.
Use IOMUX_PADS() macro in order to prepare for the multi-SoC support.
Also pass 'MX6QDL' in the defconfig to indicate it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabio Estevam [Sat, 25 Apr 2015 21:47:16 +0000 (18:47 -0300)]
mx6cuboxi: Fix the defconfig name
The correct name of the defconfig file is 'mx6cuboxi_defconfig'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Pavel Machek [Sat, 25 Apr 2015 19:36:16 +0000 (21:36 +0200)]
socfpga: implement arria V socdk SPI flash config in dts
Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add
support for it.
Signed-off-by: Pavel Machek <pavel@denx.de>
Tom Rini [Fri, 24 Apr 2015 19:07:19 +0000 (15:07 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fdt
Tom Rini [Fri, 24 Apr 2015 17:44:28 +0000 (13:44 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Fri, 24 Apr 2015 17:43:24 +0000 (13:43 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Daniel Schwierzeck [Sun, 22 Feb 2015 15:58:30 +0000 (16:58 +0100)]
MIPS: implement device-tree handover to Linux kernel
Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.
[1] http://prplfoundation.org/wiki/MIPS_documentation
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Hans de Goede [Mon, 20 Apr 2015 09:13:37 +0000 (11:13 +0200)]
fdt: Fix handling of paths with options in them
After syncing the sunxi dts files with the upstream kernel dm/fdt sunxi
builds would no longer boot.
The problem is that stdout-path is now set like this in the upstream dts
files: stdout-path = "serial0:115200n8". The use of options in of-paths,
either after an alias name, or after a full path, e.g. stdout-path =
"/soc@
01c00000/serial@
01c28000:115200", is standard of usage, but something
which the u-boot dts code so far did not handle.
This commit fixes this, adding support for both path formats.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Pavel Machek [Thu, 23 Apr 2015 07:14:01 +0000 (09:14 +0200)]
socfpga: implement socdk SPI flash config in dts
SocDK has same QSPI and SPI flash configuration as Socrates. Add
support for it.
Signed-off-by: Pavel Machek <pavel@denx.de>
York Sun [Mon, 23 Mar 2015 17:41:35 +0000 (10:41 -0700)]
armv8/fsl-lsch3: Implement workaround for I2C erratum
A009203
This erratum requires setting GLITCH_EN bit in debug register to
enable digital filter to improve clock stability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>
Yangbo Lu [Sat, 21 Mar 2015 02:28:31 +0000 (19:28 -0700)]
ls2085a: esdhc: Add esdhc support for ls2085a
This patch adds esdhc support for ls2085a.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Tue, 24 Mar 2015 20:25:03 +0000 (13:25 -0700)]
armv8/ls2085ardb: Enable NAND SPL support
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit
252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Sat, 21 Mar 2015 02:28:29 +0000 (19:28 -0700)]
freescale/qixis: Add support for booting from NAND
Use "qixis_reset nand" to reset the board to boot from NAND.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Tue, 24 Mar 2015 20:25:02 +0000 (13:25 -0700)]
armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit
252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
Jaiprakash Singh [Sat, 21 Mar 2015 02:28:27 +0000 (19:28 -0700)]
driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Sat, 21 Mar 2015 02:28:26 +0000 (19:28 -0700)]
board/ls2085qds: Add support ethernet
Add support of ethernet:
- eth.c: mapping lane to slot for (0x2A, 0x07)
- ls2085a.c: To enable/disable dpmac and get link type
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Tom Rini [Thu, 23 Apr 2015 18:56:47 +0000 (14:56 -0400)]
Merge branch 'buildman' of git://git.denx.de/u-boot-x86
Tom Rini [Thu, 23 Apr 2015 17:53:09 +0000 (13:53 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-dm
Sanchayan Maity [Fri, 17 Apr 2015 13:26:42 +0000 (18:56 +0530)]
colibri_vf: Enable USB support for Colibri Vybrid
Enable USB support on Toradex Colibri Vybrid Modules.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Sanchayan Maity [Wed, 15 Apr 2015 10:54:27 +0000 (16:24 +0530)]
usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
This driver adds support for the USB peripheral on Freescale Vybrid
SoC's.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Sanchayan Maity [Wed, 15 Apr 2015 10:54:26 +0000 (16:24 +0530)]
ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.
- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
- for VF50, use PLL2 as memory clock (synchronous mode)
- for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default
Tested on Colibri VF50/VF61 booting using serial loader over UART.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Stefan Agner [Wed, 15 Apr 2015 10:54:25 +0000 (16:24 +0530)]
ARM: vf610: Enable caches
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Sanchayan Maity [Wed, 15 Apr 2015 10:54:24 +0000 (16:24 +0530)]
ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Stefan Agner [Wed, 15 Apr 2015 10:54:23 +0000 (16:24 +0530)]
ARM: vf610: Enable external 32KHz oscillator
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Sanchayan Maity [Wed, 15 Apr 2015 10:54:22 +0000 (16:24 +0530)]
ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Heiko Schocher [Sun, 12 Apr 2015 08:18:09 +0000 (10:18 +0200)]
cmd, nand: add more info to "nand info"
add subpagesize, nand options and bbt options to the
"nand info" output.
=> nand info
Device 0: nand0, sector size 256 KiB
Page size 4096 b
OOB size 256 b
Erase size 262144 b
subpagesize 4096 b
options 0x 200
bbt options 0x 8000
Signed-off-by: Heiko Schocher <hs@denx.de>
Marek Vasut [Thu, 9 Apr 2015 23:11:54 +0000 (01:11 +0200)]
rtc: Set valid date after reset
Some RTC chips tend to set garbage date after reset.
This patch sets the date to 2000-01-01 00:00 immediatelly
after the RTC chip reset is issued using the "date reset"
command.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Bryan De Faria [Thu, 2 Apr 2015 08:57:07 +0000 (10:57 +0200)]
arm: am437x: mux: Update mux names
Correct and complete the mux names following AM437x Technical Reference Manual.
Signed-off-by: Bryan De Faria <bdefaria-ext@adeneo-embedded.com>
angelo@sysam.it [Sun, 29 Mar 2015 20:54:16 +0000 (22:54 +0200)]
m68k: add architecture-specific u-boot.lds
Add architecture-specific u-boot.lds and remove all board-specific
u-boot.lds.
All the .text customization that was board-specific have been
moved inside the related include/configs, inside a
LDS_BOARD_TEXT define.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>