oweals/u-boot.git
4 years agoram: rk3328: update lpddr3 setting
YouMin Chen [Tue, 7 Jan 2020 07:15:22 +0000 (15:15 +0800)]
ram: rk3328: update lpddr3 setting

update lpddr3 setting for fix init fail about "col error".

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3328: add support ddr4 init
YouMin Chen [Tue, 7 Jan 2020 07:15:21 +0000 (15:15 +0800)]
ram: rk3328: add support ddr4 init

Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3328: only do data traning for cs0
Kever Yang [Tue, 7 Jan 2020 07:15:20 +0000 (15:15 +0800)]
ram: rk3328: only do data traning for cs0

No need to do twice data training for rk3328 ddr sdram, we re-use the
setting for both channel. And adjust the sdram_init properly for correct
init flow.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
4 years agodoc: boards: Add rockchip documentation
Jagan Teki [Thu, 9 Jan 2020 18:46:22 +0000 (00:16 +0530)]
doc: boards: Add rockchip documentation

Rockchip has documentation file, doc/README.rockchip but
which is not so readable to add or understand the existing
contents. Even the format that support is legacy readme
in U-Boot.

Add rockchip specific documentation file using new rst
format, which describes the information about Rockchip
supported boards and it's usage steps.

Added minimal information about rk3288, rk3328, rk3368
and rk3399 boards and usage. This would indeed updated
further based on the requirements and updates.

Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Add Single boot image (with binman, pad_cat)
Jagan Teki [Thu, 9 Jan 2020 18:46:21 +0000 (00:16 +0530)]
rockchip: Add Single boot image (with binman, pad_cat)

All rockchip platforms support TPL or SPL-based bootloader
in mainline with U-Boot proper as final stage. For each
stage we need to burn the image on to flash with respective
offsets.

This patch creates a single boot image component using
- binman, for arm32 rockchip platforms
- pad_cat, for arm64 rockchip platforms.

This would help users to get rid of burning different
boot stage images.

The new image called 'u-boot-rockchip.bin'
which can burn into flash like:

₹ sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64

This would support all rockchip platforms, except rk3128
since it doesn't support for SPL yet.

Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoarm: dts: rk3188: Add rk3188-u-boot.dtsi
Jagan Teki [Thu, 9 Jan 2020 18:46:20 +0000 (00:16 +0530)]
arm: dts: rk3188: Add rk3188-u-boot.dtsi

Add U-Boot specific dtsi file for rk3188 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3188.

Right now, the file is empty, will add required changes
in future patches.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoarm: dts: rk3036: Add rk3036-u-boot.dtsi
Jagan Teki [Thu, 9 Jan 2020 18:46:19 +0000 (00:16 +0530)]
arm: dts: rk3036: Add rk3036-u-boot.dtsi

Add U-Boot specific dtsi file for rk3036 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3036.

Right now, the file is empty, will add required changes
in future patches.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMakefile: rockchip: Support SPL-alone mkimage
Jagan Teki [Thu, 9 Jan 2020 18:46:18 +0000 (00:16 +0530)]
Makefile: rockchip: Support SPL-alone mkimage

Add SPL-alone mkimage tooling support via Makefile for
few platforms or boards used in rockchip family.

With this users would get rid of explicitly creating
mkimage tool for rockchip rksd or rkspi boot modes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMakefile: rockchip: Suffix platform type with tpl name
Jagan Teki [Thu, 9 Jan 2020 18:46:17 +0000 (00:16 +0530)]
Makefile: rockchip: Suffix platform type with tpl name

Most of the platforms uses the platform type on their boot
stage image naming conventions in makefile like,

u-boot-x86-start16-tpl.bin - x86 start16 TPL bin
u-boot-spl-mtk.bin - Mediatek SPL bin

This would help to understand the users to what that
particular image belongs to? and less confused.

On that note, suffix platform type rockchip for existing
u-boot-tpl.img so now it become u-boot-tpl-rockchip.bin

Also, bin is more conventional way to include it on tools
like binman, pad_cat etc in future patches.

Note: usage of platform type doesn't follow consistent order
as of now.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMakefile: Add rockchip image type
Jagan Teki [Thu, 9 Jan 2020 18:46:16 +0000 (00:16 +0530)]
Makefile: Add rockchip image type

Add rockchip image type support. right now the image
type marked with rksd, So create image type variable
with required image type like rksd or rkspi.

Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rk3399: Add bootcount support
Jagan Teki [Thu, 9 Jan 2020 08:52:19 +0000 (14:22 +0530)]
rockchip: rk3399: Add bootcount support

Add bootcount support for Rockchip rk3399.

The bootcount value is preserved in PMU_SYS_REG0 register,
this would help to support redundent boot.

Once the redundant boot triggers, the altboot command
will look for extlinux-rollback.conf on particular
bootable partition which supposed to be a recovery
partition where redundant boot required.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockchip: Add common reset cause
Jagan Teki [Thu, 9 Jan 2020 08:52:18 +0000 (14:22 +0530)]
rockchip: Add common reset cause

Add cpu reset cause in common cpu-info file.

This would help to print the reset cause for
various resets.

Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agoarm: rockchip: Add common cru.h
Jagan Teki [Thu, 9 Jan 2020 08:52:17 +0000 (14:22 +0530)]
arm: rockchip: Add common cru.h

Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.

So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.

The rest of rockchip cru files will add it in future.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockchip: rk3399: Enable DISPLAY_CPUINFO
Jagan Teki [Thu, 9 Jan 2020 08:52:16 +0000 (14:22 +0530)]
rockchip: rk3399: Enable DISPLAY_CPUINFO

RK3288, RK3399 are now support cpu-info, so enable
DISPLAY_CPUINFO by default.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockchip: Add cpu-info
Jagan Teki [Thu, 9 Jan 2020 08:52:15 +0000 (14:22 +0530)]
rockchip: Add cpu-info

Add cpu information for rockchip soc.

This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockpro-rk3399: Enable SPI Flash
Jagan Teki [Sat, 21 Dec 2019 07:54:39 +0000 (13:24 +0530)]
rockpro-rk3399: Enable SPI Flash

Enable winbond SPI flash for ROC-PC-RK3399 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoroc-pc-rk3399: Enable SPI Flash
Jagan Teki [Sat, 21 Dec 2019 07:54:38 +0000 (13:24 +0530)]
roc-pc-rk3399: Enable SPI Flash

Enable winbond SPI flash for ROC-PC-RK3399 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: dts: Sync ROC-RK3399-PC changes from Linux
Jagan Teki [Sat, 21 Dec 2019 07:54:37 +0000 (13:24 +0530)]
rockchip: dts: Sync ROC-RK3399-PC changes from Linux

Sync the ROC-RK3399-PC device tree changes from Linux
with below commit details:

commit <c36308abe4110e4db362d5e2ae3797834a7b1192> ("arm64: dts:
rockchip: Enable MTD Flash on rk3399-roc-pc")

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoenv: Enable SPI flash env for rockchip
Jagan Teki [Sat, 21 Dec 2019 07:54:36 +0000 (13:24 +0530)]
env: Enable SPI flash env for rockchip

Most of the SPI flash devices in rockchip are 16MiB size.

So, keeping U-Boot proper offset start from 128MiB with 1MiB
size and then start env of 8KiB would be a compatible location
between all variants of flash sizes.

This patch add env start from 0x14000 with a size of 8KiB.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoenv: kconfig: Restrict rockchip env for MMC
Jagan Teki [Sat, 21 Dec 2019 07:54:35 +0000 (13:24 +0530)]
env: kconfig: Restrict rockchip env for MMC

Rockchip do support SPI flash as well, so there is
a possibility of using flash environment for those
use cases.

So, restrict the current env offset, size for MMC.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agork3399: Check MMC env while defining it
Jagan Teki [Sat, 21 Dec 2019 07:54:34 +0000 (13:24 +0530)]
rk3399: Check MMC env while defining it

rk3399 do support SPI flash as well, so there is
a possibility of using flash environment for those
usecases.

So define env device for MMC only when it is used
by specific configuration.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3399: don't assume phy_io_config() uses real regs
Thomas Hebb [Fri, 20 Dec 2019 20:28:15 +0000 (12:28 -0800)]
ram: rk3399: don't assume phy_io_config() uses real regs

In the RK3399 DRAM driver, the function set_ds_odt() supports operating
in two different modes, selected by the ctl_phy_reg argument: when true,
the function reads and writes directly from the DRAM registers, accessed
through "chan->pctl->denali_*"; when false, the function reads and
writes from an array, accessed through "params->pctl_regs.denali_*",
which is written to DRAM registers at a later time.

However, phy_config_io(), which is called by set_ds_odt() to do a subset
of its register operations, operates directly on DRAM registers at all
times. This means that it reads incorrect values (and writes new values
prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by
passing in the address of the registers to work with.

This prevents an "Invalid DRV value" error in the SPL debug log and
(presumably) results in a more correct end state. See the following logs
from a RK3399 NanoPi M4 board (4GB LPDDR3):

Before:

  sdram_init() Starting SDRAM initialization...
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 0
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

After:

  sdram_init() Starting SDRAM initialization...
  sdram_init() sdram_init: data trained for rank 2, ch 0
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMerge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
Tom Rini [Wed, 29 Jan 2020 14:34:13 +0000 (09:34 -0500)]
Merge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c

i2c changes for 2020.04
- updates the Designware I2C driver
  - get timings from device tree
  - handle units in nanoseconds
  - make sure that the requested bus speed is not exceeded
  - few smaller clean-ups
- adds enums for i2c speed and update drivers which use them
- global_data: remove unused mxc_i2c specific field

4 years agoMerge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung
Tom Rini [Wed, 29 Jan 2020 02:10:32 +0000 (21:10 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung

- Various exynos fixes

4 years agoPrepare v2020.04-rc1 v2020.04-rc1
Tom Rini [Tue, 28 Jan 2020 21:59:30 +0000 (16:59 -0500)]
Prepare v2020.04-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agoMerge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
Tom Rini [Tue, 28 Jan 2020 00:57:13 +0000 (19:57 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

- spi cs accessing slaves (Bin Meng)
- spi prevent overriding established bus (Marcin Wojtas)
- support speed in spi command (Marek Vasut)
- add W25N01GV spinand (Robert Marko)
- move cadence_qspi to use spi-mem (Vignesh Raghavendra)
- add octal mode (Vignesh Raghavendra)

4 years agoarm: exynos: odroid: Change autoboot script to use ${mmcbootdev}
Marek Szyprowski [Fri, 17 Jan 2020 13:12:58 +0000 (14:12 +0100)]
arm: exynos: odroid: Change autoboot script to use ${mmcbootdev}

This fixes the default boot command for the SD-card boot case.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
4 years agoMerge branch '2020-01-27-master-imports'
Tom Rini [Tue, 28 Jan 2020 00:54:41 +0000 (19:54 -0500)]
Merge branch '2020-01-27-master-imports'

- Add Dialog DA9063 PMIC support
- s35392a RTC bugfix
- Allow for opt-in of removal of DTB properties from the resulting
  binary.

4 years agopmic: allow dump command for non contiguous register maps
Martin Fuzzey [Tue, 14 Jan 2020 15:56:18 +0000 (15:56 +0000)]
pmic: allow dump command for non contiguous register maps

Some PMICs (such as the DA9063) have non-contiguous register maps.
Attempting to read the non implemented registers returns an error
rather than a dummy value which causes 'pmic dump' to terminate
prematurely.

Fix this by allowing the PMIC driver to return -ENODATA for such
registers, which will then be displayed as '--' by pmic dump.

Use a single error code rather than any error code so that
we can distinguish between a hardware failure reading the PMIC
and a non implemented register known to the driver.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
4 years agopower: regulator: add driver for Dialog DA9063 PMIC
Martin Fuzzey [Tue, 14 Jan 2020 15:56:17 +0000 (15:56 +0000)]
power: regulator: add driver for Dialog DA9063 PMIC

Add a driver for the regulators in the the DA9063 PMIC.

Robert Beckett: move regulator modes to header so board code can set
modes. Correct mode mask used in ldo_set_mode.
Add an option CONFIG_SPL_DM_REGULATOR_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
4 years agopower: pmic: add driver for Dialog DA9063 PMIC
Martin Fuzzey [Tue, 14 Jan 2020 15:56:16 +0000 (15:56 +0000)]
power: pmic: add driver for Dialog DA9063 PMIC

This adds the basic register access operations and child regulator
binding (if a regulator driver exists).

Robert Beckett: simplify accesses by using bottom bit of address as
offset overflow. This avoids the need to track which page we are on.
Add an option CONFIG_SPL_DM_PMIC_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
4 years agortc: s35392a: encode command correctly
Ian Ray [Tue, 14 Jan 2020 16:18:20 +0000 (16:18 +0000)]
rtc: s35392a: encode command correctly

The 3-bit "command", or register, is encoded within the device address.
Configure the device accordingly, and pass command in DM I2C read/write
calls correctly.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
4 years agocmd: sata: Add block unbind device function
Peng Ma [Wed, 4 Dec 2019 10:36:47 +0000 (10:36 +0000)]
cmd: sata: Add block unbind device function

If we didn't unbind the sata from block device, the same devices would
be added after sata remove,
This patch is to resolve this issue as below:

=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
=> sata stop
=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agotbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfig
Anatolij Gustschin [Sun, 12 Jan 2020 14:57:43 +0000 (15:57 +0100)]
tbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfig

This shrinks the image size: all -3840.0 text -3840.0

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Soeren Moch <smoch@web.de>
4 years agodts: add property removal option CONFIG_OF_REMOVE_PROPS
Anatolij Gustschin [Sun, 12 Jan 2020 14:57:42 +0000 (15:57 +0100)]
dts: add property removal option CONFIG_OF_REMOVE_PROPS

This can be used for device tree size reduction similar as
CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the
built-in DTB unchanged to the kernel, thus we may not cut it
down unconditionally. Therefore enable the property removal
list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
4 years agoarm: exynos: Read default MMC device from XOM[7:5] pins
Marek Szyprowski [Fri, 17 Jan 2020 13:02:44 +0000 (14:02 +0100)]
arm: exynos: Read default MMC device from XOM[7:5] pins

XOM pins provide information for iROM bootloader about the boot device.
Those pins are mapped to lower bits of OP_MODE register (0x10000008),
which is common for all Exynos SoC variants. Set the default MMC device id
to reflect the boot device selected by XOM[7:5] pins (2 for the SD or 0 for
the eMMC).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
4 years agospi: cadence-qspi: Add compatible for TI AM654
Vignesh Raghavendra [Thu, 5 Dec 2019 10:16:07 +0000 (15:46 +0530)]
spi: cadence-qspi: Add compatible for TI AM654

TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: cadence-qspi: Add support for Cadence Octal SPI controller
Vignesh Raghavendra [Thu, 5 Dec 2019 10:16:06 +0000 (15:46 +0530)]
spi: cadence-qspi: Add support for Cadence Octal SPI controller

Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agomtd: spi-nor-core: Add octal mode support
Vignesh Raghavendra [Thu, 5 Dec 2019 10:16:05 +0000 (15:46 +0530)]
mtd: spi-nor-core: Add octal mode support

Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: cadence-qspi: Add direct mode support
Vignesh Raghavendra [Mon, 27 Jan 2020 05:06:40 +0000 (10:36 +0530)]
spi: cadence-qspi: Add direct mode support

Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.

For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: cadence_qspi: Move to spi-mem framework
Vignesh Raghavendra [Mon, 27 Jan 2020 05:06:39 +0000 (10:36 +0530)]
spi: cadence_qspi: Move to spi-mem framework

Current Cadence QSPI driver has few limitations. It assumes all read
operations to be in Quad mode and thus does not support SFDP parsing.
Also, adding support for new mode such as Octal mode would not be
possible with current configuration. Therefore move the driver over to spi-mem
framework. This has added advantage that driver can be used to support
SPI NAND memories too.
Hence, move driver over to new spi-mem APIs.

Please note that this gets rid of mode bit setting done when
CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
that config option.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agomtd: spinand: winbond: Add support for W25N01GV
Robert Marko [Thu, 16 Jan 2020 13:03:35 +0000 (14:03 +0100)]
mtd: spinand: winbond: Add support for W25N01GV

Linux has supported W25N01GV for a long time, so lets import it.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: ti_qspi: Add support for CS other than CS0
Vignesh Raghavendra [Wed, 11 Dec 2019 13:29:36 +0000 (18:59 +0530)]
spi: ti_qspi: Add support for CS other than CS0

Make sure corresponding setup registers are updated depending on CS.
This ensures that driver can support QSPI flashes on ChipSelects other
than on CS0

Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: prevent overriding established bus settings
Marcin Wojtas [Thu, 21 Nov 2019 04:38:47 +0000 (05:38 +0100)]
spi: prevent overriding established bus settings

The SPI stack relies on a proper bus speed/mode configuration
by calling dm_spi_claim_bus(). However the hitherto code
allowed to accidentally override those settings in
the spi_get_bus_and_cs() routine.

The initially established speed could be discarded by using
the slave platdata, which turned out to be an issue on
the platforms whose slave maximum supported frequency
is not on par with the maximum frequency of the bus controller.

This patch fixes above issue by configuring the bus from
spi_get_bus_and_cs() only in case it was not done before.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agocmd: spi: Permit setting bus frequency
Marek Vasut [Fri, 20 Dec 2019 11:44:57 +0000 (12:44 +0100)]
cmd: spi: Permit setting bus frequency

The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions.
Allow changing that at runtime by specifying '@freq' bus frequency in Hz.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agotest: dm: spi: Fix sandbox dm_test_spi_find()
Bin Meng [Mon, 9 Sep 2019 13:00:03 +0000 (06:00 -0700)]
test: dm: spi: Fix sandbox dm_test_spi_find()

Per sandbox_cs_info(), sandbox spi controller only supports chip
select 0. Current test case tries to locate devices on chip select
1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs
number 1 should not return 0.

This updates the test case to handle it correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agodm: spi: Check cs number before accessing slaves
Bin Meng [Mon, 9 Sep 2019 13:00:02 +0000 (06:00 -0700)]
dm: spi: Check cs number before accessing slaves

Add chip select number check in spi_find_chip_select().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
4 years agospi: nxp_fspi: new driver for the FlexSPI controller
Michael Walle [Tue, 17 Dec 2019 23:09:58 +0000 (00:09 +0100)]
spi: nxp_fspi: new driver for the FlexSPI controller

This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.

The port was straightforward:
 - remove the interrupt handling and the completion by busy polling the
   controller
 - remove locks
 - move the setup of the memory windows into claim_bus()
 - move the setup of the speed into set_speed()
 - port the device tree bindings from the original fspi_probe() to
   ofdata_to_platdata()

There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.

This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
4 years agoMerge tag 'u-boot-clk-26Jan2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
Tom Rini [Mon, 27 Jan 2020 12:19:26 +0000 (07:19 -0500)]
Merge tag 'u-boot-clk-26Jan2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk

- Various clock fixes and enhancements

4 years agoi2c: designware_i2c: Do more in the probe() method
Simon Glass [Thu, 23 Jan 2020 18:48:26 +0000 (11:48 -0700)]
i2c: designware_i2c: Do more in the probe() method

Move some of the code currently in the ofdata_to_platdata() method to
probe() so that it is not executed when generating ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Separate out the speed calculation
Simon Glass [Thu, 23 Jan 2020 18:48:25 +0000 (11:48 -0700)]
i2c: designware_i2c: Separate out the speed calculation

We want to be able to calculate the speed separately from actually setting
the speed, so we can generate the required ACPI tables. Split out the
calculation into its own function.

Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
That is reserved for compiler internals.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Move dw_i2c_speed_config to header
Simon Glass [Thu, 23 Jan 2020 18:48:24 +0000 (11:48 -0700)]
i2c: designware_i2c: Move dw_i2c_speed_config to header

This is used to store the speed information for a bus. We want to provide
this to ACPI so that it can tell the kernel. Move this struct to the
header file so it can be accessed by the ACPI i2c implementation being
added later.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Add support for fast-plus speed
Simon Glass [Thu, 23 Jan 2020 18:48:23 +0000 (11:48 -0700)]
i2c: designware_i2c: Add support for fast-plus speed

Fast-plus runs at 1MHz and is used by some devices. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: Update drivers to use enum for speed
Simon Glass [Thu, 23 Jan 2020 18:48:22 +0000 (11:48 -0700)]
i2c: Update drivers to use enum for speed

Convert the obvious uses of i2c bus speeds to use the enum.

Use livetree access for code changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: stm32: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:21 +0000 (11:48 -0700)]
i2c: stm32: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: omap: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:20 +0000 (11:48 -0700)]
i2c: omap: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: kona_i2c: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:19 +0000 (11:48 -0700)]
i2c: kona_i2c: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:18 +0000 (11:48 -0700)]
i2c: designware_i2c: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: ast_i2c: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:17 +0000 (11:48 -0700)]
i2c: ast_i2c: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: Add enums for i2c speed and address size
Simon Glass [Thu, 23 Jan 2020 18:48:16 +0000 (11:48 -0700)]
i2c: Add enums for i2c speed and address size

Some drivers define their own speed enums and use their own constants for
speed. It makes sense to have a unified defition of the different speeds.

Since many controllers have to do different things for fast/high speed, it
is a good idea to have an enum for the mode.

Add these as well as an enum for the address mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Add spike supression
Simon Glass [Thu, 23 Jan 2020 18:48:15 +0000 (11:48 -0700)]
i2c: designware_i2c: Add spike supression

Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Rewrite timing calculation
Simon Glass [Thu, 23 Jan 2020 18:48:14 +0000 (11:48 -0700)]
i2c: designware_i2c: Rewrite timing calculation

At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.

Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than writing it in code.

The function works by calculating the 'period' of each bit on the bus in
terms of the input clock to the controller (IC_CLK). It makes sure that
the constraints are met and that the different components of that period
add up correctly.

This code was taken from coreboot which has ended up with this same
driver, but now in a much-different form.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Put hold config in a struct
Simon Glass [Thu, 23 Jan 2020 18:48:13 +0000 (11:48 -0700)]
i2c: designware_i2c: Put hold config in a struct

Create a struct to hold the three timing parameters. This will make it
easier to move these calculations into a separate function in a later
patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Drop scl_sda_cfg parameter
Simon Glass [Thu, 23 Jan 2020 18:48:12 +0000 (11:48 -0700)]
i2c: designware_i2c: Drop scl_sda_cfg parameter

Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in
the driver's private data, from which the function can obtain that
information. This allows the function to have access to the full state of
the driver.

Signed-off-by: Sicomp_param1mon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Read device-tree properties
Simon Glass [Thu, 23 Jan 2020 18:48:11 +0000 (11:48 -0700)]
i2c: designware_i2c: Read device-tree properties

The i2c controller defines a few timing properties. Read these in and
store them for use by the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Bring in the binding file
Simon Glass [Thu, 23 Jan 2020 18:48:10 +0000 (11:48 -0700)]
i2c: designware_i2c: Bring in the binding file

Bring in this file from Linux v5.4.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Use an accurate bus clock instead of MHz
Simon Glass [Thu, 23 Jan 2020 18:48:09 +0000 (11:48 -0700)]
i2c: designware_i2c: Use an accurate bus clock instead of MHz

At present the driver uses an approximation for the bus clock, e.g. 166MHz
instead of 166 2/3 MHz.

This can result in small errors in the resulting I2C speed, perhaps 0.5%
or so.

Adjust the existing code to start from the accurate figure, even if later
rounding reduces this accuracy.

Update the bus speed code to work in KHz instead of MHz, which removes
most of the error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Use an enum for selected speed mode
Simon Glass [Thu, 23 Jan 2020 18:48:08 +0000 (11:48 -0700)]
i2c: designware_i2c: Use an enum for selected speed mode

Group these #defines into an enum to make it easier to understand the
relationship between them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Rename 'max' speed to 'high' speed
Simon Glass [Thu, 23 Jan 2020 18:48:07 +0000 (11:48 -0700)]
i2c: designware_i2c: Rename 'max' speed to 'high' speed

Some SoCs support a higher speed than what is currently called 'max' in
this driver. Rename it to 'high' speed, which is the official name of the
3.4MHz speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Include clk.h in the header file
Simon Glass [Thu, 23 Jan 2020 18:48:06 +0000 (11:48 -0700)]
i2c: designware_i2c: Include clk.h in the header file

We use struct clk here so really should include this header file to avoid
build errors. Also switch the order of clk.h in the C file to match the
required code style.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Don't allow changing IC_CLK
Simon Glass [Thu, 23 Jan 2020 18:48:05 +0000 (11:48 -0700)]
i2c: designware_i2c: Don't allow changing IC_CLK

If a different input clock is required then the correct way to do this is
with a clock driver. Don't allow boards to override IC_CLK.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Add more registers
Simon Glass [Thu, 23 Jan 2020 18:48:04 +0000 (11:48 -0700)]
i2c: designware_i2c: Add more registers

Some versions of this peripherals provide more control of the bus
behaviour. Add definitions for these registers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoglobal_data: remove unused mxc_i2c specific field
Baruch Siach [Wed, 25 Dec 2019 15:57:06 +0000 (17:57 +0200)]
global_data: remove unused mxc_i2c specific field

The srdata field is unused since commit 71204e95ce13228 ("i2c: mxc:
refactor i2c driver and support dm").

Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
4 years agoclock_imx8mq: Make frac_pll_init() static
Pedro Jardim [Thu, 23 Jan 2020 13:21:53 +0000 (10:21 -0300)]
clock_imx8mq: Make frac_pll_init() static

Since frac_pll_init() is only used in this file, change it to 'static'.

This fixes the following sparse warning:

arch/arm/mach-imx/imx8m/clock_imx8mq.c:662:5: warning: no previous
prototype for ‘frac_pll_init’ [-Wmissing-prototypes]

Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
4 years agoclock_imx8mq: Remove the function sscg_pll_init()
Pedro Jardim [Thu, 23 Jan 2020 13:21:05 +0000 (10:21 -0300)]
clock_imx8mq: Remove the function sscg_pll_init()

Function sscg_pll_init() is not used anywhere, so it can simply be deleted.
This was found because of the following sparse
warning:

arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype for ‘sscg_pll_init’ [-Wmissing-prototypes]
 int sscg_pll_init(u32 pll)
     ^~~~~~~~~~~~~

Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
4 years agoclock_imx8mq: Make do_imx8m_showclocks() static
Pedro Jardim [Thu, 23 Jan 2020 13:20:51 +0000 (10:20 -0300)]
clock_imx8mq: Make do_imx8m_showclocks() static

Since do_imx8m_showclocks() is only used inside this file, make it 'static'.

This fixes the following sparse warning:

arch/arm/mach-imx/imx8m/clock_imx8mq.c:836:5: warning: no previous prototype
 for ‘do_imx8m_showclocks’ [-Wmissing-prototypes]
 int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
     ^~~~~~~~~~~~~~~~~~~

Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
4 years agoclock_imx8mq: Delete not used init_usb_clk()
Pedro Jardim [Thu, 23 Jan 2020 13:20:14 +0000 (10:20 -0300)]
clock_imx8mq: Delete not used init_usb_clk()

Function init_usb_clk() is not used anywhere, so it can simply be deleted.
This was detected by the following sparse warning:

arch/arm/mach-imx/imx8m/clock_imx8mq.c:377:6: warning: no previous prototype
 for ‘init_usb_clk’ [-Wmissing-prototypes]
 void init_usb_clk(void)
      ^~~~~~~~~~~~

Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
4 years agoclk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()
Giulio Benetti [Fri, 17 Jan 2020 12:06:42 +0000 (13:06 +0100)]
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()

Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
4 years agoclk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()
Giulio Benetti [Fri, 17 Jan 2020 12:06:41 +0000 (13:06 +0100)]
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()

Guard 'mfd==0' to prevent 'divide by zero' issue in
clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd
should never be 0 at all.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
4 years agoclk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()
Giulio Benetti [Fri, 17 Jan 2020 12:06:40 +0000 (13:06 +0100)]
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()

Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
4 years agocommon: fix regression on block cache init
Angelo Durgehello [Sun, 26 Jan 2020 18:31:22 +0000 (19:31 +0100)]
common: fix regression on block cache init

m68k needs block cache list initialized after relocation.
Other architectures must not be involved.

Fixing regression related to:

commit 1526bcce0f7285087621e16e6720636d01839da8
("common: add blkcache init")

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
4 years agoarm: mvebu: fix A38x breakage from commit bb872dd930cc
Joel Johnson [Sun, 26 Jan 2020 16:48:58 +0000 (09:48 -0700)]
arm: mvebu: fix A38x breakage from commit bb872dd930cc

This function parameter usage of load_addr was incorrectly caught in
the clarifying renames of commit bb872dd930cc, which results in boot
failures on Marvell A38x.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Patch-to: Simon Glass <sjg@chromium.org>

4 years agoMerge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
Tom Rini [Sun, 26 Jan 2020 17:05:11 +0000 (12:05 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi

- Libre Computer ALL-H3-IT/ALL-H5-CC board (Chen-Yu Tsai)
- Allwinner R40 Ethernet, usb phy enablement (Andre Przywara)
- Sunxi auto load from 128KB MMC offset (Andre Przywara)
- Orange Pi Win Ethernet phy enablement (Jernej Skrabec)

4 years agoconfigs: Orange Pi Win: enable ethernet phy
Jernej Skrabec [Sun, 26 Jan 2020 12:38:34 +0000 (13:38 +0100)]
configs: Orange Pi Win: enable ethernet phy

Orange Pi Win has gigabit ethernet port, but default U-Boot
configuration for that board enabled ethernet driver but
didn't enable realtek phy.

Fix that.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agosunxi: Automate loading from 128KB MMC offset
Andre Przywara [Fri, 10 Jan 2020 01:47:32 +0000 (01:47 +0000)]
sunxi: Automate loading from 128KB MMC offset

Since commit 067e0b9684d4 ("sunxi: Allow booting from 128KB SD/eMMC offset")
we support having the SPL loaded from either the traditional 8KB SD
card/eMMC offset, or from the alternative location at 128KB. However the
sector to find the U-Boot image was still hard-coded at compile time,
and had to be adjusted for one of the two choices.

Since we can actually override the function to return the sector offset,
we can just check the boot source byte there to select the proper offset
based on from where the SPL was loaded.

This allows the very same binary image to be loaded from either 128KB or
8KB, with the U-Boot proper image always being located just behind the SPL.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agosunxi: SPL: Factor out sunxi_get_boot_source()
Andre Przywara [Fri, 10 Jan 2020 01:47:31 +0000 (01:47 +0000)]
sunxi: SPL: Factor out sunxi_get_boot_source()

The Boot ROM write some boot source ID (SD card, eMMC, SPI, ...) into
a certain location in SRAM, so the SPL can easily determine where to
load U-Boot proper from.
Factor out reading this value, as it will come in handy again shortly.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agoclk: Fix error checking of dev_read_addr_ptr
Sean Anderson [Wed, 25 Dec 2019 04:57:47 +0000 (23:57 -0500)]
clk: Fix error checking of dev_read_addr_ptr

dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
4 years agoclk: Include missing headers for linux/clk-provider.h
Sean Anderson [Wed, 25 Dec 2019 04:56:22 +0000 (23:56 -0500)]
clk: Include missing headers for linux/clk-provider.h

This header was missing a couple of include dependencies when included on its
own.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
4 years agoclk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA is enabled
Giulio Benetti [Thu, 12 Dec 2019 22:53:19 +0000 (23:53 +0100)]
clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA is enabled

clk_get_by_name() requires clk_get_by_id() that is not available if
CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else
condition of #if CONFIG_IS_ENABLED(OF_PLATDATA).

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
4 years agoclk: show more error info when uclass_get_device_by_name
Peng Fan [Tue, 22 Oct 2019 03:31:08 +0000 (03:31 +0000)]
clk: show more error info when uclass_get_device_by_name

It will ease debug when uclass_get_device_by_name failed with
more error info printed out.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
4 years agoclk: mediatek: use unsigned type for returning the clk rate
Fabien Parent [Thu, 17 Oct 2019 19:02:05 +0000 (21:02 +0200)]
clk: mediatek: use unsigned type for returning the clk rate

mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.

This commit change the return type of mtk_clk_find_parent_rate to
ulong.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Tom Rini [Sat, 25 Jan 2020 17:20:51 +0000 (12:20 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Updates and fixes for ls1028a, lx2160a, ls1012a, ls1021a, ls2080a,
ls1088a platforms:
- lx2-rev2 pcie support, enetc related updates, layerscape-pcie fixes

4 years agoMerge branch '2020-01-24-master-imports'
Tom Rini [Sat, 25 Jan 2020 17:04:59 +0000 (12:04 -0500)]
Merge branch '2020-01-24-master-imports'

- Enable fastboot on some MediaTek platforms
- DMA enchancements
- Assorted bugfixes

4 years agomtd: add prototypes for weak function
Patrick Delaunay [Fri, 24 Jan 2020 12:45:56 +0000 (13:45 +0100)]
mtd: add prototypes for weak function

This patch adds a prototype for the weak function
board_mtdparts_default().

It solves one warning when compiling with W=1 on stm32mp1 board:

board/st/stm32mp1/stm32mp1.c:
     warning: no previous prototype for 'board_mtdparts_default'
              [-Wmissing-prototypes]
     void board_mtdparts_default(const char **mtdids,
                                 const char **mtdparts)
          ^~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agocommon: blk: fix comment about blkcache_read return value
Eric Nelson [Wed, 22 Jan 2020 23:59:55 +0000 (16:59 -0700)]
common: blk: fix comment about blkcache_read return value

The blkcache_read() routine returns 1 (true) to indicate that a block was
found in the cache and returned, or 0 if not.

Signed-off-by: Eric Nelson <eric@nelint.com>
4 years agomeerkat96: fix typo in MAINTAINERS email address
Shawn Guo [Fri, 24 Jan 2020 04:59:42 +0000 (12:59 +0800)]
meerkat96: fix typo in MAINTAINERS email address

There is a typo in meerkat96 MAINTAINERS email address.  Fix it.

Reported-by: Carl Gelfand <carl@novtech.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
4 years agogenboardscfg.py: drop python version comment
Baruch Siach [Wed, 22 Jan 2020 12:54:24 +0000 (14:54 +0200)]
genboardscfg.py: drop python version comment

genboardscfg.py requires python 3.x since commit 3bc14098d8fb
("genboardscfg.py: Convert to Python 3").

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agocommon: add blkcache init
Angelo Durgehello [Tue, 21 Jan 2020 09:37:27 +0000 (10:37 +0100)]
common: add blkcache init

On m68k, block_cache list is relocated, but next and prev list
pointers are not adjusted to the relocated struct list_head address,
so the first iteration over the block_cache list hangs.

This patch initializes the block_cache list after relocation.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
4 years agonet: macb: Drop local cache flush
Vignesh Raghavendra [Thu, 16 Jan 2020 08:53:48 +0000 (14:23 +0530)]
net: macb: Drop local cache flush

Now that arch specific dma mapping APIs take care of cache
flush/invalidate, drop local cache flush operation.
While at that fix dma_unmap_single() call to match new prototype

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
4 years agomtd: denali: Drop custom dma mapping functions
Vignesh Raghavendra [Thu, 16 Jan 2020 08:53:47 +0000 (14:23 +0530)]
mtd: denali: Drop custom dma mapping functions

Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>