oweals/u-boot.git
6 years agosdhci: Add new sdhci ops for platform specific tuning and delays
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:06 +0000 (12:37 +0530)]
sdhci: Add new sdhci ops for platform specific tuning and delays

This patch adds new hooks for any platform specific tuning and
tap delays programing. These are needed for supporting
SD3.0.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agommc: sdhci: Handle execute tuning command in sdhci_send_command
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:05 +0000 (12:37 +0530)]
mmc: sdhci: Handle execute tuning command in sdhci_send_command

This patch upadted sdhci_send_command to handle execute tuning
command.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agommc: sdhci: Add support for disabling clock
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:04 +0000 (12:37 +0530)]
mmc: sdhci: Add support for disabling clock

This patch adds support to disable clock if clk_disable
was set and then enable or set clock if the clock was changed
or clock was disabled when clock needs to be enabled.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agommc: Changed the datatype of the variable to handle 64-bit arch
Vipul Kumar [Thu, 3 May 2018 06:50:54 +0000 (12:20 +0530)]
mmc: Changed the datatype of the variable to handle 64-bit arch

This patch changed the datatype of variable "start" from uint to ulong
to work properly on 64-bit machines as well. Also the return type of
get_timer() function is ulong.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynqmp: Add ZynqMP minimal R5 support
Michal Simek [Thu, 12 Apr 2018 15:39:46 +0000 (17:39 +0200)]
arm: zynqmp: Add ZynqMP minimal R5 support

Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.

This configuration with uart1 was tested on zcu100-revC.

U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)

Model: Xilinx ZynqMP R5
DRAM:  512 MiB
WARNING: Caches not enabled
MMC:
In:    serial@ff010000
Out:   serial@ff010000
Err:   serial@ff010000
Net:   Net Initialization Skipped
No ethernet found.
ZynqMP r5>

There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split

2. Load via jtag when directly to R5

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agotools: zynqmpimage: Add bif support
Alexander Graf [Fri, 13 Apr 2018 12:18:52 +0000 (14:18 +0200)]
tools: zynqmpimage: Add bif support

The officially described way to generate boot.bin files for ZynqMP is to
describe the contents of the target binary using a file of the "bif"
format.  This file then links to other files that all get packed into a
bootable image.

This patch adds support to read such a .bif file and generate a respective
ZynqMP boot.bin file that can include the normal image and pmu files, but
also supports image partitions now. This makes it a handy replacement for
the proprietary "bootgen" utility that is currently used to generate
boot.bin files with FSBL.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoMAINTAINERS: Declare tools/zynqmp* as Xilinx maintained
Alexander Graf [Fri, 13 Apr 2018 12:18:51 +0000 (14:18 +0200)]
MAINTAINERS: Declare tools/zynqmp* as Xilinx maintained

The zynqmpimage.c and the new zynqmpbif.c files are all maintained by
Xilinx for the Zynq platforms. Let's match them accordingly
in the MAINTAINERS file.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agotools: zynqmpimage: Move defines to header
Alexander Graf [Fri, 13 Apr 2018 12:18:50 +0000 (14:18 +0200)]
tools: zynqmpimage: Move defines to header

We will add support for ZynqMP bif input files later, so let's move
all structure definitions into a header file that can be used by that
one as well.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agotools: zynqmpimage: Add partition read support
Alexander Graf [Fri, 13 Apr 2018 12:18:49 +0000 (14:18 +0200)]
tools: zynqmpimage: Add partition read support

The zynqmp image format has support for inline partitions which are
used by FSBL to describe payloads that are loaded by FSBL itself.

While we can't create images that contain partitions (yet), we should
still at least be able to examine them and show the user what's inside
when we analyze an image created by bootgen.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm64: zynqmp: Show model information instead of custom IDENT_STRING
Michal Simek [Mon, 30 Apr 2018 07:26:47 +0000 (09:26 +0200)]
arm64: zynqmp: Show model information instead of custom IDENT_STRING

DISPLAY_BOARDINFO in OF case show model identification string from DT.
Enable this feature instead of custom IDENT_STRING which does the same
thing.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
6 years agoarm64: zynqmp: Simplify boot_target variable composition
Michal Simek [Wed, 25 Apr 2018 09:10:34 +0000 (11:10 +0200)]
arm64: zynqmp: Simplify boot_target variable composition

Call calloc for space allocation only at one location and include if/else
to sprintf. This will simplify run time device adding based on id aliases.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
6 years agoarm64: zynqmp: Setup MMU map for DDR at run time
Nitin Jain [Fri, 20 Apr 2018 07:00:40 +0000 (12:30 +0530)]
arm64: zynqmp: Setup MMU map for DDR at run time

This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.

The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.

Signed-off-by: Nitin Jain <nitin.jain@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm64: zynqmp: Enable cadence WDT for zcu100
Michal Simek [Thu, 19 Apr 2018 13:43:50 +0000 (15:43 +0200)]
arm64: zynqmp: Enable cadence WDT for zcu100

Enable watchdog on zcu100 to make sure if there is a bug in the u-boot
there is proper reset.
Watchdog expires and PMU fw is informed and based on setting proper
action is taken.

The patch is enabling reset-on-timeout feature and also fixing fixed
clock rate for watchdog where 100MHz is max (and also default) clock value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm64: zynqmp: Wire watchdog internals
Michal Simek [Thu, 19 Apr 2018 13:43:38 +0000 (15:43 +0200)]
arm64: zynqmp: Wire watchdog internals

Enable watchdog in full U-Boot.

Similar changes were done by:
"arm: zynq: Wire watchdog internals"
(sha1: e6cc3b25d721c3001019f8b44bfaae2a57255162)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agowatchdog: cadence: Show used timeout value
Michal Simek [Thu, 19 Apr 2018 13:22:04 +0000 (15:22 +0200)]
watchdog: cadence: Show used timeout value

Debug message was showing timeout value which was passed to start
function but there is a checking if this value can be setup.
The patch is moving this debug printf function below checking.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm64: zynqmp: Reset FPD Watchdog on zcu100
Michal Simek [Thu, 19 Apr 2018 12:41:11 +0000 (14:41 +0200)]
arm64: zynqmp: Reset FPD Watchdog on zcu100

Low level configuration didn't reset FPD Watchdog that's why accessing
it caused u-boot hang.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agonand: zynq: Send address cycles as per onfi parameter page
Siva Durga Prasad Paladugu [Thu, 25 May 2017 06:45:24 +0000 (12:15 +0530)]
nand: zynq: Send address cycles as per onfi parameter page

Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agonand: zynq: Add support for 16-bit buswidth
Siva Durga Prasad Paladugu [Thu, 25 May 2017 08:55:55 +0000 (14:25 +0530)]
nand: zynq: Add support for 16-bit buswidth

This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoMAINTAINERS: zynqmp: Point to proper zynqmp folder
Michal Simek [Wed, 18 Apr 2018 13:00:43 +0000 (15:00 +0200)]
MAINTAINERS: zynqmp: Point to proper zynqmp folder

Point to Zynqmp arm64 cpu folder not to Zynq arm32.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoserial: zynq: Remove header depedency on arm header structure
Michal Simek [Wed, 18 Apr 2018 10:52:48 +0000 (12:52 +0200)]
serial: zynq: Remove header depedency on arm header structure

There is no need to have arm hardware header in this driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agotimer: Add Cadence TTC timer counter support
Michal Simek [Tue, 17 Apr 2018 11:40:46 +0000 (13:40 +0200)]
timer: Add Cadence TTC timer counter support

This driver was tested on Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agomicroblaze: Dont enable UBI support by default
Siva Durga Prasad Paladugu [Wed, 3 Jan 2018 07:45:29 +0000 (13:15 +0530)]
microblaze: Dont enable UBI support by default

This patch removes UBI support from defconfig and it can
be enabled from menuconfig as per need.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm64: zynqmp: Add new defconfig for zc1275 revB
Siva Durga Prasad Paladugu [Wed, 11 Apr 2018 08:43:05 +0000 (14:13 +0530)]
arm64: zynqmp: Add new defconfig for zc1275 revB

This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoscsi: ceva: Convert driver to use UCLASS_AHCI instead of SCSI
Michal Simek [Fri, 6 Apr 2018 11:32:52 +0000 (13:32 +0200)]
scsi: ceva: Convert driver to use UCLASS_AHCI instead of SCSI

In v2018 the patch
"dm: ahci: Correct uclass private data"
(sha1: bfc1c6b4838501d10aa48c0e92eaf70976f4b2dd)
was causing an issue for ceva_sata.
But this issue is not in v2018.05-rc1 but still converting to
UCLASS_AHCI would make more sense.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Remove checkboard and enable DISPLAY_CPUINFO
Michal Simek [Wed, 28 Feb 2018 08:50:07 +0000 (09:50 +0100)]
arm: zynq: Remove checkboard and enable DISPLAY_CPUINFO

Now that showing silicon version is part of the CPU
info display, let's remove checkboard().

Note that the generic show_board_info() will still
show the DT 'model' property. For instance:

U-Boot 2018.05-rc2-00025-g611b3ee0159b (Apr 19 2018 - 11:23:12 +0200)

CPU:   Zynq 7z045
Silicon: v1.0
Model: Zynq ZC706 Development Board
I2C:   ready

Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>,
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

mini configuration doesn't need to show this information.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Rework FPGA initialization
Michal Simek [Wed, 17 Jan 2018 13:56:22 +0000 (10:56 -0300)]
arm: zynq: Rework FPGA initialization

This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.

Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Enable debug_uart_init in spl when enabled
Michal Simek [Thu, 19 Apr 2018 10:36:48 +0000 (12:36 +0200)]
arm: zynq: Enable debug_uart_init in spl when enabled

In past this code was commented and was used for debug purpose.
But there is no reason not to enabled it based on macros.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoMerge git://git.denx.de/u-boot-ubi
Tom Rini [Thu, 10 May 2018 11:17:14 +0000 (07:17 -0400)]
Merge git://git.denx.de/u-boot-ubi

6 years agoMerge git://git.denx.de/u-boot-sunxi
Tom Rini [Wed, 9 May 2018 16:58:06 +0000 (12:58 -0400)]
Merge git://git.denx.de/u-boot-sunxi

6 years agoubifs: avoid assert failed in ubifs.c
Patrice Chotard [Fri, 27 Apr 2018 13:51:23 +0000 (15:51 +0200)]
ubifs: avoid assert failed in ubifs.c

This patch solves assert failed displayed in the console during a boot.
The root cause is that the ubifs_inode is not already allocated when
ubifs_printdir and ubifs_finddir functions are called.

Trace showing the issue:
feed 'boot.scr.uimg', ino 94, new f_pos 0x17b40ece
dent->ch.sqnum '7132', creat_sqnum 3886945402880
UBIFS assert failed in ubifs_finddir at 436
INODE ALLOCATION: creat_sqnum '7129'
Found U-Boot script /boot.scr.uimg

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agobootm.c: Correct the flush_len used in bootm_load_os()
Tom Rini [Tue, 1 May 2018 16:32:37 +0000 (12:32 -0400)]
bootm.c: Correct the flush_len used in bootm_load_os()

In do_bootm_states when doing BOOTM_STATE_LOADOS we use load_end
uninitialized and Coverity notes this now.  This however leads down
another interesting path.  We pass this pointer to bootm_load_os and
that in turn uses this uninitialized value immediately to calculate the
flush length, and is wrong.  We do not know what load_end will be until
after bootm_decomp_image is called, so we must only set flush_len after
that.  All of this also makes it clear that the only reason we pass a
pointer for load_end to bootm_load_os is so that we can call lmb_reserve
on success.  Rather than initialize load_end to 0 in do_bootm_states we
can just call lmb_reserve ourself.

Reported-by: Coverity (CID: 175572)
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoimage: fit: Show signatures and hashes for configurations
Clément Péron [Mon, 30 Apr 2018 09:06:40 +0000 (11:06 +0200)]
image: fit: Show signatures and hashes for configurations

The signature/hash information are displayed for images but nor for
configurations.

Add subnodes printing in fit_conf_print() like it's done in fit_image_print()

Signed-off-by: Clément Péron <peron.clem@gmail.com>
[trini: Add guards around fit_conf_print to avoid warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoarm: bitops: fix find_next_zero_bit() for case size < 32
Grygorii Strashko [Sat, 28 Apr 2018 00:58:49 +0000 (19:58 -0500)]
arm: bitops: fix find_next_zero_bit() for case size < 32

find_next_zero_bit() incorrectly handles cases when:
- total bitmap size < 32
- rest of bits to process

static inline int find_next_zero_bit(void *addr, int size, int offset)
{
unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;

if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
[1]
goto found_first;
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size & ~31UL) {
tmp = *(p++);
if (~tmp)
goto found_middle;
result += 32;
size -= 32;
}
[2]
if (!size)
return result;
tmp = *p;

found_first:
[3]  tmp |= ~0UL >> size;

^^^ algo can reach above line from from points:
 [1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1
 [2] size < 32 - rest of bits to process
 in both cases bits to search are tmp[size-1..0], but line [3] will simply
 set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail.

example: bitmap size = 16, offset = 0, bitmap is empty.
 code will go through the point [2], tmp = 0x0
 after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16.

found_middle:
return result + ffz(tmp);
}

Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3].

Fixes: 81e9fe5a2988 ("arm: implement find_next_zero_bit function")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
6 years agocmd: add ADC cli commands
Neil Armstrong [Fri, 27 Apr 2018 13:17:57 +0000 (15:17 +0200)]
cmd: add ADC cli commands

Add an 'adc' cli command to get information from adc devices and to read
"single shot" data.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agopci: Don't use pci_indirect when DM is active
Mario Six [Fri, 27 Apr 2018 12:53:37 +0000 (14:53 +0200)]
pci: Don't use pci_indirect when DM is active

Declaration of indirect PCI bridges is not compatible with DM: Both
define PCI operations, but in different ways. Hence, don't use indirect
bridges if DM is active.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agogdsys: drivers: Add gdsys_rxaui_ctrl driver
Mario Six [Fri, 27 Apr 2018 12:53:33 +0000 (14:53 +0200)]
gdsys: drivers: Add gdsys_rxaui_ctrl driver

Add a driver for RXAUI control on IHS FPGAs.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoclk: Add ICS8N3QV01 driver
Mario Six [Fri, 27 Apr 2018 12:53:15 +0000 (14:53 +0200)]
clk: Add ICS8N3QV01 driver

Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agoihs_mdio: Make DM-compatible
Mario Six [Fri, 27 Apr 2018 12:52:10 +0000 (14:52 +0200)]
ihs_mdio: Make DM-compatible

Make the ihs_mdio driver DM-compatible, while retaining the old
functionality for not-yet-converted boards.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agoihs_mdio: Encapsulate register access
Mario Six [Fri, 27 Apr 2018 12:52:09 +0000 (14:52 +0200)]
ihs_mdio: Encapsulate register access

To prepare for DM conversion, encapsulate all register accesses in
function calls.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agodb410c: set clk node to be probed before relocation
Ramon Fried [Fri, 20 Apr 2018 19:39:50 +0000 (22:39 +0300)]
db410c: set clk node to be probed before relocation

The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that the msm-serial driver can actually
use the clock node.

Signed-off-by: Ramon Fried <ramon.fried@linaro.org>
6 years agoARM: dts: sti: Add stih410-b2260-u-boot.dtsi
Patrice Chotard [Fri, 20 Apr 2018 07:53:55 +0000 (09:53 +0200)]
ARM: dts: sti: Add stih410-b2260-u-boot.dtsi

STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs.
As currently no U-boot driver is available for the USB3 PHY and to avoid
issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY
using stih410-b2260-u-boot.dtsi file.

Fixes: 2fd4242cc50e ("ubs: xhci-dwc3: Enable USB3 PHY when available")

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoarm: ti: boot: Extract PARTS_DEFAULT to boot.h
Sam Protsenko [Thu, 19 Apr 2018 20:57:30 +0000 (23:57 +0300)]
arm: ti: boot: Extract PARTS_DEFAULT to boot.h

Eliminate code duplication: the same PARTS_DEFAULT was defined in
am57xx_evm.h and in dra7xx_evm.h. Extract it to environment/boot.h and
use in all OMAP5-based boards.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
6 years agoMerge git://git.denx.de/u-boot-mmc
Tom Rini [Tue, 8 May 2018 17:47:39 +0000 (13:47 -0400)]
Merge git://git.denx.de/u-boot-mmc

6 years agoMerge git://git.denx.de/u-boot-uniphier
Tom Rini [Tue, 8 May 2018 17:47:26 +0000 (13:47 -0400)]
Merge git://git.denx.de/u-boot-uniphier

6 years agolib/Kconfig: Mark OF_LIBFDT_OVERLAY as depending on OF_LIBFDT
Tom Rini [Tue, 8 May 2018 12:52:17 +0000 (08:52 -0400)]
lib/Kconfig: Mark OF_LIBFDT_OVERLAY as depending on OF_LIBFDT

The overlay code is only useful when OF_LIBFDT is set, so mark it as
depending on that first.

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoadc: add Amlogic Meson SAR ADC driver
Neil Armstrong [Mon, 23 Apr 2018 14:19:23 +0000 (16:19 +0200)]
adc: add Amlogic Meson SAR ADC driver

This patch adds the driver for the Amlogic Meson Successive Approximation
Register (SAR) A/D Converter based on the Linux IIO driver thanks to the
great work of Martin Blumenstingl.
The driver has been adapted to U-Boot and the ADC UClass.

This patch depends on the regmap "regmap: add regmap_update_bits() helper"
patch and has been tested using the newly introducted "adc" CLI command
in the "cmd: add ADC cli commands" patch.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agotest: regmap: add read/modify/write test
Neil Armstrong [Fri, 27 Apr 2018 09:56:15 +0000 (11:56 +0200)]
test: regmap: add read/modify/write test

Add calls to regmap_read/modify_bits/write even if the proper memory
read/write calls are not executed in sandbox.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoregmap: add regmap_update_bits() helper
Neil Armstrong [Fri, 27 Apr 2018 09:56:14 +0000 (11:56 +0200)]
regmap: add regmap_update_bits() helper

Add the regmap_update_bits() to simply the read/modify/write of registers
in a single command. The function is taken from Linux regmap
implementation.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoARM: dts: stm32mp157: Add vrefbuf DT node
Patrice Chotard [Thu, 26 Apr 2018 15:00:49 +0000 (17:00 +0200)]
ARM: dts: stm32mp157: Add vrefbuf DT node

Add vrefbuf device tree node. This allows to get
a voltage reference for ADCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoconfigs: stm32mp15: Enable STM32_VREFBUF flag
Fabrice Gasnier [Thu, 26 Apr 2018 15:00:48 +0000 (17:00 +0200)]
configs: stm32mp15: Enable STM32_VREFBUF flag

Enable vrefbuf on stm32mp15, to be used by ADC.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoclk: stm32mp1: Add VREF clock gating
Fabrice Gasnier [Thu, 26 Apr 2018 15:00:47 +0000 (17:00 +0200)]
clk: stm32mp1: Add VREF clock gating

Add VREF clock gating, that may be used by STM32 VREFBUF regulator.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agopower: regulator: Add support for stm32-vrefbuf
Fabrice Gasnier [Thu, 26 Apr 2018 15:00:46 +0000 (17:00 +0200)]
power: regulator: Add support for stm32-vrefbuf

Add regulator driver for STM32 voltage reference buffer which can be
used as voltage reference for ADCs, DACs and external components through
dedicated VREF+ pin.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoconfigs: stm32mp15_basic: Set regulator relative flags
Patrice Chotard [Thu, 26 Apr 2018 15:13:12 +0000 (17:13 +0200)]
configs: stm32mp15_basic: Set regulator relative flags

Enable DM_REGULATOR_STPMU1 flag to activate regulator
driver for STM32MP15 SoC and CMD_REGULATOR flag to be
able to set/get regulator state int U-boot command line.

Disable PMIC_CHILDREN as this flag is not needed in SPL
for STM32MP1.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoARM: dts: stm32mp157c-ed1: Add regulator node
Patrice Chotard [Thu, 26 Apr 2018 15:13:11 +0000 (17:13 +0200)]
ARM: dts: stm32mp157c-ed1: Add regulator node

Add regulator nodes needed by stpmu1 regulator driver
Add vmmc-supply and vqmmc-supply regulator property for
sdmmc1 and sdmmc2.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agopower: pmic: stpmu1: Add regulator bindings
Patrice Chotard [Thu, 26 Apr 2018 15:13:10 +0000 (17:13 +0200)]
power: pmic: stpmu1: Add regulator bindings

Add regulator bindings to get access to regulator managed
by drivers/power/regulator/stpmu1.c regulator driver.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agopower: regulator: stpmu1: Introduce stpmu1 driver
Christophe Kerello [Thu, 26 Apr 2018 15:13:09 +0000 (17:13 +0200)]
power: regulator: stpmu1: Introduce stpmu1 driver

Enable support for the regulator functions of the STPMU1X PMIC. The
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoARM: dts: stm32mp157: Add SoC pwr regulator entry
Patrice Chotard [Thu, 26 Apr 2018 14:45:19 +0000 (16:45 +0200)]
ARM: dts: stm32mp157: Add SoC pwr regulator entry

Add SoC power regulator entry for reg11, reg18 and usb33
regulator.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agostm32mp: regulator: add SoC pwr regulator support
Patrick Delaunay [Thu, 26 Apr 2018 14:45:18 +0000 (16:45 +0200)]
stm32mp: regulator: add SoC pwr regulator support

This driver binds and manages the following regulator of
SoC's PWR block :
  - reg11
  - reg18
  - usb33

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoarm: controlcenterdc: Add spi-flash compatible strings
Mario Six [Thu, 26 Apr 2018 08:10:59 +0000 (10:10 +0200)]
arm: controlcenterdc: Add spi-flash compatible strings

Since kirkwook SPI was recently converted to DM, add compatible strings
to the SPI flash devices to make them work with the new driver.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agoenv: ti: android: boot with FIT Image
Praneeth Bajjuri [Wed, 25 Apr 2018 21:03:24 +0000 (16:03 -0500)]
env: ti: android: boot with FIT Image

Boot android over emmc by default thru FIT image

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Suggested-by: Andrew F.Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
6 years agoconfigs: TI: Enable FIT Library overlay support
Praneeth Bajjuri [Wed, 25 Apr 2018 21:03:23 +0000 (16:03 -0500)]
configs: TI: Enable FIT Library overlay support

Enable the FDT library overlay support for all TI SOC family.

Without this option, when Loading fdt from FIT image, the
following warning is seen.

"config with overlays but CONFIG_OF_LIBFDT_OVERLAY not set".

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Suggested-by: Andrew F.Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
6 years agoarm: dra76: fastboot: extend cpu type for getvar command
Praneeth Bajjuri [Wed, 25 Apr 2018 20:56:34 +0000 (15:56 -0500)]
arm: dra76: fastboot: extend cpu type for getvar command

'commit dda0bd674481 ("arm: dra762: Add support for device package identification")'
introduces ABZ and ACD package identification.

This patch is to extend usage of "fastboot getvar cpu" for
DRA76x ABZ and ACD devices.

Helps in fixing the boot warning.

Warning: fastboot.cpu: unknown CPU rev: 123863298
on
CPU  : DRA762-GP ES1.0 ABZ package
Model: TI AM5748 IDK
Board: AM574x IDK REV 1.0A

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agodefconfig: at91-sama5d2_ptc_ek: remove unused SYS_EXTRA_OPTIONS
Ludovic Desroches [Wed, 25 Apr 2018 09:22:41 +0000 (12:22 +0300)]
defconfig: at91-sama5d2_ptc_ek: remove unused SYS_EXTRA_OPTIONS

Remove SYS_USE_NANDFLASH, SYS_USE_MMC as they are deprecated and
unused.
The board configurations already use CONFIG_SD_BOOT and
CONFIG_NAND_BOOT respectively.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[eugen.hristev@microchip.com: rework on latest u-boot]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
6 years agoboard: sama5d27_som1_ek: Fix the USB vbus power
Eugen Hristev [Tue, 24 Apr 2018 11:36:28 +0000 (14:36 +0300)]
board: sama5d27_som1_ek: Fix the USB vbus power

According to the REVB schematic, fix the USB vbus power enable pin.

Based on original work by Wenyou Yang

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
6 years agoconfigs: at91: sama5: updated mtdparts variable in bootargs
Eugen Hristev [Tue, 24 Apr 2018 09:00:16 +0000 (12:00 +0300)]
configs: at91: sama5: updated mtdparts variable in bootargs

We have a new demo layout of our sama5 boards for the NAND Flash
memory.
According to this new layout, adjust the mtdparts variable in bootargs
to align with this, which is available at :
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d3XplainedMainPage#NAND_Flash_demo_Memory_map,

Based on original work by Wenyou Yang

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
6 years agoboard: sama5d2_ptc_ek: adjust the smc timings of nand
Eugen Hristev [Tue, 24 Apr 2018 07:43:53 +0000 (10:43 +0300)]
board: sama5d2_ptc_ek: adjust the smc timings of nand

To fix the issue of write the rootfs.ubi, adjust the smc timings
configuration of the nand controller.

Based on original work by Wenyou Yang

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
6 years agogpio: atmel_pio4: give a full configuration when muxing pins
Ludovic Desroches [Tue, 24 Apr 2018 07:16:01 +0000 (10:16 +0300)]
gpio: atmel_pio4: give a full configuration when muxing pins

When a pin is muxed to a peripheral or as a GPIO, the only
configuration that can be set is the pullup. It is too restrictive
so this patch allows to give a full configuration.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
6 years agoboard: atmel: sama5d2_ptc_ek: update pin configuration for NAND
Ludovic Desroches [Mon, 23 Apr 2018 07:59:50 +0000 (10:59 +0300)]
board: atmel: sama5d2_ptc_ek: update pin configuration for NAND

The drive strength has to be set to medium for the NAND data lines.
With a low drive, we can get some data corruption.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
6 years agogpio: atmel_pio4: add drive strength macros
Ludovic Desroches [Mon, 23 Apr 2018 07:59:49 +0000 (10:59 +0300)]
gpio: atmel_pio4: add drive strength macros

Macros for drive strength configuration were missing.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
6 years agopci: intel: Add Intel FPGA PCIe controller driver
Ley Foon Tan [Fri, 20 Apr 2018 13:55:45 +0000 (21:55 +0800)]
pci: intel: Add Intel FPGA PCIe controller driver

Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in
rootport mode only, the EP mode is not supported. The driver is tested
with the Intel e1000e NIC driver.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
6 years agoarm64: Add SMC and HVC commands
Michalis Pappas [Fri, 13 Apr 2018 07:40:57 +0000 (10:40 +0300)]
arm64: Add SMC and HVC commands

This patch adds smc and hvc commands, that allow issuing Secure Monitor
Calls and Hypervisor Calls conforming to the ARM SMC Calling Convention.

Add Kconfig items to allow each command can be individually enabled.

Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agopinctrl: meson: Update pinmux with new Linux bindings
Neil Armstrong [Wed, 11 Apr 2018 15:40:41 +0000 (17:40 +0200)]
pinctrl: meson: Update pinmux with new Linux bindings

The pinctrl bindings has changed for Amlogic Meson SoCs since Linux 4.13,
update the pinctrl driver to take this in account.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agoARM64: meson: Sync DT and Bindings with Linux 4.16
Neil Armstrong [Wed, 11 Apr 2018 15:40:40 +0000 (17:40 +0200)]
ARM64: meson: Sync DT and Bindings with Linux 4.16

Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.16.0.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agoARM: meson: rename GXBB to GX
Neil Armstrong [Wed, 11 Apr 2018 15:13:45 +0000 (17:13 +0200)]
ARM: meson: rename GXBB to GX

Taking into account the Amlogic Family name starts with GX, including
the GXBB, GXL and GXM SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agoclk: clk_stm32f: Use PLLSAIP as USB 48MHz clock
Patrice Chotard [Wed, 11 Apr 2018 15:07:45 +0000 (17:07 +0200)]
clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock

On all STM32F4 and F7 SoCs  family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>

6 years agodm: led: add testcase for "default-state" property
Patrick Bruenn [Wed, 11 Apr 2018 09:16:29 +0000 (11:16 +0200)]
dm: led: add testcase for "default-state" property

Add two more gpio-leds to sandbox test device tree with default-state
property set to "on"/"off".
Add dm_test_led_default_state() to check that these new LED's are set to
LEDST_ON and LEDST_OFF.

dm: led: add testcase for "default-state" property

Add two more gpio-leds to sandbox test device tree with default-state
property set to "on"/"off".
Add dm_test_led_default_state() to check that these new LED's are set to
LEDST_ON and LEDST_OFF.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
6 years agodm: led: auto probe() LEDs with "default-state"
Patrick Bruenn [Wed, 11 Apr 2018 09:16:28 +0000 (11:16 +0200)]
dm: led: auto probe() LEDs with "default-state"

To avoid board specificy LED activation code, automatically
activate gpio-leds with "default-state" property during bind().

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
6 years agodm: led: Support "default-state" property
Patrick Bruenn [Wed, 11 Apr 2018 09:16:27 +0000 (11:16 +0200)]
dm: led: Support "default-state" property

Add support for the device tree property "default-state". This feature
might be useful for LEDs indicating "power on" or similar states.

Note: Even with this commit gpio-leds remain in reset state. That's
because the led_gpio is not probed until DM_FLAG_ACTIVATED is set.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
6 years agommc: support writing sparse images
Jassi Brar [Fri, 6 Apr 2018 06:35:24 +0000 (12:05 +0530)]
mmc: support writing sparse images

Provide an alternate path for sparse-images to be
written to MMC. For example, via tftp on platforms
that don't support fastboot protocol. Or when an
image is to written at some offset, rather than the
start of a partition.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
[trini: Guard with CONFIG_FASTBOOT_FLASH tests, use LBAF for lbaint_t
        printing]
Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agopower: pwm regulator: support live tree
Andy Yan [Tue, 27 Mar 2018 11:39:38 +0000 (19:39 +0800)]
power: pwm regulator: support live tree

Use live tree compatible api for pwm regulator.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
6 years agodm: mmc: socfpga: call dwmci_probe()
Patrick Bruenn [Tue, 6 Mar 2018 08:07:23 +0000 (09:07 +0100)]
dm: mmc: socfpga: call dwmci_probe()

On a socfpga_cyclone5 based board the SD card, was never powered up. For
other dw_mmc based SoCs dwmci_probe() is called in the platform specific
probe(). It seems this call is missing for socfpga_dw_mmc.

With this change DWMCI_PWREN is set by dmwci_init().

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
6 years agommc: Kconfig: add the MMC_TRACE config in Kconfig
Jaehoon Chung [Fri, 26 Jan 2018 10:25:31 +0000 (19:25 +0900)]
mmc: Kconfig: add the MMC_TRACE config in Kconfig

Add the MMC_TRACE config in Kconfig.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
6 years agommc: add the debug message in mmc_set_clock
Jaehoon Chung [Fri, 26 Jan 2018 10:25:30 +0000 (19:25 +0900)]
mmc: add the debug message in mmc_set_clock

Add the debug message for checking the mmc clock status.
It's helpful to debug the controlling clock.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
6 years agommc: add the MMC_CLK_ENABLE/DISABLE macro in mmc.h
Jaehoon Chung [Fri, 26 Jan 2018 10:25:29 +0000 (19:25 +0900)]
mmc: add the MMC_CLK_ENABLE/DISABLE macro in mmc.h

mmc_set_clock() function has the disable argument as bool type.
When mmc_set_clock is called, it might be passed to "true" or "false".
But it's too confusion whether clock is enabled or disabled with only
"true" and "false".
To prevent the confusion, replace to MMC_CLK_ENABLE/DISABLE macro from
true/false.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
6 years agolib: fdtdec: drop the old compatible about max77686
Jaehoon Chung [Thu, 25 Jan 2018 07:11:03 +0000 (16:11 +0900)]
lib: fdtdec: drop the old compatible about max77686

Drop the old compatible about max77686.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
6 years agopower: pmic_max77686: remove the old pmic_max77686 file
Jaehoon Chung [Thu, 25 Jan 2018 07:11:02 +0000 (16:11 +0900)]
power: pmic_max77686: remove the old pmic_max77686 file

max77686 pmic is supporting with max77686.c under pmic/ and regulator/
direnctroy. Remove pmic_max77686.c what didn't use anywhere.
Instead, enable CONFIG_DM_REGULATOR_MAX77686 and
CONFIG_DM_PMIC_MAX77686.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
6 years agoconfigs: trats2: enable the max77686 regulator config
Jaehoon Chung [Thu, 25 Jan 2018 07:11:01 +0000 (16:11 +0900)]
configs: trats2: enable the max77686 regulator config

Enable the CONFIG_DM_REGULATOR_MAX77686 for using regulator driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
6 years agoARM: uniphier: enable CONFIG_PINCONF
Masahiro Yamada [Sat, 5 May 2018 10:53:57 +0000 (19:53 +0900)]
ARM: uniphier: enable CONFIG_PINCONF

Enable the pin configuration feature for UniPhier 64 bit SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agopinctrl: uniphier: add ethernet TX pin data for LD20
Masahiro Yamada [Sat, 5 May 2018 10:53:56 +0000 (19:53 +0900)]
pinctrl: uniphier: add ethernet TX pin data for LD20

These are necessary to optimize the drive-strength of the pins.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agopinctrl: uniphier: support drive-strength configuration
Masahiro Yamada [Sat, 5 May 2018 10:53:55 +0000 (19:53 +0900)]
pinctrl: uniphier: support drive-strength configuration

This allows our DT to specify drive-strength property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agopinctrl: uniphier: support per-pin configuration via DT
Masahiro Yamada [Sat, 5 May 2018 10:53:54 +0000 (19:53 +0900)]
pinctrl: uniphier: support per-pin configuration via DT

Currently, the UniPhier pinctrl drivers expose only the pin-group
interface to device tree.

Provide .get_pins_count, .get_pin_name, .pinconf_set hooks to support
pin configuration via 'pins' DT property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agopinctrl: uniphier: include <linux/build_bug.h> instead of <linux/bug.h>
Masahiro Yamada [Sat, 5 May 2018 10:53:53 +0000 (19:53 +0900)]
pinctrl: uniphier: include <linux/build_bug.h> instead of <linux/bug.h>

The #include <linux/bug.h> is here to use BUILD_BUG_ON_ZERO().

By replacing it with <linux/build_bug.h>, we can reduce the number of
headers pulled in.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agopinctrl: uniphier: replace printf() with dev_err()
Masahiro Yamada [Sat, 5 May 2018 10:53:52 +0000 (19:53 +0900)]
pinctrl: uniphier: replace printf() with dev_err()

dev_err() is more suitable for printing error messages.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agopinctrl: uniphier: remove unneeded pin data of LD6b SoC
Masahiro Yamada [Sat, 5 May 2018 10:53:51 +0000 (19:53 +0900)]
pinctrl: uniphier: remove unneeded pin data of LD6b SoC

Since commit f73cfb4d0dee ("pinctrl: uniphier: simplify input enable
and delete pin arrays"), these data are no longer used in any useful
way.  Remove.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agofastboot: sparse: make write_sparse_image useable for non-fastboot
Jassi Brar [Fri, 6 Apr 2018 06:35:09 +0000 (12:05 +0530)]
fastboot: sparse: make write_sparse_image useable for non-fastboot

write_sparse_image could be useful for non-fastboot users.
For ex a platform, without usb-device/fastboot support, could
get sparse images over tftp and write using the mmc command.
Or non-android systems could also leverage the sparse format.

Towards that, this patch removes anything fastboot specific from
the write_sparse_image implementation. Which includes making the
function return integer as error code and calls for fastboot logging
via an optional callback function 'mssg'.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
6 years agofastboot: sparse: remove redundant argument to write_sparse_image
Jassi Brar [Fri, 6 Apr 2018 06:34:52 +0000 (12:04 +0530)]
fastboot: sparse: remove redundant argument to write_sparse_image

'sz' has no use for write_sparse_image, remove it simplifying the api.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
6 years agoarm: v7R: Add support for enabling caches
Lokesh Vutla [Thu, 26 Apr 2018 12:51:31 +0000 (18:21 +0530)]
arm: v7R: Add support for enabling caches

Cache maintenance procedure is same for v7A and v7R
processors. So re-use cache-cp15.c file except for
mmu parts.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agoarm: v7R: Add support for MPU
Lokesh Vutla [Thu, 26 Apr 2018 12:51:30 +0000 (18:21 +0530)]
arm: v7R: Add support for MPU

The Memory Protection Unit(MPU) allows to partition memory into regions
and set individual protection attributes for each region. In absence
of MPU a default map[1] will take effect. Add support for configuring
MPU on Cortex-R, by reusing the existing support for Cortex-M processor.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html

Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agoarm: v7R: Add initial support
Michal Simek [Thu, 26 Apr 2018 12:51:29 +0000 (18:21 +0530)]
arm: v7R: Add initial support

The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded,
real-time systems. It implements the ARMv7-R architecture, and includes
Thumb-2 technology for optimum code density and processing throughput.

Except for MPU(Memory Protection Unit) and few CP15 registers, most of the
features are compatible with v7 architecture. So,reuse the same armv7
folder and introduce a new config CPU_V7R in order to differentiate
from v7 based platforms.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoarm: v7: Kconfig: Introduce SYS_ARM_CACHE_CP15
Lokesh Vutla [Thu, 26 Apr 2018 12:51:28 +0000 (18:21 +0530)]
arm: v7: Kconfig: Introduce SYS_ARM_CACHE_CP15

Certain ARM architectures like ARMv7-A, ARMv7-R has support for
enabling caches using CP15 registers. To have a common support
for all these architectures, introduce a Kconfig symbol
SYS_ARM_CACHE_CP15 that selects cache-cp15.c

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>