oweals/u-boot.git
5 years agoARM: dts: stm32: Synchronize DT with kernel one
Patrice Chotard [Tue, 12 Feb 2019 15:50:38 +0000 (16:50 +0100)]
ARM: dts: stm32: Synchronize DT with kernel one

This patch synchronizes U-boot DT with kernel one
This is based on https://patchwork.kernel.org/cover/10797115/

This patch adds initial support of STM32MP157 discovery boards:
  - Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1).
    This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios)
    and 512MB of DDR3. Several connections are available on this boards:
    4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ...

  - Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2).
    This board is a "super-set" of stm32mp157a-dk1. A display panel (otm8009a)
    and Murata wifi/BT combo is added.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
5 years agostpmic1: add NVM update support in fuse command
Patrick Delaunay [Mon, 4 Feb 2019 10:26:22 +0000 (11:26 +0100)]
stpmic1: add NVM update support in fuse command

Add functions to read/update the non volatile memory of STPMIC1
(8 bytes-register at 0xF8 address) and allow access
with fuse command (bank=1, word > 0xF8).

For example:

STM32MP> fuse read 1 0xf8 8
Reading bank 1:

Word 0x000000f8: 000000ee 00000092 000000c0 00000002
Word 0x000000fc: 000000f2 00000080 00000002 00000033

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: dts: activate psci-1.0
Patrick Delaunay [Mon, 4 Feb 2019 10:26:21 +0000 (11:26 +0100)]
stm32mp1: dts: activate psci-1.0

Updates the stm32mp157c devicetree to bind the U-Boot PSCI driver need for
power off command; TF-A for stm32mp15x supports PSCI 1.0.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: add command poweroff
Patrick Delaunay [Fri, 12 Apr 2019 09:55:46 +0000 (11:55 +0200)]
stm32mp1: add command poweroff

Activate the command poweroff by default for STM32MP1:
- with PCSI from TF-A for trusted boot
- with PMIC sysreset request for basic boot (SYSRESET_POWER)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agopmic: stpmu1: add power switch off support
Patrick Delaunay [Mon, 4 Feb 2019 10:26:19 +0000 (11:26 +0100)]
pmic: stpmu1: add power switch off support

Add sysreset support, and support power switch off request,
needed by poweroff command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostpmic1: update register names
Patrick Delaunay [Mon, 4 Feb 2019 10:26:18 +0000 (11:26 +0100)]
stpmic1: update register names

Alignment with  STPMIC1 datasheet
  s/MAIN_CONTROL_REG/MAIN_CR/g
  s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
  s/MASK_RESET_LDOS/LDOS_MRST_CR/g
  s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
  s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
  s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
  s/USB_CTRL_REG/BST_SW_CR/g
  s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
  s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agopower: rename stpmu1 to official name stpmic1
Patrick Delaunay [Mon, 4 Feb 2019 10:26:17 +0000 (11:26 +0100)]
power: rename stpmu1 to official name stpmic1

Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
5 years agopower: stpmu1: rename files to stpmic1
Patrick Delaunay [Mon, 4 Feb 2019 10:26:16 +0000 (11:26 +0100)]
power: stpmu1: rename files to stpmic1

Prepare file modification for kernel alignment and
rename driver to stpmic1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
5 years agoregulator: stpmu1: update buck1 range
Patrick Delaunay [Mon, 4 Feb 2019 10:26:15 +0000 (11:26 +0100)]
regulator: stpmu1: update buck1 range

SW impact for Rev 1.2 of STPMIC1 in U-Boot:
Buck converters output voltage change for Buck1
=> Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V
   (see STPMIC1 datasheet / chapter 5.3 Buck converters)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: Replace OTP read by SHADOW read
Patrick Delaunay [Wed, 27 Feb 2019 16:01:29 +0000 (17:01 +0100)]
stm32mp1: Replace OTP read by SHADOW read

Replace STM32_BSEC_OTP() by STM32_BSEC_SHADOW() to
increase read performance.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: bsec: shadow all the upper OTP (no secure) during boot
Patrick Delaunay [Wed, 27 Feb 2019 16:01:28 +0000 (17:01 +0100)]
stm32mp1: bsec: shadow all the upper OTP (no secure) during boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: bsec: use device tree new compatible
Patrick Delaunay [Wed, 27 Feb 2019 16:01:27 +0000 (17:01 +0100)]
stm32mp1: bsec: use device tree new compatible

Update bsec driver to use the device tree provided by Kernel.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: basic boot: SPL enable access to GPIOZ bank
Patrick Delaunay [Wed, 27 Feb 2019 16:01:26 +0000 (17:01 +0100)]
stm32mp1: basic boot: SPL enable access to GPIOZ bank

SPL need to set GPIOZ_SECCFGR = 0 to enable access to GPIOZ bank
(open security).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: align serial number on bootrom
Patrick Delaunay [Wed, 27 Feb 2019 16:01:25 +0000 (17:01 +0100)]
stm32mp1: align serial number on bootrom

Always use upper case for serial number.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: add syscfg initialization
Patrick Delaunay [Wed, 27 Feb 2019 16:01:24 +0000 (17:01 +0100)]
stm32mp1: add syscfg initialization

Initialize the system configuration for basic boot
- update interconnect setting
- disable pull-down for boot pin
- enable High Speed Low Voltage Pad mode for SPI, SDMMC, ETH, QSPI
- activate I/O compensation

Done by SSBL = TF-A for trusted boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: add some syscon drivers for syscfg and etpzc
Patrick Delaunay [Wed, 27 Feb 2019 16:01:23 +0000 (17:01 +0100)]
stm32mp1: add some syscon drivers for syscfg and etpzc

Add SYSCON driver for syscfg and etpzc and reorder in alphabetics order

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: activated some configuration
Patrick Delaunay [Wed, 27 Feb 2019 16:01:22 +0000 (17:01 +0100)]
stm32mp1: activated some configuration

Add configuration useful for test
- FIT support
- MEMTEST
- DFU
- CACHE
- TIME
- TIMER

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: update memory layout
Patrick Delaunay [Wed, 27 Feb 2019 16:01:21 +0000 (17:01 +0100)]
stm32mp1: update memory layout

Update the memory layout to be aligned with other platform and avoid
overlap with 32MB Linux kernel (multiv7 image).
+ Kernel => 32MiB offset = 0xC2000000
            and increase the bootm size to 32MiB
+ FDT => 64MiB offset = 0xc4000000
+ SCRIPT => 65Mib offset = 0xc4100000
+ PXESCRIPT => 66Mib offset = 0xc4200000
+ SPLASHIMAGE => 67Mib offset = 0xc4300000
+ RAMDISK => 68Mib offset = 0xc4400000
             (not limited size)

In sources/boot/u-boot/doc/README.distro

+ kernel_addr_r: A size of 16MB for the kernel is likely adequate.
+ pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate.
+ fdt_addr_r: A size of 1MB for the FDT/DTB seems reasonable.
+ ramdisk_addr_r: It is recommended that this location be highest in RAM
                  out of fdt_addr_, kernel_addr_r, and ramdisk_addr_r,
                  so that the RAM disk can vary in size and use any
                 available RAM.
+ pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate.
+ scriptaddr: A size of 1MB for extlinux.conf is more than adequate.

For suggestions on memory locations for ARM systems, you must follow
the guidelines specified in Documentation/arm/Booting
in the Linux kernel tree.

And in sources/linux-stm32mp/Documentation/arm/Booting

The zImage may also be placed in system RAM and called there.  The
kernel should be placed in the first 128MiB of RAM.  It is recommended
that it is loaded above 32MiB in order to avoid the need to relocate
prior to decompression, which will make the boot process slightly
faster.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: support forced boot mode
Patrick Delaunay [Wed, 27 Feb 2019 16:01:20 +0000 (17:01 +0100)]
stm32mp1: support forced boot mode

The boot mode can be forced by key press
or by TAMP register, requested in kernel by syscon-reboot-mode

tamp: tamp@5c00a000 {
compatible = "simple-bus", "syscon", "simple-mfd";
reg = <0x5c00a000 0x400>;

reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x150>; /* reg20 */
mask = <0xff>;
mode-normal = <0>;
mode-fastboot = <0x1>;
mode-recovery = <0x2>;
mode-stm32cubeprogrammer = <0x3>;
mode-ums_mmc0 = <0x10>;
mode-ums_mmc1 = <0x11>;
mode-ums_mmc2 = <0x12>;
};
};

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: activate FASTBOOT on eMMC
Patrick Delaunay [Wed, 27 Feb 2019 16:01:19 +0000 (17:01 +0100)]
stm32mp1: activate FASTBOOT on eMMC

activate Fastboot for eMMC on EV1 board (mmc1)

$> sudo apt-get install android-tools-adb android-tools-fastboot
$> fastboot -i 0x0483 getvar bootloader-version

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: update bootcmd
Patrick Delaunay [Wed, 27 Feb 2019 16:01:18 +0000 (17:01 +0100)]
stm32mp1: update bootcmd

Clearly separate bootcmd for stm32mp1 board
(bootcmd_stm32mp) and preboot management.
That solve issue for fastboot continue command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: spl: hang with trace when DDR init failed
Patrick Delaunay [Wed, 27 Feb 2019 16:01:17 +0000 (17:01 +0100)]
stm32mp1: spl: hang with trace when DDR init failed

When DDR initialization failed, print error message
and stop the SPL execution.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: cosmetic: add comment on psci_migrate_info_type return value
Patrick Delaunay [Wed, 27 Feb 2019 16:01:16 +0000 (17:01 +0100)]
stm32mp1: cosmetic: add comment on psci_migrate_info_type return value

Add explaination for the return value of psci_migrate_info_type:
  2 = Trusted OS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: cosmetic cleanup Kconfig
Patrick Delaunay [Wed, 27 Feb 2019 16:01:15 +0000 (17:01 +0100)]
stm32mp1: cosmetic cleanup Kconfig

Cosmetic cleanup in mach-stm32mp Kconfig
- remove duplicated SPL_DRIVERS_MISC_SUPPORT
- update help for TARGET_STM32MP1
- set value for NR_DRAM_BANKS
- remove one comment as DEBUG_UART is deactivated by default
- include board Kconfig at the end of the file

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: spl: add spl_display_print
Patrick Delaunay [Wed, 27 Feb 2019 16:01:14 +0000 (17:01 +0100)]
stm32mp1: spl: add spl_display_print

SPL displays the board model from device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: update print_cpuinfo()
Patrick Delaunay [Wed, 27 Feb 2019 16:01:13 +0000 (17:01 +0100)]
stm32mp1: update print_cpuinfo()

Display CPU part number and package information.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: update boot mode management
Patrick Delaunay [Wed, 27 Feb 2019 16:01:12 +0000 (17:01 +0100)]
stm32mp1: update boot mode management

- export the function get_bootmode() and reused it in spl code
- manage uart instance by alias (prepare v4.19 binding)
- solve issue on nand instance
- restore console for uart boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: add runtime information in environment
Patrick Delaunay [Wed, 27 Feb 2019 16:01:11 +0000 (17:01 +0100)]
stm32mp1: add runtime information in environment

Set board name with the first dts compatible found in DT
code under CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

The result with DEVICE_TREE=stm32mp157c-ev1 is:
    STM32MP> env print
     board=stm32mp1
     board_name=stm32mp157c-ev1

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: display board information
Patrick Delaunay [Tue, 12 Feb 2019 10:44:41 +0000 (11:44 +0100)]
stm32mp1: display board information

Implement checkboard() function to display
- the boot chain used: basic or trusted
- the board compatible in device tree
- the board identifier and revision, saved in OTP59 for ST boards

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: bsec: access with SMC for trusted boot
Patrick Delaunay [Tue, 12 Feb 2019 10:44:40 +0000 (11:44 +0100)]
stm32mp1: bsec: access with SMC for trusted boot

As BSEC is secure aware, all register access need to be done
by TF-A for TRUSTED boot chain, when U-Boot is executed in
normal world.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: add trusted boot with TF-A
Patrick Delaunay [Tue, 12 Feb 2019 10:44:39 +0000 (11:44 +0100)]
stm32mp1: add trusted boot with TF-A

Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
  BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32

The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power

The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoMerge branch '2019-04-09-master-imports-fs'
Tom Rini [Wed, 10 Apr 2019 12:18:18 +0000 (08:18 -0400)]
Merge branch '2019-04-09-master-imports-fs'

- test.py tests for mmc
- ext4 symlink support and other fixes
- ext4 block group descriptor sizing

5 years agotest.py: Disable fsck for FAT tests for now
Tom Rini [Tue, 9 Apr 2019 20:08:52 +0000 (16:08 -0400)]
test.py: Disable fsck for FAT tests for now

Currently enabling fsck on FAT16/FAT32 exposes that we have problems
with:
TestFsBasic.test_fs13[fat16]
TestFsBasic.test_fs11[fat32]
TestFsBasic.test_fs12[fat32]
TestFsBasic.test_fs13[fat32]
TestFsExt.test_fs_ext1[fat32]
TestFsExt.test_fs_ext2[fat32]
TestFsExt.test_fs_ext3[fat32]
TestFsExt.test_fs_ext4[fat32]
TestFsExt.test_fs_ext5[fat32]
TestFsExt.test_fs_ext6[fat32]
TestFsExt.test_fs_ext7[fat32]
TestFsExt.test_fs_ext8[fat32]
TestFsExt.test_fs_ext9[fat32]
TestMkdir.test_mkdir6[fat16]
TestMkdir.test_mkdir1[fat32]
TestMkdir.test_mkdir2[fat32]
TestMkdir.test_mkdir3[fat32]
TestMkdir.test_mkdir4[fat32]
TestMkdir.test_mkdir5[fat32]
TestMkdir.test_mkdir6[fat32]
TestUnlink.test_unlink1[fat16]
TestUnlink.test_unlink2[fat16]
TestUnlink.test_unlink3[fat16]
TestUnlink.test_unlink4[fat16]
TestUnlink.test_unlink5[fat16]
TestUnlink.test_unlink6[fat16]
TestUnlink.test_unlink7[fat16]
TestUnlink.test_unlink1[fat32]
TestUnlink.test_unlink2[fat32]
TestUnlink.test_unlink3[fat32]
TestUnlink.test_unlink4[fat32]
TestUnlink.test_unlink5[fat32]
TestUnlink.test_unlink6[fat32]
TestUnlink.test_unlink7[fat32]

This is because we don't update the "information sector" on FAT32.
While in the future we should resolve this problem and include that
feature, we should enable fsck for ext4 to ensure that things remain in
good shape there.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoFix ext4 block group descriptor sizing
Benjamin Lim [Fri, 29 Mar 2019 11:29:45 +0000 (07:29 -0400)]
Fix ext4 block group descriptor sizing

Ext4 allows for arbitrarily sized block group descriptors when 64-bit
addressing is enabled, which was previously not properly supported. This
patch dynamically allocates a chunk of memory of the correct size.

Signed-off-by: Benjamin Lim <jarsp.ctf@gmail.com>
5 years agotest/py: mmc: Add 'mmc read' performance check
Marek Vasut [Wed, 13 Mar 2019 16:49:29 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc read' performance check

Add option to the mmc rd test to check the duration of the
execution of the mmc read command. This allows intercepting
read performance regressions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agotest/py: mmc: Add 'mmc info' test
Marek Vasut [Wed, 13 Mar 2019 16:49:28 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc info' test

Add test for 'mmc info' subcommand. This tests whether the card
information is obtained correctly and verifies the device, bus
speed, bus mode and bus width.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agotest/py: mmc: Add 'mmc rescan' test
Marek Vasut [Wed, 13 Mar 2019 16:49:27 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc rescan' test

Add test for 'mmc rescan' subcommand. This tests whether the
system can switch to a specific card and then rescan the card.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agotest/py: mmc: Add 'mmc dev' test
Marek Vasut [Wed, 13 Mar 2019 16:49:26 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc dev' test

Add separate test for 'mmc dev' subcommand. This tests whether
the system can switch to a specific card.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agotest/py: mmc: Factor out device selection
Marek Vasut [Wed, 13 Mar 2019 16:49:25 +0000 (17:49 +0100)]
test/py: mmc: Factor out device selection

Factor out the 'mmc dev' call so it can be recycled by other tests.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agofs: fat: fix reading non-cluster-aligned root directory
Anssi Hannula [Wed, 27 Feb 2019 10:55:57 +0000 (12:55 +0200)]
fs: fat: fix reading non-cluster-aligned root directory

A FAT12/FAT16 root directory location is specified by a sector offset and
it might not start at a cluster boundary. It also resides before the
data area (before cluster 2).

However, the current code assumes that the root directory is located at
a beginning of a cluster, causing no files to be found if that is not
the case.

Since the FAT12/FAT16 root directory is located before the data area
and is not aligned to clusters, using unsigned cluster numbers to refer
to the root directory does not work well (the "cluster number" may be
negative, and even allowing it be signed would not make it properly
aligned).

Modify the code to not use the normal cluster numbering when referring to
the root directory of FAT12/FAT16 and instead use a cluster-sized
offsets counted from the root directory start sector.

This is a relatively common case as at least the filesystem formatter on
Win7 seems to create such filesystems by default on 2GB USB sticks when
"FAT" is selected (cluster size 64 sectors, rootdir size 32 sectors,
rootdir starts at half a cluster before cluster 2).

dosfstools mkfs.vfat does not seem to create affected filesystems.

Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
Reviewed-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Tested-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
5 years agofs: ext4: Problem with ext4load and sparse files
Gero Schumacher [Tue, 26 Feb 2019 15:45:22 +0000 (15:45 +0000)]
fs: ext4: Problem with ext4load and sparse files

Hi,

when I try to load a sparse file via ext4load, I am getting the error message
'invalid extent'

After a deeper look in the code, it seems to be an issue in the function ext4fs_get_extent_block in fs/ext4/ext4_common.c:

The file starts with 1k of zeros. The blocksize is 1024. So the first extend block contains the following information:

eh_entries: 1
eh_depth: 1
ei_block 1

When the upper layer (ext4fs_read_file) asks for fileblock 0, we are running in the 'invalid extent' error message.
For me it seems, that the code is not prepared for handling a sparse block at the beginning of the file. The following change, solved my problem:

I am really not an expert in ext4 filesystems. Can somebody please have a look at this issue and give me a feedback, if I am totally wrong or not?

5 years agotest: fs: Added tests for symlinks
Jean-Jacques Hiblot [Wed, 13 Feb 2019 11:15:27 +0000 (12:15 +0100)]
test: fs: Added tests for symlinks

Test cases are:
1) basic link creation, verify it can be followed
2) chained links, verify it can be followed
3) replace exiting file a with a link, and a link with a link. verify it
   can be followed
4) create a broken link, verify it can't be followed

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agofs: Add a new command to create symbolic links
Jean-Jacques Hiblot [Wed, 13 Feb 2019 11:15:26 +0000 (12:15 +0100)]
fs: Add a new command to create symbolic links

The command line is:
ln <interface> <dev[:part]> target linkname

Currently symbolic links are supported only in ext4 and only if the option
CMD_EXT4_WRITE is enabled.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agofs: ext4: Add support for the creation of symbolic links
Jean-Jacques Hiblot [Wed, 13 Feb 2019 11:15:25 +0000 (12:15 +0100)]
fs: ext4: Add support for the creation of symbolic links

Re-use the functions used to write/create a file, to support creation of a
symbolic link.
The difference with a regular file are small:
- The inode mode is flagged with S_IFLNK instead of S_IFREG
- The ext2_dirent's filetype is FILETYPE_SYMLINK instead of FILETYPE_REG
- Instead of storing the content of a file in allocated blocks, the path
to the target is stored. And if the target's path is short enough, no block
is allocated and the target's path is stored in ext2_inode.b.symlink

As with regulars files, if a file/symlink with the same name exits, it is
unlinked first and then re-created.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Fix ext4 env code]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agofs: ext4: constify the buffer passed to write functions
Jean-Jacques Hiblot [Wed, 13 Feb 2019 11:15:24 +0000 (12:15 +0100)]
fs: ext4: constify the buffer passed to write functions

There is no need to modify the buffer passed to ext4fs_write_file().
The memset() call is not required here and was likely copied from the
equivalent part of the ext4fs_read_file() function where we do need it.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agotest: fs: Add filesystem integrity checks
Jean-Jacques Hiblot [Wed, 13 Feb 2019 11:15:23 +0000 (12:15 +0100)]
test: fs: Add filesystem integrity checks

We need to make sure that file writes,file creation, etc. are properly
performed and do not corrupt the filesystem.
To help with this, introduce the assert_fs_integrity() function that
executes the appropriate fsck tool. It should be called at the end of any
test that modify the content/organization of the filesystem.
Currently only supports FATs and EXT4.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agotest: fs: disable the metadata checksums on ext4 filesystems
Jean-Jacques Hiblot [Wed, 13 Feb 2019 11:15:22 +0000 (12:15 +0100)]
test: fs: disable the metadata checksums on ext4 filesystems

If the metadata checksums are enabled, all write operations will fail.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 years agofs: ext4: cache extent data
Stephen Warren [Wed, 30 Jan 2019 19:58:05 +0000 (12:58 -0700)]
fs: ext4: cache extent data

When a file contains extents, U-Boot currently reads extent-related data
for each block in the file, even if that data is located in the same
block each time. This significantly slows down loading of files that use
extents. Implement a very dumb cache to prevent repeatedly reading the
same block. Files with extents now load as fast as files without.

Note: There are many cases where read_allocated_block() is called. This
patch only addresses one of those places; all others still read redundant
data in any case they did before. This is a minimal patch to fix the
load command; other cases aren't fixed.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-ubi
Tom Rini [Tue, 9 Apr 2019 16:10:53 +0000 (12:10 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-ubi

5 years agoMerge tag 'u-boot-atmel-2019.07-a' of git://git.denx.de/u-boot-atmel
Tom Rini [Tue, 9 Apr 2019 16:10:40 +0000 (12:10 -0400)]
Merge tag 'u-boot-atmel-2019.07-a' of git://git.denx.de/u-boot-atmel

First set of u-boot-atmel features and fixes for 2019.07 cycle

5 years agonet: macb: Add small delay after link establishment
Stefan Roese [Wed, 27 Mar 2019 10:20:19 +0000 (11:20 +0100)]
net: macb: Add small delay after link establishment

I've noticed that the first ethernet packet after PHY link establishment
is not tranferred correctly most of the time on my AT91SAM9G25 board.
Here I usually see a timeout of a few seconds, which is quite
annoying.

Adding a small delay (10ms in this case) after the link establishment
helps to solve this problem. With this patch applied, this timeout
on the first packet is not seen any more.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agopinctrl: at91: add slewrate support for SAM9X60
Claudiu Beznea [Mon, 25 Mar 2019 10:34:00 +0000 (10:34 +0000)]
pinctrl: at91: add slewrate support for SAM9X60

Add slew rate support for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
5 years agopinctrl: at91: add compatibles for SAM9X60 pin controller
Claudiu Beznea [Mon, 25 Mar 2019 10:33:59 +0000 (10:33 +0000)]
pinctrl: at91: add compatibles for SAM9X60 pin controller

Add compatibles for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
5 years agopinctrl: at91: add drive strength support for SAM9X60
Claudiu Beznea [Mon, 25 Mar 2019 10:33:57 +0000 (10:33 +0000)]
pinctrl: at91: add drive strength support for SAM9X60

Add drive strength support for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
5 years agopinctrl: at91: add option to use drive strength bits
Claudiu Beznea [Mon, 25 Mar 2019 10:33:56 +0000 (10:33 +0000)]
pinctrl: at91: add option to use drive strength bits

SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
5 years agoarm: at91: Add gardena-gateway-at91sam support
Stefan Roese [Tue, 2 Apr 2019 08:57:27 +0000 (10:57 +0200)]
arm: at91: Add gardena-gateway-at91sam support

The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agoarm: at91: at91sam9x5.dtsi: Add watchdog handle
Stefan Roese [Tue, 2 Apr 2019 08:57:26 +0000 (10:57 +0200)]
arm: at91: at91sam9x5.dtsi: Add watchdog handle

This makes it possible to reference the watchdog DT node via "&watchdog"
from board dts files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agoarm: at91: siemens: Add support to generate combined SPL+U-Boot image
Stefan Roese [Tue, 2 Apr 2019 08:57:25 +0000 (10:57 +0200)]
arm: at91: siemens: Add support to generate combined SPL+U-Boot image

This patch adds the necessary defines to the Siemens AT91SAM based
boards (smartweb, corvus and taurus) to generate the combined binary
image with SPL and main U-Boot image combined (u-boot-with-spl.bin).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
5 years agoMakefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binary
Stefan Roese [Wed, 3 Apr 2019 13:24:50 +0000 (15:24 +0200)]
Makefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binary

This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that
shall be used to generate the combined SPL + U-Boot image. The default
value is the current value "spl/u-boot-spl.bin".

This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets
which use SPL NAND support (boot from NAND). For these build targets the
combined image "u-boot-with-spl.bin" is now automatically generated and
can be programmed into NAND as one single image (vs. SPL image and U-Boot
as 2 separate images).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
5 years agoMakefile.spl: Move generated AT91SAM NAND image boot.bin to spl directory
Stefan Roese [Tue, 2 Apr 2019 08:57:23 +0000 (10:57 +0200)]
Makefile.spl: Move generated AT91SAM NAND image boot.bin to spl directory

This patch moves the AT91SAM NAND booting SPL image "boot.bin" which
includes the ECC values from the root directory into the spl directory,
where all SPL related images are located.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
5 years agoarm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds
Stefan Roese [Tue, 2 Apr 2019 08:57:22 +0000 (10:57 +0200)]
arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds

This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agoarm: at91: Enable watchdog support
Stefan Roese [Wed, 3 Apr 2019 05:37:40 +0000 (07:37 +0200)]
arm: at91: Enable watchdog support

This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
5 years agoarm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUT
Stefan Roese [Wed, 3 Apr 2019 05:37:05 +0000 (07:37 +0200)]
arm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUT

This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any
more. The WD timeout value can be provided via the "timeout-sec" DT
property. If not provided this way, the default value of 2 seconds will
be used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
5 years agowatchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start()
Stefan Roese [Tue, 2 Apr 2019 08:57:19 +0000 (10:57 +0200)]
watchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start()

This patch fixes the timer register setup in at91_wdt_start() to
correctly configure the register again. The input timeout value is
now in milli-seconds instead of seconds with the new watchdog API.
Make sure to take this into account and only use a max timeout
value of 16 seconds as appropriate for this SoC.

Also the check against a lower timeout value than 0 is removed. This
check makes no sense, as the timeout value is unsigned.

Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
5 years agowatchdog: Handle SPL build with watchdog disabled
Stefan Roese [Tue, 2 Apr 2019 08:57:18 +0000 (10:57 +0200)]
watchdog: Handle SPL build with watchdog disabled

This patch adds some checks, so that the watchdog can be enabled in main
U-Boot proper but can be disabled in SPL.

This will be used by some AT91SAM based boards, which might enable the
watchdog in the main U-Boot proper and not in SPL. It will be enabled in
SPL by default there, so no need to configure it there. This approach
saves some space in SPL.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
5 years agoserial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL
Stefan Roese [Wed, 3 Apr 2019 13:24:19 +0000 (15:24 +0200)]
serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL

This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.

Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.

This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
a different value if needed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
5 years agoarm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled
Stefan Roese [Tue, 2 Apr 2019 08:57:16 +0000 (10:57 +0200)]
arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled

This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
5 years agoarm: at91: Makefile: Compile lowlevel_init only when really necessary
Stefan Roese [Tue, 2 Apr 2019 08:57:15 +0000 (10:57 +0200)]
arm: at91: Makefile: Compile lowlevel_init only when really necessary

Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: Heiko Schocher <hs@denx.de>
5 years agoboard: pm9g45: Migrate to CONFIG_DM
Ilko Iliev [Wed, 3 Apr 2019 14:50:30 +0000 (16:50 +0200)]
board: pm9g45: Migrate to CONFIG_DM

Migrate the following options to CONFIG_DM:
  CONFIG_DM_GPIO
  CONFIG_DM_MMC
  CONFIG_DM_ETH
  CONFIG_DM_SERIAL
  CONFIG_DM_USB

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
5 years agoARM: at91: sama5d2: Wrap cpu detection to fix macb driver
Alexander Dahl [Fri, 22 Mar 2019 13:25:54 +0000 (14:25 +0100)]
ARM: at91: sama5d2: Wrap cpu detection to fix macb driver

When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?

That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:

#ifndef cpu_is_sama5d2
#define cpu_is_sama5d2() 0
#endif

That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.

The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:

=> dhcp
ethernet@f8008000: PHY present at 1
ethernet@f8008000: Starting autonegotiation...
ethernet@f8008000: Autonegotiation complete
ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17

Retry time exceeded; starting again

Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!

The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.

Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
5 years agomtd: ubi, ubifs debug: Use pr_debug instead of pr_crit
Eran Matityahu [Wed, 13 Feb 2019 18:56:17 +0000 (20:56 +0200)]
mtd: ubi, ubifs debug: Use pr_debug instead of pr_crit

Before printk.h was introduced and MTDDEBUG was removed,
pr_crit() was calling MTDDEBUG(), which was since then
replaced by the current pr_debug().

pr_debug is more appropriate here.

Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agomtd: ubi debug: Remove the pid print from ubi_assert
Eran Matityahu [Wed, 13 Feb 2019 18:55:43 +0000 (20:55 +0200)]
mtd: ubi debug: Remove the pid print from ubi_assert

Add a new definition for ubi_assert and keep
the original one in an ifndef __UBOOT__.

Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
5 years agoMerge tag 'efi-2019-07-rc1' of git://git.denx.de/u-boot-efi
Tom Rini [Tue, 9 Apr 2019 02:32:45 +0000 (22:32 -0400)]
Merge tag 'efi-2019-07-rc1' of git://git.denx.de/u-boot-efi

Pull request for UEFI sub-system for v2019.07-rc1

The patch series adds support for the BootNext and BootCurrent variables.

The rest is mostly bug fixes. With the bug fixes in place it becomes
possible to use the EFI Shell `edit` command.

A new unit test is supplied to check the image base and size fields of the
loaded image protocol.

An inline check when freeing memory from the pool safeguards against double
frees.

5 years agoMerge git://git.denx.de/u-boot-riscv
Tom Rini [Tue, 9 Apr 2019 02:32:11 +0000 (22:32 -0400)]
Merge git://git.denx.de/u-boot-riscv

- RISC-V arch support SMP.
- Support Andestech's PLIC and PLMT.
- qemu, fu54e, ae350 boards enable SMP by default.
- Fix CONFIG_DEFAULT_DEVICE_TREE failure.

5 years agoPrepare v2019.04 v2019.04
Tom Rini [Tue, 9 Apr 2019 01:40:40 +0000 (21:40 -0400)]
Prepare v2019.04

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoarm: sunxi: Enable DM_MMC on required SoCs
Jagan Teki [Mon, 8 Apr 2019 20:27:54 +0000 (01:57 +0530)]
arm: sunxi: Enable DM_MMC on required SoCs

Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.

Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]

So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.

Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.

[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html

Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agoMerge tag 'fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-staging
Tom Rini [Mon, 8 Apr 2019 14:11:29 +0000 (10:11 -0400)]
Merge tag 'fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-staging

- i.MX8QXP-MEK ethernet fix

5 years agodts: imx8qxp-mek: Add PHY post reset delay
Andrejs Cainikovs [Fri, 1 Mar 2019 13:28:00 +0000 (13:28 +0000)]
dts: imx8qxp-mek: Add PHY post reset delay

PHY cannot be detected unless we wait about 150 ms.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agonet: dm: fec: Support phy-reset-post-delay property
Andrejs Cainikovs [Fri, 1 Mar 2019 13:27:59 +0000 (13:27 +0000)]
net: dm: fec: Support phy-reset-post-delay property

As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
  a delay of phy-reset-post-delay milliseconds will be observed after the
  phy-reset-gpios has been toggled. Can be omitted thus no delay is
  observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
5 years agowatchdog: Move watchdog_dev to data section (BSS may not be cleared)
Stefan Roese [Wed, 3 Apr 2019 07:12:48 +0000 (09:12 +0200)]
watchdog: Move watchdog_dev to data section (BSS may not be cleared)

This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
5 years agoriscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure
Rick Chen [Wed, 3 Apr 2019 02:43:37 +0000 (10:43 +0800)]
riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure

It occurs since commit 27cb7300ffda
("Ensure device tree DTS is compiled").

More details can refer to
89c2b5c02049aea746b1edee0b4e1d8519dec2f4
ARM: fix arch/arm/dts/Makefile

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: ae350: enable SMP
Rick Chen [Tue, 2 Apr 2019 07:56:44 +0000 (15:56 +0800)]
riscv: ae350: enable SMP

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: dts: ae350 support SMP
Rick Chen [Tue, 2 Apr 2019 07:56:43 +0000 (15:56 +0800)]
riscv: dts: ae350 support SMP

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: ax25: Andes specific cache shall only support in M-mode
Rick Chen [Tue, 2 Apr 2019 07:56:42 +0000 (15:56 +0800)]
riscv: ax25: Andes specific cache shall only support in M-mode

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: ax25: Add platform-specific Kconfig options
Rick Chen [Tue, 2 Apr 2019 07:56:41 +0000 (15:56 +0800)]
riscv: ax25: Add platform-specific Kconfig options

Add ax25 RISC-V platform-specific Kconfig options,
to include CPU and timer drivers. Also disable
ATCPIT100 SoC timer and replace by PLMT.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: Add a SYSCON driver for Andestech's PLMT
Rick Chen [Tue, 2 Apr 2019 07:56:40 +0000 (15:56 +0800)]
riscv: Add a SYSCON driver for Andestech's PLMT

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: Add a SYSCON driver for Andestech's PLIC
Rick Chen [Tue, 2 Apr 2019 07:56:39 +0000 (15:56 +0800)]
riscv: Add a SYSCON driver for Andestech's PLIC

The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: qemu: enable SMP
Lukas Auer [Sun, 17 Mar 2019 18:28:42 +0000 (19:28 +0100)]
riscv: qemu: enable SMP

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: fu540: enable SMP
Lukas Auer [Sun, 17 Mar 2019 18:28:41 +0000 (19:28 +0100)]
riscv: fu540: enable SMP

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: hang if relocation of secondary harts fails
Lukas Auer [Sun, 17 Mar 2019 18:28:40 +0000 (19:28 +0100)]
riscv: hang if relocation of secondary harts fails

Print an error message and hang if smp_call_function() returns an error,
indicating that relocation of the secondary harts has failed.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
5 years agoriscv: do not rely on hart ID passed by previous boot stage
Lukas Auer [Sun, 17 Mar 2019 18:28:39 +0000 (19:28 +0100)]
riscv: do not rely on hart ID passed by previous boot stage

RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.

Suggested-by: Rick Chen <rick@andestech.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
5 years agoriscv: boot images passed to bootm on all harts
Lukas Auer [Sun, 17 Mar 2019 18:28:38 +0000 (19:28 +0100)]
riscv: boot images passed to bootm on all harts

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: add support for multi-hart systems
Lukas Auer [Sun, 17 Mar 2019 18:28:37 +0000 (19:28 +0100)]
riscv: add support for multi-hart systems

On RISC-V, all harts boot independently. To be able to run on a
multi-hart system, U-Boot must be extended with the functionality to
manage all harts in the system. All harts entering U-Boot are registered
in the available_harts mask stored in global data. A hart lottery system
as used in the Linux kernel selects the hart U-Boot runs on. All other
harts are halted. U-Boot can delegate functions to them using
smp_call_function().

Every hart has a valid pointer to the global data structure and a 8KiB
stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: save hart ID in register tp instead of s0
Lukas Auer [Sun, 17 Mar 2019 18:28:36 +0000 (19:28 +0100)]
riscv: save hart ID in register tp instead of s0

The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
5 years agoriscv: delay initialization of caches and debug UART
Lukas Auer [Sun, 17 Mar 2019 18:28:35 +0000 (19:28 +0100)]
riscv: delay initialization of caches and debug UART

Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once on the main hart running
U-Boot.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: implement IPI platform functions using SBI
Lukas Auer [Sun, 17 Mar 2019 18:28:34 +0000 (19:28 +0100)]
riscv: implement IPI platform functions using SBI

The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: import the supervisor binary interface header file
Lukas Auer [Sun, 17 Mar 2019 18:28:33 +0000 (19:28 +0100)]
riscv: import the supervisor binary interface header file

Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
5 years agoriscv: add infrastructure for calling functions on other harts
Lukas Auer [Sun, 17 Mar 2019 18:28:32 +0000 (19:28 +0100)]
riscv: add infrastructure for calling functions on other harts

Harts on RISC-V boot independently, U-Boot is responsible for managing
them. Functions are called on other harts with smp_call_function(),
which sends inter-processor interrupts (IPIs) to all other available
harts. Available harts are those marked as available in the device tree
and present in the available_harts mask stored in global data. The
available_harts mask is used to register all harts that have entered
U-Boot. Functions are specified with their address and two function
arguments (argument 2 and 3). The first function argument is always the
hart ID of the hart calling the function. On the other harts, the IPI
interrupt handler handle_ipi() must be called on software interrupts to
handle the request and call the specified function.

Functions are stored in the ipi_data data structure. Every hart has its
own data structure in global data. While this is not required at the
moment (all harts are expected to boot Linux), this does allow future
expansion, where other harts may be used for monitoring or other tasks.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
5 years agonet: phy: implement fallback mechanism for negative phy adresses
Hannes Schmelzer [Fri, 29 Mar 2019 08:54:05 +0000 (09:54 +0100)]
net: phy: implement fallback mechanism for negative phy adresses

Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
5 years agoefi_loader: correct CTRL-A - CTRL-Z console input
Heinrich Schuchardt [Sat, 6 Apr 2019 18:59:24 +0000 (20:59 +0200)]
efi_loader: correct CTRL-A - CTRL-Z console input

In the extended text input protocol CTRL-A - CTRL-Z have to be signaled as
Unicode characters a-z or A-Z depending on the shift state and not as 0x01
to 0x1a.

Update Python unit test.

This patch is required for using the EFI shell `edit` command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>