oweals/u-boot.git
15 years agofsl-ddr: make the self refresh idle threshold configurable
Dave Liu [Fri, 21 Nov 2008 08:31:35 +0000 (16:31 +0800)]
fsl-ddr: make the self refresh idle threshold configurable

Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years agofsl-ddr: clean up the ddr code for DDR3 controller
Dave Liu [Fri, 21 Nov 2008 08:31:29 +0000 (16:31 +0800)]
fsl-ddr: clean up the ddr code for DDR3 controller

- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years agofsl-ddr: update the bit mask for DDR3 controller
Dave Liu [Fri, 21 Nov 2008 08:31:22 +0000 (16:31 +0800)]
fsl-ddr: update the bit mask for DDR3 controller

According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.

Signed-off-by: Dave Liu <daveliu@freescale.com>
15 years ago85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards
Kumar Gala [Tue, 2 Dec 2008 22:08:40 +0000 (16:08 -0600)]
85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards

Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years ago85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Kumar Gala [Tue, 2 Dec 2008 22:08:39 +0000 (16:08 -0600)]
85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards

Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address.  In most situations these are
mapped 1:1.  However any code accessing the bus should use VIRT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years ago85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards
Kumar Gala [Tue, 2 Dec 2008 22:08:38 +0000 (16:08 -0600)]
85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards

Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields
of TLBs.  This is what we should have always been using from the start.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years ago85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
Kumar Gala [Tue, 2 Dec 2008 22:08:37 +0000 (16:08 -0600)]
85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards

Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years ago85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards
Kumar Gala [Tue, 2 Dec 2008 22:08:36 +0000 (16:08 -0600)]
85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards

Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years ago85xx: separate FLASH BASE virtual from physical address
Kumar Gala [Tue, 2 Dec 2008 20:19:34 +0000 (14:19 -0600)]
85xx: separate FLASH BASE virtual from physical address

Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and
maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years ago85xx: separate PIXIS virtual from physical address
Kumar Gala [Tue, 2 Dec 2008 20:19:33 +0000 (14:19 -0600)]
85xx: separate PIXIS virtual from physical address

Added a PIXIS_BASE_PHYS for use as the physical address and maintain
PIXIS_BASE as the virtual address of the PIXIS fpga registers.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years agoAdd README file for MPC8572DS board
Haiying Wang [Tue, 11 Nov 2008 13:52:09 +0000 (08:52 -0500)]
Add README file for MPC8572DS board

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
15 years agoBlackfin: use common strmhz() in system output
Mike Frysinger [Mon, 20 Oct 2008 20:15:04 +0000 (16:15 -0400)]
Blackfin: use common strmhz() in system output

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoMerge branch 'master' of git://git.denx.de/u-boot-nand-flash
Wolfgang Denk [Fri, 23 Jan 2009 21:48:06 +0000 (22:48 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

15 years agoMerge branch 'master' of git://git.denx.de/u-boot-microblaze
Wolfgang Denk [Fri, 23 Jan 2009 21:47:25 +0000 (22:47 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-microblaze

15 years agonand: fixup printf modifiers to match types used
Mike Frysinger [Mon, 19 Jan 2009 00:46:06 +0000 (19:46 -0500)]
nand: fixup printf modifiers to match types used

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agonand read.jffs2 (nand_legacy) in common/cmd_nand.c
Schlaegl Manfred jun [Tue, 20 Jan 2009 15:57:55 +0000 (16:57 +0100)]
nand read.jffs2 (nand_legacy) in common/cmd_nand.c

Error with CONFIG_NAND_LEGACY in common/cmd_nand.c:
With current code "nand read.jffs2s" (read and skip bad blocks) is always interpreted as
"nand read.jffs2" (read and fill bad blocks with 0xff). This is because ".jffs2" is
tested before ".jffs2s" and only the first two characters are compared.

Correction:
Test for ".jffs2s" first and compare the first 7 characters.

Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoNAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS
Wolfgang Grandegger [Fri, 16 Jan 2009 17:55:54 +0000 (18:55 +0100)]
NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS

This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define

 #define NAND_MAX_CHIPS          CONFIG_SYS_MAX_NAND_DEVICE

but that's bogus and did not work anyhow.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoNAND: Fix cache and memory inconsistency issue
Dave Liu [Tue, 2 Dec 2008 03:48:51 +0000 (11:48 +0800)]
NAND: Fix cache and memory inconsistency issue

We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.

- 83xx family is using the d-cache lock, so all of d-cache
  access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
  cache lock. you will see the issue.

This patch fixes the cache issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoNAND: Enable nand lock, unlock feature
Nishanth Menon [Sat, 13 Dec 2008 15:43:06 +0000 (09:43 -0600)]
NAND: Enable nand lock, unlock feature

Enable nand lock, unlock and status of lock feature.
Not every device and platform requires this, hence,
it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK

Nand unlock and status operate on block boundary instead
of page boundary. Details in:
http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT

Intial solution provided by Vikram Pandita <vikram.pandita@ti.com>
Includes preliminary suggestions from Scott Wood

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoNAND: move board_nand_init to nand.h
Mike Frysinger [Sat, 6 Dec 2008 07:40:55 +0000 (02:40 -0500)]
NAND: move board_nand_init to nand.h

Rather than putting the function prototype for board_nand_init() in the one
place where it gets called, put it into nand.h so that every place that also
defines it gets the prototype.  Otherwise, errors can go silently unnoticed
such as using the wrong return value (void rather than int) when defining
the function.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoOneNAND: Additional sync with 2.6.27
Stefan Roese [Tue, 2 Dec 2008 10:06:47 +0000 (11:06 +0100)]
OneNAND: Additional sync with 2.6.27

- Add subpage write support
- Add onenand_oob_64/32 ecclayout

This has been missing and without it UBI has some incompatibilies issues
with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is
placed differently (2048 instead of 512) without this fix.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
15 years agoAdd markbad function
Kyungmin Park [Thu, 13 Nov 2008 06:14:33 +0000 (15:14 +0900)]
Add markbad function

Add missing markbad function
If not, it's hang when it entered the mtd->mark_bad().

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
15 years agoOneNAND: Bad block aware read/write command support
Stefan Roese [Wed, 12 Nov 2008 12:47:24 +0000 (13:47 +0100)]
OneNAND: Bad block aware read/write command support

Update OneNAND command to support bad block awareness.
Also change the OneNAND command style to better match the
NAND version.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
15 years agoOneNAND: Save version_id in onenand_chip struct
Stefan Roese [Tue, 11 Nov 2008 09:29:09 +0000 (10:29 +0100)]
OneNAND: Save version_id in onenand_chip struct

The version (ver_id) was not stored in the onenand_chip structure and
because of this the continuous locking scheme could be enabled on some
chips.

Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoOneNAND: Fix compiler warnings
Stefan Roese [Tue, 11 Nov 2008 09:28:53 +0000 (10:28 +0100)]
OneNAND: Fix compiler warnings

Signed-off-by: Stefan Roese <sr@denx.de>
15 years agompc83xx: enable eLBC NAND support for MPC8315ERDB board
Dave Liu [Tue, 4 Nov 2008 06:55:06 +0000 (14:55 +0800)]
mpc83xx: enable eLBC NAND support for MPC8315ERDB board

Signed-off-by: Dave Liu <daveliu@freescale.com>
15 years agoSync with 2.6.27
Kyungmin Park [Tue, 4 Nov 2008 00:24:07 +0000 (09:24 +0900)]
Sync with 2.6.27

Sync with OneNAND kernel codes

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
15 years agomicroblaze: Use cache functions (especially cache status)
Michal Simek [Mon, 5 Jan 2009 12:35:31 +0000 (13:35 +0100)]
microblaze: Use cache functions (especially cache status)
in systems which are configured without flash

15 years agomicroblaze: Add cache flush
Michal Simek [Mon, 5 Jan 2009 12:29:32 +0000 (13:29 +0100)]
microblaze: Add cache flush

15 years agomicroblaze: Add bootup messages to board.c
Michal Simek [Mon, 5 Jan 2009 12:28:40 +0000 (13:28 +0100)]
microblaze: Add bootup messages to board.c

15 years agomicroblaze: Change microblaze-generic config file
Michal Simek [Fri, 19 Dec 2008 12:25:55 +0000 (13:25 +0100)]
microblaze: Change microblaze-generic config file

Signed-off-by: Michal Simek <monstr@monstr.eu>
15 years agomicroblaze: Rename ml401 to microblaze-generic
Michal Simek [Fri, 19 Dec 2008 12:14:05 +0000 (13:14 +0100)]
microblaze: Rename ml401 to microblaze-generic

Signed-off-by: Michal Simek <monstr@monstr.eu>
15 years agoMerge branch 'fixes'
Haavard Skinnemoen [Thu, 22 Jan 2009 10:11:09 +0000 (11:11 +0100)]
Merge branch 'fixes'

15 years agoPrepare v2009.01 v2009.01
Wolfgang Denk [Wed, 21 Jan 2009 22:08:12 +0000 (23:08 +0100)]
Prepare v2009.01

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoPrepare 2009.01-rc3 v2009.01-rc3
Wolfgang Denk [Sun, 18 Jan 2009 20:37:48 +0000 (21:37 +0100)]
Prepare 2009.01-rc3

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoMerge branch 'master' of /home/wd/git/u-boot/custodians
Wolfgang Denk [Sun, 18 Jan 2009 20:11:05 +0000 (21:11 +0100)]
Merge branch 'master' of /home/wd/git/u-boot/custodians

15 years agobuild system: treat all Darwin's alike
Mike Frysinger [Sat, 17 Jan 2009 18:32:42 +0000 (13:32 -0500)]
build system: treat all Darwin's alike

The x86 based version of Darwin behaves the same quirky way as the powerpc
Darwin, so only check HOSTOS when setting up Darwin workarounds.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agofdt_resize(): fix actualsize calculations with unaligned blobs
Peter Korsgaard [Wed, 14 Jan 2009 12:52:24 +0000 (13:52 +0100)]
fdt_resize(): fix actualsize calculations with unaligned blobs

The code in fdt_resize() to extend the fdt size to end on a page boundary
is wrong for fdt's not located at an address aligned on a page boundary.
What's even worse, the code would make actualsize shrink rather than grow
if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(),
causing fdt_add_mem_rsv to fail.

Fix it by aligning end address (blob + size) to a page boundary instead.
For aligned fdt's this is equivalent to what we had before.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
15 years agoncb: use socklen_t
Mike Frysinger [Fri, 9 Jan 2009 09:38:17 +0000 (04:38 -0500)]
ncb: use socklen_t

The recvfrom() function takes a socklen_t, not an int.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Wolfgang Denk [Fri, 16 Jan 2009 08:22:25 +0000 (09:22 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

15 years agoMerge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Wolfgang Denk [Fri, 16 Jan 2009 08:17:53 +0000 (09:17 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

15 years agosh: serial: use readx/writex accessors
Jean-Christophe PLAGNIOL-VILLARD [Sun, 11 Jan 2009 15:35:16 +0000 (16:35 +0100)]
sh: serial: use readx/writex accessors

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agosh: serial: coding style cleanup
Jean-Christophe PLAGNIOL-VILLARD [Sun, 11 Jan 2009 15:35:15 +0000 (16:35 +0100)]
sh: serial: coding style cleanup

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agosh: Fix compile error on lowlevel_init file
Nobuhiro Iwamatsu [Sun, 11 Jan 2009 08:48:56 +0000 (17:48 +0900)]
sh: Fix compile error on lowlevel_init file

lowlevel_init of SH was corrected to use the write/readXX macro.
However, there was a problem that was not able to be compiled partially.
This patch corrected this.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agosh: Fix up rsk7203 target for out of tree build
Kieran Bingham [Tue, 30 Dec 2008 01:16:03 +0000 (01:16 +0000)]
sh: Fix up rsk7203 target for out of tree build

Fix up rsk7203 target to build successfully using out-of-tree build.

Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agosh: use write{8,16,32} in all lowlevel_init
Jean-Christophe PLAGNIOL-VILLARD [Sat, 20 Dec 2008 18:29:49 +0000 (19:29 +0100)]
sh: use write{8,16,32} in all lowlevel_init

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agosh: lowlevel_init coding style cleanup
Jean-Christophe PLAGNIOL-VILLARD [Sat, 20 Dec 2008 18:29:48 +0000 (19:29 +0100)]
sh: lowlevel_init coding style cleanup

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agosh: update sh2/sh2a timer coding style
Jean-Christophe PLAGNIOL-VILLARD [Sat, 20 Dec 2008 14:27:45 +0000 (15:27 +0100)]
sh: update sh2/sh2a timer coding style

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agosh: update sh timer coding style
Jean-Christophe PLAGNIOL-VILLARD [Sat, 20 Dec 2008 14:25:22 +0000 (15:25 +0100)]
sh: update sh timer coding style

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
15 years agoPrepare 2009.01-rc2 v2009.01-rc2
Wolfgang Denk [Wed, 14 Jan 2009 22:26:05 +0000 (23:26 +0100)]
Prepare 2009.01-rc2

Update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agocpu/mpc824x/Makefile: fix warning with parallel builds
Wolfgang Denk [Wed, 14 Jan 2009 21:35:30 +0000 (22:35 +0100)]
cpu/mpc824x/Makefile: fix warning with parallel builds

Parallel builds would occasionally issue this build warning:

    ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists

Use "ln -sf" as quick work around for the issue.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards
Matthias Fuchs [Fri, 2 Jan 2009 11:18:49 +0000 (12:18 +0100)]
ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards

This patch adds esd's loadpci BSP command to CPCI4052 and
CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Disable pci node in device tree on CPCI405 pci adapters
Matthias Fuchs [Fri, 2 Jan 2009 11:18:12 +0000 (12:18 +0100)]
ppc4xx: Disable pci node in device tree on CPCI405 pci adapters

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Cleanup CPCI405 board code
Matthias Fuchs [Fri, 2 Jan 2009 11:17:36 +0000 (12:17 +0100)]
ppc4xx: Cleanup CPCI405 board code

This patch cleans up CPCI405 board support:
- wrap long lines
- unification of spaces in function calls
- remove dead code

Use correct io accessors on peripherals.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoppc4xx: Enable auto RS485 mode on PLU405 boards
Matthias Fuchs [Fri, 2 Jan 2009 11:16:35 +0000 (12:16 +0100)]
ppc4xx: Enable auto RS485 mode on PLU405 boards

This patch turns on the auto RS485 mode in the 2nd external
uart on PLU405 boards. This is a special mode of the used
Exar XR16C2850 uart. Because these boards only have a 485 physical
layer connected it's a good idea to turn it on by default.

Signed-off-by: Matthias Fuchs <mf@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
15 years agoMerge branch 'master' of /home/wd/git/u-boot/custodians
Wolfgang Denk [Tue, 13 Jan 2009 23:27:06 +0000 (00:27 +0100)]
Merge branch 'master' of /home/wd/git/u-boot/custodians

15 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Tue, 13 Jan 2009 23:26:48 +0000 (00:26 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

15 years agoSome changes of TLB entry setting for MPC8572DS
Haiying Wang [Tue, 13 Jan 2009 21:29:28 +0000 (16:29 -0500)]
Some changes of TLB entry setting for MPC8572DS

- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
15 years agoChange DDR tlb start entry to CONFIG param for 85xx
Haiying Wang [Tue, 13 Jan 2009 21:29:22 +0000 (16:29 -0500)]
Change DDR tlb start entry to CONFIG param for 85xx

So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
15 years agoChange PCIE1&2 deciide logic on MPC8544DS board more readable
Roy Zang [Fri, 9 Jan 2009 08:02:35 +0000 (16:02 +0800)]
Change PCIE1&2 deciide logic on MPC8544DS board more readable

The IO port selection for MPC8544DS board:
 Port cfg_io_ports
 PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2 0x4, 0x5, 0x6, 0x7
 PCIE3 0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
15 years agoPCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit
Roy Zang [Fri, 9 Jan 2009 08:01:52 +0000 (16:01 +0800)]
PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit

PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
15 years agoFix IO port selection issue on MPC8544DS and MPC8572DS boards
Roy Zang [Fri, 9 Jan 2009 08:00:55 +0000 (16:00 +0800)]
Fix IO port selection issue on MPC8544DS and MPC8572DS boards

The IO port selection is not correct on MPC8572DS and MPC8544DS board.
 This patch fixes this issue.
 For MPC8572
 Port cfg_io_ports
 PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf
 PCIE2 0x3, 0x7
 PCIE3 0x7

For MPC8544
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2 0x4, 0x5, 0x6, 0x7
PCIE3 0x6, 0x7
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
15 years agompc8610hpcd: Fix PCI mapping concepts
Becky Bruce [Thu, 4 Dec 2008 04:36:44 +0000 (22:36 -0600)]
mpc8610hpcd: Fix PCI mapping concepts

Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
15 years agosbc8641d: Fix PCI mapping concepts
Becky Bruce [Thu, 4 Dec 2008 04:36:26 +0000 (22:36 -0600)]
sbc8641d: Fix PCI mapping concepts

Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
15 years agoMPC86xx: fix build warnings
Wolfgang Denk [Mon, 12 Jan 2009 13:50:35 +0000 (14:50 +0100)]
MPC86xx: fix build warnings

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years agoMerge branch 'master' of git://git.denx.de/u-boot-blackfin
Wolfgang Denk [Sat, 10 Jan 2009 17:18:37 +0000 (18:18 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-blackfin

15 years agobf537-stamp/nand: fix board_nand_init prototype
Mike Frysinger [Mon, 5 Jan 2009 21:09:44 +0000 (16:09 -0500)]
bf537-stamp/nand: fix board_nand_init prototype

The board_nand_init() function should return an int, not void.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoBlackfin: drop CONFIG_SPI handling in board init
Mike Frysinger [Thu, 11 Dec 2008 12:04:48 +0000 (07:04 -0500)]
Blackfin: drop CONFIG_SPI handling in board init

The eeprom SPI init functions are duplicated as the common code already
executes these for us.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoBlackfin: fix out-of-tree building with ldscripts
Mike Frysinger [Fri, 24 Oct 2008 21:51:57 +0000 (17:51 -0400)]
Blackfin: fix out-of-tree building with ldscripts

Many of the Blackfin board linker scripts are preprocessed, so make sure we
output the linker script into the build tree rather than the source tree.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoBlackfin: fix linker scripts to work with --gc-sections
Mike Frysinger [Fri, 24 Oct 2008 21:48:54 +0000 (17:48 -0400)]
Blackfin: fix linker scripts to work with --gc-sections

Make sure all .text sections get pulled in and the entry point is properly
referenced so they don't get discarded when linking with --gc-sections.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoBlackfin: set proper LDRFLAGS for parallel booting LDRs
Mike Frysinger [Sun, 12 Oct 2008 00:45:44 +0000 (20:45 -0400)]
Blackfin: set proper LDRFLAGS for parallel booting LDRs

In order to boot an LDR out of parallel flash, the ldr utility needs a few
flags to tell it to generate the right header.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
15 years agoat91rm9200: move define from lowlevel_init to header
Jean-Christophe PLAGNIOL-VILLARD [Tue, 6 Jan 2009 20:41:59 +0000 (21:41 +0100)]
at91rm9200: move define from lowlevel_init to header

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 years agom501sk: move to the common memory setup
Jean-Christophe PLAGNIOL-VILLARD [Sat, 3 Jan 2009 16:22:26 +0000 (17:22 +0100)]
m501sk: move to the common memory setup

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 years agoat91rm9200: rename lowlevel init value to CONFIG_SYS_
Jean-Christophe PLAGNIOL-VILLARD [Sat, 3 Jan 2009 16:22:25 +0000 (17:22 +0100)]
at91rm9200: rename lowlevel init value to CONFIG_SYS_

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 years agoat91: add at91sam9xeek board support
Nicolas Ferre [Tue, 6 Jan 2009 20:13:14 +0000 (21:13 +0100)]
at91: add at91sam9xeek board support

At91sam9xe is basically an at91sam9260 with embedded flash. We can manage
it as another entry for at91sam9260 in the Makefile.

Check documentation at :
http://www.atmel.com/dyn/products/product_card.asp?part_id=4263

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 years agofix bmp_logo.h make dependencies to allow parallel build
Jean-Christophe PLAGNIOL-VILLARD [Tue, 6 Jan 2009 20:15:57 +0000 (21:15 +0100)]
fix bmp_logo.h make dependencies to allow parallel build

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 years agoat91: Fix Atmel's at91sam9 boards out of tree build
Jean-Christophe PLAGNIOL-VILLARD [Sat, 3 Jan 2009 16:22:24 +0000 (17:22 +0100)]
at91: Fix Atmel's at91sam9 boards out of tree build

introduced in commit 89a7a87f084c

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Tue, 30 Dec 2008 22:30:47 +0000 (23:30 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

15 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Wolfgang Denk [Tue, 30 Dec 2008 22:28:13 +0000 (23:28 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

15 years agoMerge branch 'master' of git://git.denx.de/u-boot-nand-flash
Wolfgang Denk [Tue, 30 Dec 2008 22:25:01 +0000 (23:25 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

15 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Wolfgang Denk [Tue, 30 Dec 2008 22:22:19 +0000 (23:22 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

15 years agoREADME: update mailing list name and hits to patch submission.
Wolfgang Denk [Tue, 30 Dec 2008 21:56:11 +0000 (22:56 +0100)]
README: update mailing list name and hits to patch submission.

Signed-off-by: Wolfgang Denk <wd@denx.de>
15 years ago85xx: Enable inbound PCI config cycles for X-ES boards cleanup
Peter Tyser [Tue, 23 Dec 2008 22:32:01 +0000 (16:32 -0600)]
85xx: Enable inbound PCI config cycles for X-ES boards cleanup

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years agoXPedite5200 board support cleanup
Peter Tyser [Tue, 23 Dec 2008 22:32:00 +0000 (16:32 -0600)]
XPedite5200 board support cleanup

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years agousb_kbd: fix usb_kbd_deregister when DEVICE_DEREGISTER not enable
Jean-Christophe PLAGNIOL-VILLARD [Tue, 2 Dec 2008 20:58:04 +0000 (21:58 +0100)]
usb_kbd: fix usb_kbd_deregister when DEVICE_DEREGISTER not enable

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Remy Böhmer <linux@bohmer.net>
15 years agompc8[56]xx: Put localbus clock in sysinfo and gd
Trent Piepho [Wed, 3 Dec 2008 23:16:37 +0000 (15:16 -0800)]
mpc8[56]xx: Put localbus clock in sysinfo and gd

Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.

This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.

The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.

get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.

checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
15 years agompc86xx: Double local bus clock divider
Trent Piepho [Wed, 3 Dec 2008 23:16:36 +0000 (15:16 -0800)]
mpc86xx: Double local bus clock divider

The local bus clock divider should be doubled for both 8610 and 8641.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
15 years agompc8568: Double local bus clock divider
Trent Piepho [Wed, 3 Dec 2008 23:16:35 +0000 (15:16 -0800)]
mpc8568: Double local bus clock divider

The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.

Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
15 years ago85xx: Fix the boot window issue
Dave Liu [Tue, 16 Dec 2008 04:09:27 +0000 (12:09 +0800)]
85xx: Fix the boot window issue

If one custom board is using the 8MB flash, it is set
as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000.
The current start.S code will be broken at switch_as.

It is because the TLB1[15] is set as 16MB page size,
EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000.

For the 8MB flash case, the EPN = 0xefxxxxxx,
RPN = 0xffxxxxxx. Assume the virt address of switch_as
is 0xef7ff18c, the real address of the instruction at
switch_as should be 0xff7ff18c. the 0xff7ff18c is out
of the range of the default 8MB boot LAW window
0xff800000 - 0xffffffff.

So when we switch to AS1 address space at switch_as,
the core can't fetch the instruction at switch_as any
more. It will cause broken issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
15 years agosbc8548: use proper PHY address
Paul Gortmaker [Thu, 11 Dec 2008 20:47:50 +0000 (15:47 -0500)]
sbc8548: use proper PHY address

The values given for the PHY address were wrong, so the code
read no valid PHY ID, and fell through to the generic PHY
support, which would work on 1000M but would not auto negotiate
down to 100M or 10M.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
15 years agosbc8548: enable command line editing by default.
Paul Gortmaker [Thu, 11 Dec 2008 20:47:51 +0000 (15:47 -0500)]
sbc8548: enable command line editing by default.

Lets make things a bit more user friendly.  It isn't 1985 anymore.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
15 years agosbc8548: don't enable the 3rd and 4th eTSEC
Paul Gortmaker [Thu, 11 Dec 2008 20:47:49 +0000 (15:47 -0500)]
sbc8548: don't enable the 3rd and 4th eTSEC

These interfaces don't have usable connectors on the board, so don't
bother enumerating or configuring them.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
15 years agoSet IVPR to kenrel entry point in second core boot page
Haiying Wang [Wed, 3 Dec 2008 15:08:19 +0000 (10:08 -0500)]
Set IVPR to kenrel entry point in second core boot page

Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
15 years agompc8xxx: LCRR[CLKDIV] is sometimes five bits
Trent Piepho [Wed, 3 Dec 2008 23:16:34 +0000 (15:16 -0800)]
mpc8xxx: LCRR[CLKDIV] is sometimes five bits

On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
15 years agompc8[56]xx: Put localbus clock in device tree
Trent Piepho [Wed, 3 Dec 2008 23:16:38 +0000 (15:16 -0800)]
mpc8[56]xx: Put localbus clock in device tree

Export the localbus frequency in the device tree, the same way the CPU, TB,
CCB, and various other frequencies are exported in their respective device
tree nodes.

Some localbus devices need this information to be programed correctly, so
it makes sense to export it along with the other frequencies.

Unfortunately, when someone wrote the localbus dts bindings, they didn't
bother to define what the "compatible" property should be.  So it seems no
one was quite sure what to put in their dts files.

Based on current existing dts files in the kernel source, I've used
"fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all
of the 85xx devices, and are looked for by the Linux code.  The eLBC is
apparently not entirely backward compatible with the pq3 LBC and so eLBC
equipped platforms like 8572 won't use pq3-localbus.

For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems
and is also looked for by the Linux code.  On MPC8641, I've also used
"fsl,mpc8641-localbus" as it is also commonly used in dts files, some of
which don't use "fsl,elbc" or any other acceptable name to match on.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
15 years agoNAND FSL elbc: Use virt_to_phys to determine which bank is in use
Kumar Gala [Tue, 16 Dec 2008 20:59:22 +0000 (14:59 -0600)]
NAND FSL elbc: Use virt_to_phys to determine which bank is in use

The current code that determines which bank/chipselect is used for a
given NAND instance only worked for 32-bit addresses and assumed
a 1:1 mapping.  This breaks in 36-bit physical configs.

The proper way to handle this is to use the virt_to_phys() and
BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address
with the the virtual address the NAND code uses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Scott Wood <scottwood@freescale.com>
15 years agoppc: Use addrmap in virt_to_phys and map_physmem.
Kumar Gala [Tue, 16 Dec 2008 20:59:21 +0000 (14:59 -0600)]
ppc: Use addrmap in virt_to_phys and map_physmem.

If we have addr map support enabled use the mapping functions to
implement virt_to_phys() and map_physmem().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years ago85xx: Add support to populate addr map based on TLB settings
Kumar Gala [Tue, 16 Dec 2008 20:59:20 +0000 (14:59 -0600)]
85xx: Add support to populate addr map based on TLB settings

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 years agoXPedite5200 board support
Peter Tyser [Mon, 1 Dec 2008 19:47:13 +0000 (13:47 -0600)]
XPedite5200 board support

Initial support for Extreme Engineering Solutions XPedite5200 -
a MPC8548-based PMC single board computer.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years ago85xx: Enable inbound PCI config cycles for X-ES boards
Peter Tyser [Wed, 29 Oct 2008 17:39:27 +0000 (12:39 -0500)]
85xx: Enable inbound PCI config cycles for X-ES boards

Update X-ES Freescale boards to allow inbound PCI configuration
cycles when configured as agent/endpoint.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>