oweals/u-boot.git
8 years agostrider: Support con-dp flavor
Dirk Eibach [Thu, 2 Jun 2016 07:05:41 +0000 (09:05 +0200)]
strider: Support con-dp flavor

There is a new strider console flavor with DisplayPort
video.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agogdsys: osd: Allow osdsize on valid screens only
Dirk Eibach [Thu, 2 Jun 2016 07:05:40 +0000 (09:05 +0200)]
gdsys: osd: Allow osdsize on valid screens only

Limit "osdsize"-command to access valid screens only.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoioep-fpga: Support intempo compression
Dirk Eibach [Thu, 2 Jun 2016 07:05:39 +0000 (09:05 +0200)]
ioep-fpga: Support intempo compression

There is a new "intempo" compression type that can
be reported on startup.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoFix to davinci_nand.h to place CEnCFG registers at correct
Peter Howard [Thu, 2 Jun 2016 03:19:26 +0000 (13:19 +1000)]
Fix to davinci_nand.h to place CEnCFG registers at correct

Signed-off-by: Peter Howard <phoward@gme.net.au>
8 years agodm: scsi: if_typename should be scsi
Ed Swarthout [Wed, 1 Jun 2016 13:11:24 +0000 (08:11 -0500)]
dm: scsi: if_typename should be scsi

Fixes:

=> ext2ls scsi 0:1
** Bad device scsi 0:1 **

for boards which use the scsi legacy driver (such as ls1043ardb).

Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Mon, 6 Jun 2016 14:04:58 +0000 (10:04 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

Modified:
configs/ls1012afrdm_qspi_defconfig
configs/ls1012aqds_qspi_defconfig
configs/ls1012ardb_qspi_defconfig
include/configs/ls1012afrdm.h
include/configs/ls1012aqds.h
include/configs/ls1012ardb.h

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Mon, 6 Jun 2016 11:16:39 +0000 (07:16 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-microblaze

8 years agoARM64: zynqmp: Extend malloc space before relocation
Michal Simek [Fri, 3 Jun 2016 09:35:17 +0000 (11:35 +0200)]
ARM64: zynqmp: Extend malloc space before relocation

For boards which have more devices it is necessary to extend malloc
space.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add support for standard distro boot commands
Michal Simek [Fri, 22 Apr 2016 12:28:54 +0000 (14:28 +0200)]
ARM64: zynqmp: Add support for standard distro boot commands

Nand and QSPI are not defined now but this will be extended.
Based on selected bootmode boot_targets are rewritten.
Patch also contains detection if variables are saved. If yes don't
rewrite boot_targets variable.

Also move variable setup to the end of file because SCSI needs to be
defined before others macros are using it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
8 years agoARM64: zynqmp: Remove CONFIG_BOOTP_SERVERIP
Alexander Graf [Wed, 1 Jun 2016 20:41:54 +0000 (22:41 +0200)]
ARM64: zynqmp: Remove CONFIG_BOOTP_SERVERIP

When the CONFIG_BOOTP_SERVERIP option is set, we ignore all
dhcp values for the tftp server and use our own serverip and
file name instead.

This is usually not what we want and I doubt it's set for a
good reason on ZynqMP. It definitely hurts if we want to support
uEFI PXE boot on it. So just remove the option for now.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable AHCI when CONFIG_SATA_CEVA is defined
Michal Simek [Wed, 1 Jun 2016 12:29:33 +0000 (14:29 +0200)]
ARM64: zynqmp: Enable AHCI when CONFIG_SATA_CEVA is defined

Simplify zcu102 board file by moving CONFIG_AHCI enabling to common
file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable support for SPL FIT images
Michal Simek [Tue, 17 May 2016 06:38:53 +0000 (08:38 +0200)]
ARM64: zynqmp: Enable support for SPL FIT images

Enable support for RAM based FIT images read by SPL.
Empty function for now to keep compiler happy.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoenv: Setup GD_FLG_ENV_DEFAULT flag when default environment are used
Michal Simek [Mon, 30 May 2016 14:06:54 +0000 (16:06 +0200)]
env: Setup GD_FLG_ENV_DEFAULT flag when default environment are used

Setup flag when default environment are used to be able to
rewrite default distro boot variables based on SoC boot mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
8 years agoARM64: zynq: Fix boot.bin generation for Zynq and ZynqMP
Michal Simek [Mon, 30 May 2016 12:57:02 +0000 (14:57 +0200)]
ARM64: zynq: Fix boot.bin generation for Zynq and ZynqMP

Fix boot.bin generation for Zynq and ZynqMP.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Marek Vasut <marex@denx.de>
8 years agoARM64: zynqmp: Extend page_table_size
Michal Simek [Mon, 30 May 2016 08:41:26 +0000 (10:41 +0200)]
ARM64: zynqmp: Extend page_table_size

0xc000 is not sufficient page table size if dc4 with 4 gems
is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add support for zc1751-dc4
Michal Simek [Thu, 26 May 2016 06:06:38 +0000 (08:06 +0200)]
ARM64: zynqmp: Add support for zc1751-dc4

zc1751-dc4 contains four GEMs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add debug uart for zc1751-dc2
Michal Simek [Fri, 20 May 2016 07:55:00 +0000 (09:55 +0200)]
ARM64: zynqmp: Add debug uart for zc1751-dc2

Add debug uart for zc1751-dc2.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable Vitesse and RealTek ethernet phys
Michal Simek [Mon, 30 May 2016 08:13:37 +0000 (10:13 +0200)]
ARM64: zynqmp: Enable Vitesse and RealTek ethernet phys

Phys are available on zc1751-dc4 that's why enable them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Move MSR instruction selection to Kconfig
Michal Simek [Tue, 24 May 2016 09:45:11 +0000 (11:45 +0200)]
microblaze: Move MSR instruction selection to Kconfig

Select MSR instructions via Kconfig instead of xparameters.h.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Add option to pass cpu version number
Michal Simek [Tue, 24 May 2016 11:23:59 +0000 (13:23 +0200)]
microblaze: Add option to pass cpu version number

Toolchain can use some flags by default based on cpu version.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomicroblaze: Select compilation flags via Kconfig
Michal Simek [Tue, 24 May 2016 09:42:26 +0000 (11:42 +0200)]
microblaze: Select compilation flags via Kconfig

Remove autogenerated config.mk and select CPU options via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable CMD_NAND via Kconfig
Michal Simek [Fri, 27 May 2016 09:25:49 +0000 (11:25 +0200)]
ARM64: zynqmp: Enable CMD_NAND via Kconfig

Simplify board file by enabling CMD_NAND via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agomtd: nand: arasan_nfc: Correct nand ecc initialization
Siva Durga Prasad Paladugu [Wed, 25 May 2016 09:50:38 +0000 (15:20 +0530)]
mtd: nand: arasan_nfc: Correct nand ecc initialization

Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoarm: lib: Fix fix push/pop-section directives
Marek Vasut [Sat, 4 Jun 2016 22:46:55 +0000 (00:46 +0200)]
arm: lib: Fix fix push/pop-section directives

Repair typos in the previous "arm: lib: fix push/pop-section directives"
patch, which prevented VCMA9 board from building.

Signed-off-by: Marek Vasut <marex@denx.de>
Fixes: b2f1858455e9 ("arm: lib: fix push/pop-section directives")
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stephen Warren <swarren@nvidia.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Sat, 4 Jun 2016 16:12:26 +0000 (12:12 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

8 years agospl: fit: Fix non-matching DT names console output
Andreas Dannenberg [Fri, 3 Jun 2016 19:05:04 +0000 (14:05 -0500)]
spl: fit: Fix non-matching DT names console output

When no DTB can be matched successfully to the board that's being used
a list of available FIT-embedded DTBs will be output to the console for
diagnostic purposes. But rather than the contents of the "description"
FDT property a non-existent property was accessed and as a result "NULL"
was output instead of the actual name(s) of the DTB(s). Fix this issue
by using the correct property which is also the exact same property
that's used earlier during the actual board matching process.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
8 years agoMerge git://git.denx.de/u-boot-nand-flash
Tom Rini [Sat, 4 Jun 2016 12:49:47 +0000 (08:49 -0400)]
Merge git://git.denx.de/u-boot-nand-flash

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Sat, 4 Jun 2016 12:49:08 +0000 (08:49 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agofreescale: Tweak various Makefiles to remove redundancy, fix aesthetics
Robert P. J. Day [Wed, 13 Apr 2016 21:49:28 +0000 (17:49 -0400)]
freescale: Tweak various Makefiles to remove redundancy, fix aesthetics

No intended functional change, just remove redundancies in some
Makefiles, and make whitespace aesthetics uniform.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodm: test: Add GPIO open drain tests
mario.six@gdsys.cc [Wed, 25 May 2016 13:15:23 +0000 (15:15 +0200)]
dm: test: Add GPIO open drain tests

Add some tests for the new open drain setting feature of the GPIO
uclass, and extend the capabilities of the sandbox GPIO driver
accordingly.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodm: gpio: Implement open drain for MPC85XX GPIO
mario.six@gdsys.cc [Wed, 25 May 2016 13:15:22 +0000 (15:15 +0200)]
dm: gpio: Implement open drain for MPC85XX GPIO

This patch implements the open-drain setting feature for the MPC85XX
GPIO controller.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodm: gpio: Add methods for open drain setting
mario.six@gdsys.cc [Wed, 25 May 2016 13:15:21 +0000 (15:15 +0200)]
dm: gpio: Add methods for open drain setting

Certain GPIO devices have the capability to switch their GPIOs into
open-drain mode, that is, instead of actively driving the output
(Push-pull output), the pin is connected to the collector (for a NPN
transistor) or the drain (for a MOSFET) of a transistor, respectively.
The pin then either forms an open circuit or a connection to ground,
depending on the state of the transistor.

This patch adds functions to the GPIO uclass to switch GPIOs to
open-drain mode on devices that support it.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodm: gpio: Add driver for MPC85XX GPIO controller
mario.six@gdsys.cc [Wed, 25 May 2016 13:15:20 +0000 (15:15 +0200)]
dm: gpio: Add driver for MPC85XX GPIO controller

This patch adds a driver for the built-in GPIO controller of the MPC85XX
SoC (probably supporting other PowerQUICC III SoCs as well).

Each GPIO bank is identified by its own entry in the device tree, i.e.

gpio-controller@fc00 {
      #gpio-cells = <2>;
      compatible = "fsl,pq3-gpio";
      reg = <0xfc00 0x100>
}

By default, each bank is assumed to have 32 GPIOs, but the ngpios
setting is honored, so the number of GPIOs for each bank in configurable
to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
the P1022 SoC).

The usual functions of GPIO drivers (setting input/output mode and output
value setting) are supported.

The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.
Robert P. J. Day [Mon, 23 May 2016 10:49:21 +0000 (06:49 -0400)]
arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.

Replace a number of array length calculations with the ARRAY_SIZE()
macro, for clarity.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
Shengzhou Liu [Tue, 31 May 2016 07:39:06 +0000 (15:39 +0800)]
board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot

We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agopowerpc/board: SPL: Enable malloc flag in global data.
Sumit Garg [Wed, 25 May 2016 16:41:48 +0000 (12:41 -0400)]
powerpc/board: SPL: Enable malloc flag in global data.

For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT
flag in global data after allocating memory using mem_malloc_init.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agonand: fix nand torture to use changed mtd api
Max Krummenacher [Mon, 30 May 2016 14:28:28 +0000 (16:28 +0200)]
nand: fix nand torture to use changed mtd api

The mtd subsystem deprecated and renamed the direct use of the mtd_info
struct's functionpointers. Instead the corresponding mtd_xxx function
should be used.

See also:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=3c3c10bba1e4ccb75b41442e45c1a072f6cded19

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
8 years agomtd: nand: Sync with Linux v4.6
Scott Wood [Mon, 30 May 2016 18:57:58 +0000 (13:57 -0500)]
mtd: nand: Sync with Linux v4.6

Updates the NAND code to match Linux v4.6.  The previous sync was from
Linux v4.1 in commit d3963721d93fafa.

Note that none of the individual NAND drivers tracked Linux closely
enough to be synced themselves, other than manually applying a few
cross-tree changes.

Signed-off-by: Scott Wood <oss@buserror.net>
Tested-by: Heiko Schocher <hs@denx.de>
8 years agomtd: nand: Add page argument to write_page() etc.
Scott Wood [Mon, 30 May 2016 18:57:57 +0000 (13:57 -0500)]
mtd: nand: Add page argument to write_page() etc.

This change is part of the Linux 4.6 sync.  It is being done before the
main sync patch in order to make it easier to address the issue across
all NAND drivers (many/most of which do not closely track their Linux
counterparts) separately from other merge issues.

Signed-off-by: Scott Wood <oss@buserror.net>
8 years agomtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data
Scott Wood [Mon, 30 May 2016 18:57:56 +0000 (13:57 -0500)]
mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data

These functions are part of the Linux 4.6 sync.  They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.

Signed-off-by: Scott Wood <oss@buserror.net>
8 years agonand: Embed mtd_info in struct nand_chip
Scott Wood [Mon, 30 May 2016 18:57:55 +0000 (13:57 -0500)]
nand: Embed mtd_info in struct nand_chip

nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.

This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip.  It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].

Signed-off-by: Scott Wood <oss@buserror.net>
8 years agomtd: nand: Remove nand_info_t typedef
Scott Wood [Mon, 30 May 2016 18:57:54 +0000 (13:57 -0500)]
mtd: nand: Remove nand_info_t typedef

This typedef serves no purpose other than causing confusion with
struct nand_chip.

Signed-off-by: Scott Wood <oss@buserror.net>
8 years agomtd: nand: Remove docg4 driver and palmtreo680 flashing tool
Scott Wood [Mon, 30 May 2016 18:57:53 +0000 (13:57 -0500)]
mtd: nand: Remove docg4 driver and palmtreo680 flashing tool

Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only
user of the docg4 driver and the palmtreo680 image flashing tool.  This
patch removes them.

Signed-off-by: Scott Wood <oss@buserror.net>
Cc: Mike Dunn <mikedunn@newsguy.com>
Cc: Simon Glass <sjg@chromium.org>
8 years agomtd: nand: Remove jz4740 driver
Marek Vasut [Mon, 30 May 2016 18:57:52 +0000 (13:57 -0500)]
mtd: nand: Remove jz4740 driver

This driver is not used by anyone, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Scott Wood <oss@buserror.net>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Scott Wood <oss@buserror.net>
8 years agomtd: nand: arasan_nfc: Correct nand ecc initialization
Siva Durga Prasad Paladugu [Wed, 25 May 2016 09:50:38 +0000 (15:20 +0530)]
mtd: nand: arasan_nfc: Correct nand ecc initialization

Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
8 years agousb: move CONFIG_USB_XHCI_DWC3 to Kconfig
Masahiro Yamada [Fri, 3 Jun 2016 22:35:04 +0000 (07:35 +0900)]
usb: move CONFIG_USB_XHCI_DWC3 to Kconfig

Create an entry for "config USB_XHCI_DWC3" in Kconfig and
switch over to it for all boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agousb: move CONFIG_USB_XHCI to Kconfig with renaming
Masahiro Yamada [Fri, 3 Jun 2016 22:35:03 +0000 (07:35 +0900)]
usb: move CONFIG_USB_XHCI to Kconfig with renaming

Move CONFIG_USB_XHCI to defconfig files for all boards, renaming it
into CONFIG_USB_XHCI_HCD.

As commented in the help of "config USB_XHCI" entry, this has been
a TODO for a long time; now CONFIG_USB_XHCI_HCD and CONFIG_USB_XHCI
have been unified in favor of the former.

Note:
Some boards define CONFIG_USB_XHCI in their headers without
CONFIG_USB, which does not meet the "depends on" in Kconfig.
I added CONFIG_USB=y for those boards when converting.
Otherwise, they would fail to build.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoconfigs: blackfin: move CONFIG_USB to defconfig
Masahiro Yamada [Fri, 3 Jun 2016 22:35:02 +0000 (07:35 +0900)]
configs: blackfin: move CONFIG_USB to defconfig

These Blackfin boards are the last ones that define CONFIG_USB in
their headers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agousb: dwc3: Correct datatype of base to unsigned long
Siva Durga Prasad Paladugu [Thu, 12 May 2016 06:57:13 +0000 (08:57 +0200)]
usb: dwc3: Correct datatype of base to unsigned long

Correct type of varibale base to unsigned long as
keeping it as int causes usb failures if MSB of
the base address is set.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoarmv8: ls1012a: Add support of ls1012afrdm board
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:36 +0000 (18:41 +0530)]
armv8: ls1012a: Add support of ls1012afrdm board

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls1012a: Add support of ls1012ardb board
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:35 +0000 (18:41 +0530)]
armv8: ls1012a: Add support of ls1012ardb board

QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls1012a: Add support of ls1012aqds board
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:34 +0000 (18:41 +0530)]
armv8: ls1012a: Add support of ls1012aqds board

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: freescale: common: Add flag for LBMAP brdcfg reg offset
Abhimanyu Saini [Fri, 3 Jun 2016 13:11:33 +0000 (18:41 +0530)]
board: freescale: common: Add flag for LBMAP brdcfg reg offset

Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard: freescale: common: Conditionally compile IFC QXIS func
Abhimanyu Saini [Fri, 3 Jun 2016 13:11:32 +0000 (18:41 +0530)]
board: freescale: common: Conditionally compile IFC QXIS func

Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:31 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.

This patch add support of LS1012A SoC along with
 - Update platform & DDR clock read logic as per SVR
 - Define MMDC controller register set.
 - Update LUT base address for PCIe
 - Avoid L3 platform cache compilation
 - Update USB address, errata
 - SerDes table
 - Added CSU IDs for SDHC2, SAI-1 to SAI-4

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Organize SoC overview at common location
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:30 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Organize SoC overview at common location

SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc

Also move README.lsch2 and README.lsch3 in same folder.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: fix compile warning "rcw_tmp"
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:29 +0000 (18:41 +0530)]
armv8: fsl-layerscape: fix compile warning "rcw_tmp"

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable â€˜rcw_tmp’ [-Wunused-variable]
  u32 rcw_tmp;

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: mtd: spi: Adding support for QSPI flash
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:28 +0000 (18:41 +0530)]
driver: mtd: spi: Adding support for QSPI flash

Serial number, vendor id and page size are added for QSPI flash
common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Avoid LS1043A specifc defines
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:27 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Avoid LS1043A specifc defines

Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Put SMMU config code in SMMU_BASE
Prabhakar Kushwaha [Fri, 3 Jun 2016 13:11:26 +0000 (18:41 +0530)]
armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE

It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.

So put SMMU configuration code under SMMU_BASE.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls1043aqds: fix usb PWRFAULT setting
Shaohui Xie [Mon, 30 May 2016 06:26:55 +0000 (14:26 +0800)]
armv8: ls1043aqds: fix usb PWRFAULT setting

SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should
be used for USB 3 & 2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver/ddr/fsl: Check condition for erratum A-009803
Shengzhou Liu [Wed, 25 May 2016 08:15:00 +0000 (16:15 +0800)]
driver/ddr/fsl: Check condition for erratum A-009803

Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/ddr/fsl: Disabling data init if ECC is not enabled
York Sun [Thu, 26 May 2016 19:19:03 +0000 (12:19 -0700)]
drivers/ddr/fsl: Disabling data init if ECC is not enabled

If ECC is not enabled, data init can be disabled to speed up booting.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoboard: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined
York Sun [Thu, 26 May 2016 20:59:03 +0000 (13:59 -0700)]
board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined

U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agopcie/layerscape: fix bug in bus number computation when setting msi-map
Bogdan Purcareata [Tue, 17 May 2016 07:18:40 +0000 (07:18 +0000)]
pcie/layerscape: fix bug in bus number computation when setting msi-map

When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in
computing the bus number.

The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A
given bus number is relative to hose->first_busno, so that has to be
subtracted from the PCI device id.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Acked-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/ddr/fsl: Fix timing_cfg_2 register
York Sun [Thu, 19 May 2016 04:11:19 +0000 (21:11 -0700)]
drivers/ddr/fsl: Fix timing_cfg_2 register

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoboard: ls102xa: Fix ICID setup
Vincent Siles [Wed, 18 May 2016 12:41:14 +0000 (14:41 +0200)]
board: ls102xa: Fix ICID setup

LS102A ref manual dictates that ICID have to be written to the MSB
of the ICID register, not to the LSB.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
8 years agommc: fsl_esdhc: fix check_and_invalidate_dcache_range function
Yangbo Lu [Thu, 12 May 2016 11:12:58 +0000 (19:12 +0800)]
mmc: fsl_esdhc: fix check_and_invalidate_dcache_range function

In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboard/freescale: Update ddr clk_adjust
Shengzhou Liu [Wed, 4 May 2016 02:20:22 +0000 (10:20 +0800)]
board/freescale: Update ddr clk_adjust

This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
Shengzhou Liu [Wed, 4 May 2016 02:20:21 +0000 (10:20 +0800)]
drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Fri, 3 Jun 2016 20:30:47 +0000 (16:30 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra

8 years agoarm: lib: fix push/pop-section directives
Stephen Warren [Fri, 3 Jun 2016 19:05:11 +0000 (13:05 -0600)]
arm: lib: fix push/pop-section directives

With the existing code, function symbols are defined in .text, and the
body is defined in .text.xxx. This causes (at least some version of) the
linker not to emit the function body into the final binary, since it's
part of a different section to the symbols being referenced. This of
course causes a wide variety of failures.

This change moves the push/pop-section directives before the function
symbols, and after any relate ENDPROC macro invocations, so that symbols
and bodies are all in the "pushed" sections, and thus the function bodies
are emitted into the binary.

This solves (at least) the boot problems currently seen on Tegra systems
that use SPL (i.e. all ARMv7 Tegras).

Fixes: 13b0a91a6d48 ("arm: lib: Split asm symbols into different .text subsections")
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Fri, 3 Jun 2016 01:42:23 +0000 (21:42 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

8 years agoARM: k2g: Configure reset mux to device reset
Lokesh Vutla [Thu, 26 May 2016 13:35:44 +0000 (19:05 +0530)]
ARM: k2g: Configure reset mux to device reset

BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.

Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.

Right now to give a default watchdog behaviour "Device reset" is
being selected.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
8 years agoarm: am57xx: Fix alignment where necessary
Keerthy [Tue, 24 May 2016 06:15:07 +0000 (11:45 +0530)]
arm: am57xx: Fix alignment where necessary

This just fixes alignment for better readability.

Signed-off-by: Keerthy <j-keerthy@ti.com>
8 years agoarm: am57xx: Fix omap_vcores assignment for am572x-idk
Keerthy [Tue, 24 May 2016 06:15:06 +0000 (11:45 +0530)]
arm: am57xx: Fix omap_vcores assignment for am572x-idk

Currently omap_vcores is wrongly assigned a default value of
beagle_x15_volts. Hence populating a new structure for am572x-idk
and assigning it to omap_vcores in the vcores_init function.

Fixes: c020d355c45ed40fe12a ("board: ti: am57xx: Add support for am572x idk in SPL")
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
8 years agoarm: omap: Introduce vcores_init function
Keerthy [Tue, 24 May 2016 06:15:05 +0000 (11:45 +0530)]
arm: omap: Introduce vcores_init function

The pmic registers for variants of am57xx boards are different
hence we need to assign them carefully based on the board type.
Add a function to assign omap_vcores after the board detection.

Signed-off-by: Keerthy <j-keerthy@ti.com>
8 years agoARM: DRA7: Add macros for voltage values for all OPPs
Anna, Suman [Mon, 23 May 2016 18:32:17 +0000 (13:32 -0500)]
ARM: DRA7: Add macros for voltage values for all OPPs

Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros are defined for VD_MPU and VD_CORE at OPP_OD
and OPP_HIGH as these use the same values as OPP_NOM.

The current macros will be used as common macros that can be
redefined appropriately based on a selected OPP configuration
at build time.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: DRA7: Consolidate voltage macros across different SoCs
Anna, Suman [Mon, 23 May 2016 18:32:16 +0000 (13:32 -0500)]
ARM: DRA7: Consolidate voltage macros across different SoCs

The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.

This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: DRA7: Define common macros for efuse register offsets
Anna, Suman [Mon, 23 May 2016 18:32:15 +0000 (13:32 -0500)]
ARM: DRA7: Define common macros for efuse register offsets

Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values
Anna, Suman [Mon, 23 May 2016 18:32:14 +0000 (13:32 -0500)]
ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values

The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.

The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agousb: phy: omap_usb_phy: Fix USB3_PHY DPLL configuration
Roger Quadros [Mon, 23 May 2016 14:37:50 +0000 (17:37 +0300)]
usb: phy: omap_usb_phy: Fix USB3_PHY DPLL configuration

The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.

This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.

Signed-off-by: Roger Quadros <rogerq@ti.com>
8 years agodra7xx: Enable USB_PHY3 32KHz clock
Roger Quadros [Mon, 23 May 2016 14:37:49 +0000 (17:37 +0300)]
dra7xx: Enable USB_PHY3 32KHz clock

DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.

Signed-off-by: Roger Quadros <rogerq@ti.com>
8 years agoARM: AM57xx: AM43xx: Fix USB host
Roger Quadros [Mon, 23 May 2016 14:37:48 +0000 (17:37 +0300)]
ARM: AM57xx: AM43xx: Fix USB host

CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.

Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.

Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks")
Signed-off-by: Roger Quadros <rogerq@ti.com>
8 years agoARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAP
Roger Quadros [Mon, 23 May 2016 14:37:47 +0000 (17:37 +0300)]
ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAP

CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.

Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks"
Signed-off-by: Roger Quadros <rogerq@ti.com>
8 years agolib: Enable private libgcc by default
Marek Vasut [Thu, 26 May 2016 16:01:47 +0000 (18:01 +0200)]
lib: Enable private libgcc by default

This patch decouples U-Boot binary from the toolchain on systems where
private libgcc is available. Instead of pulling in functions provided
by the libgcc from the toolchain, U-Boot will use it's own set of libgcc
functions. These functions are usually imported from Linux kernel, which
also uses it's own libgcc functions instead of the ones provided by the
toolchain.

This patch solves a rather common problem. The toolchain can usually
generate code for many variants of target architecture and often even
different endianness. The libgcc on the other hand is usually compiled
for one particular configuration and the functions provided by it may
or may not be suited for use in U-Boot. This can manifest in two ways,
either the U-Boot fails to compile altogether and linker will complain
or, in the much worse case, the resulting U-Boot will build, but will
misbehave in very subtle and hard to debug ways.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Split asm symbols into different .text subsections
Marek Vasut [Thu, 26 May 2016 16:01:46 +0000 (18:01 +0200)]
arm: lib: Split asm symbols into different .text subsections

Split each symbol in lib1funcs into different .text.foo section instead
of placing all of them into plain .text . This allows the linker to collect
and discard unused assembler symbols.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Import Thumb1 functions
Marek Vasut [Thu, 26 May 2016 16:01:45 +0000 (18:01 +0200)]
arm: lib: Import Thumb1 functions

Import functions into lib1funcs.S which are required for Thumb1
build. These functions come from gcc 5.3.1 release.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: import muldi3.S from Linux
Marek Vasut [Thu, 26 May 2016 16:01:44 +0000 (18:01 +0200)]
arm: lib: import muldi3.S from Linux

Import muldi3.S from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This file implements __aeabi_lmul and it's alias __muldi3, which
is needed when doing Thumb1 builds.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Repair Warning: conditional infixes are deprecated in unified syntax
Marek Vasut [Thu, 26 May 2016 16:01:43 +0000 (18:01 +0200)]
arm: lib: Repair Warning: conditional infixes are deprecated in unified syntax

Fix the following warning when building for thumb2 target by tweaking the
instruction syntax:

Warning: conditional infixes are deprecated in unified syntax

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Import __do_div64 from Linux
Marek Vasut [Thu, 26 May 2016 16:01:42 +0000 (18:01 +0200)]
arm: lib: Import __do_div64 from Linux

Import __do_div64 from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This function is for some toolchains, which generate _udivmoddi4()
for 64 bit division.

Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Fix uldivmod.S build on Thumb2
Marek Vasut [Thu, 26 May 2016 16:01:41 +0000 (18:01 +0200)]
arm: lib: Fix uldivmod.S build on Thumb2

This assembler source won't build in Thumb2 mode, so fix it adding
the necessary Thumb2 conditional macros from unified.h .

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Sync libgcc 32b division/modulo operations
Marek Vasut [Thu, 26 May 2016 16:01:40 +0000 (18:01 +0200)]
arm: lib: Sync libgcc 32b division/modulo operations

Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 ,
commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these
four files are present in lib1funcs.S in Linux, so replace these files
with lib1funcs.S from Linux.

Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro
in lib1funcs.S . Moreover, to make all of the functions available, define
CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM
EABI.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Sync libgcc shift operations
Marek Vasut [Thu, 26 May 2016 16:01:39 +0000 (18:01 +0200)]
arm: lib: Sync libgcc shift operations

Sync the libgcc shift operations with Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three
files is easy, as there is almost no change in them, except the
addition of Thumb support.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: lib: Drop underscore from private libgcc filenames
Marek Vasut [Thu, 26 May 2016 16:01:38 +0000 (18:01 +0200)]
arm: lib: Drop underscore from private libgcc filenames

Drop the underscore from the filenames of files implementing libgcc
routines. There is no functional change. This change is done to make
sync with Linux kernel easier.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: include: Import unified.h from Linux kernel
Marek Vasut [Thu, 26 May 2016 16:01:37 +0000 (18:01 +0200)]
arm: include: Import unified.h from Linux kernel

Import unified.h from Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains
macros used in libgcc functions in Linux kernel on ARM and will be
needed for the libgcc sync.

Since unified.h defines the W(instr) macro, we must drop this from
the macro from memcpy.S , otherwise this triggers a warning about
symbol redefinition. In order to keep the changes to unified.h to
the minimum, tweak arch/arm/lib/Makefile such that it defines the
CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all
of the assembler files. This is mandatory.

Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and
only if Thumb2 build is enabled. This macro is checked by unified.h
and toggles between ARM and Thumb2 variant of the instructions in the
assembler source files.

Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the
new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between
more optimal and more dense codepaths which work on armv5 and newer
and less optimal codepaths which work on armv4 and possible armv3m.
Tegra2 needs the same special handling as it does in arch/arm/Makefile
to cater for the arm720t boot core.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: config: Introduce CONFIG_SYS_ARM_ARCH
Marek Vasut [Thu, 26 May 2016 16:01:36 +0000 (18:01 +0200)]
arm: config: Introduce CONFIG_SYS_ARM_ARCH

Introduce new helper Kconfig option, which is automatically set to
the version of ARM architecture for which the U-Boot is built. This
is useful when selecting tuning options in the libgcc imported from
Linux kernel.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: omap: Enable tiny printf on omap3_logic
Marek Vasut [Tue, 31 May 2016 21:12:47 +0000 (23:12 +0200)]
ARM: omap: Enable tiny printf on omap3_logic

Enable support for tiny printf on the omap3_logic board to trim down
the SPL size. This makes the SPL actually build again and fit into
the SRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: lesne@alse-fr.com
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agotiny-printf: Support sprintf()
Marek Vasut [Tue, 31 May 2016 21:12:46 +0000 (23:12 +0200)]
tiny-printf: Support sprintf()

Add a simple version of this function for SPL. It does not check the buffer
size as this would add to the code size.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: lesne@alse-fr.com
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sylvain Lesne <lesne@alse-fr.com>
Tested-by: Sylvain Lesne <lesne@alse-fr.com>
8 years agoarm: Select CONFIG_ARM64 for Cavium ThunderX
Marek Vasut [Wed, 1 Jun 2016 00:33:53 +0000 (02:33 +0200)]
arm: Select CONFIG_ARM64 for Cavium ThunderX

Select the config option, since this board is ARM64.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>