oweals/u-boot.git
6 years agoconfigs: gurnard: Move CONFIG_ATMEL_SPI to defconfigs
Jagan Teki [Wed, 14 Mar 2018 13:16:33 +0000 (18:46 +0530)]
configs: gurnard: Move CONFIG_ATMEL_SPI to defconfigs

Now CONFIG_ATMEL_SPI is defined in Kconfig, so move the
same into defconfig file.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
6 years agoat91: gurnard: Enable DM_SPI
Jagan Teki [Wed, 14 Mar 2018 13:16:32 +0000 (18:46 +0530)]
at91: gurnard: Enable DM_SPI

Enable DM_SPI for atmel SPI driver on gurnard board.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
6 years agospi: atmel: Add ifdef for DM_GPIO code
Jagan Teki [Wed, 14 Mar 2018 13:16:31 +0000 (18:46 +0530)]
spi: atmel: Add ifdef for DM_GPIO code

Few boards are configuring gpio directly from board instead
using drivers/gpio so add ifdef for DM_GPIO to compatible
for both the cases.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
6 years agoMerge tag 'signed-rpi-next' of git://github.com/agraf/u-boot
Tom Rini [Fri, 6 Apr 2018 12:30:10 +0000 (08:30 -0400)]
Merge tag 'signed-rpi-next' of git://github.com/agraf/u-boot

Patch queue for rpi - 2018-04-06

Highlights this time around:

  - Support for new RPi3 B+ model
  - Fix for some SD cards on newer RPi firmware

6 years agorpi: Complete table of models with new revision code scheme
Jonathan Gray [Fri, 6 Apr 2018 08:45:49 +0000 (18:45 +1000)]
rpi: Complete table of models with new revision code scheme

In the model table for the new revision code encoding documented in
https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
add the entries for old models with the new scheme and add CM3 which
only appears in the new scheme.

A device tree for CM3 is not currently upstreamed in linux.  When that
happens the name will likely have to be adjusted in the table.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
6 years agommc: use core clock frequency in bcm2835 sdhost
Jonathan Gray [Sat, 17 Mar 2018 05:15:48 +0000 (16:15 +1100)]
mmc: use core clock frequency in bcm2835 sdhost

In raspberrypi-firmware 7fdcd00e00a42a1c91e8bd6f5eb8352fe9358557 and
later start.elf now sets the EMMC clock to 200 MHz.

According to Phil Elwell in
https://github.com/raspberrypi/firmware/issues/953
the SDHost controller shares the core/VPU clock and doesn't use
the EMMC clock.

Use the core clock id when determining the frequency to allow
U-Boot to work with recent versions of raspberrypi-firmware.
Otherwise U-Boot hangs at:

U-Boot 2018.03 (Mar 14 2018 - 20:36:00 +1100)

DRAM:  948 MiB
RPI 3 Model B (0xa02082)
MMC:   mmc@7e202000: 0, sdhci@7e300000: 1
Loading Environment from FAT...

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
6 years agorpi3_32b: Enable lan78xx driver
Peter Robinson [Fri, 16 Mar 2018 06:26:29 +0000 (06:26 +0000)]
rpi3_32b: Enable lan78xx driver

The new Raspberry Pi B 3+ has a lan78xx device attached to it. Let's add
driver support in U-Boot for it.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
6 years agorpi: Add identifier for the new RPi3 B+
Alexander Graf [Thu, 15 Mar 2018 14:05:37 +0000 (15:05 +0100)]
rpi: Add identifier for the new RPi3 B+

The Raspberr Pi Foundation released a new RPi3 version which we want
to detect as well, so we can enable ethernet on it and know the correct
device tree file name.

Add an identifier for it.

Signed-off-by: Alexander Graf <agraf@suse.de>
6 years agorpi3: Enable lan78xx driver
Alexander Graf [Thu, 15 Mar 2018 14:05:36 +0000 (15:05 +0100)]
rpi3: Enable lan78xx driver

The new Raspberry Pi B 3+ has a lan78xx device attached to it. Let's add
driver support in U-Boot for it.

Signed-off-by: Alexander Graf <agraf@suse.de>
6 years agorpi: Allow to boot without serial
Alexander Graf [Thu, 5 Apr 2018 09:36:22 +0000 (11:36 +0200)]
rpi: Allow to boot without serial

When we enable CONFIG_OF_BOARD on Raspberry Pis, we may end up without
serial console support in early boot. Hence we need to make the serial
port optional, otherwise we will never get to the point where serial
would be probed.

Signed-off-by: Alexander Graf <agraf@suse.de>
6 years agoMerge git://git.denx.de/u-boot-sunxi
Tom Rini [Wed, 4 Apr 2018 13:18:38 +0000 (09:18 -0400)]
Merge git://git.denx.de/u-boot-sunxi

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoRevert "sunxi: Pine64: temporarily remove extra Pine64 non-plus DT"
Andre Przywara [Wed, 4 Apr 2018 00:31:23 +0000 (01:31 +0100)]
Revert "sunxi: Pine64: temporarily remove extra Pine64 non-plus DT"

Now with the MMC environment gone, we have enough space to accommodate
the Pine64 "non-plus" .dtb again.

This reverts commit 47952b8e42c2790150e16d3d4235b3a1ee0ba9bb.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agosunxi: revert disabling of features
Andre Przywara [Wed, 4 Apr 2018 00:31:22 +0000 (01:31 +0100)]
sunxi: revert disabling of features

In January some commits were introduced to mitigate the U-Boot image
size issues we encountered on sunxi builds.
Now with the MMC environment removed we can bring them back, as we
practically don't have a size limit anymore.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agosunxi: disable direct MMC environment
Andre Przywara [Wed, 4 Apr 2018 00:31:21 +0000 (01:31 +0100)]
sunxi: disable direct MMC environment

Since the dawn of time for the Allwinner support in mainline U-Boot
we store the environment to the SD card and write directly at
544KB from the beginning of the device. This leads to problems when
the U-Boot proper image grows beyond 504KB and eventually overlaps.
With one release of having the environment preferably in a FAT
partition, let's now turn off the MMC variant fallback, so we get back
all the space we need to implement features.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agonet: sun8i-emac: remove support for old binding
Andre Przywara [Wed, 4 Apr 2018 00:31:20 +0000 (01:31 +0100)]
net: sun8i-emac: remove support for old binding

The original DT binding used by U-Boot's sun8i-emac driver was not really
agreed upon, and deviated from the "official" binding now used by the
kernel. Since now all U-Boot users have been converted to the new
binding, we can remove support for the old DT nodes from the driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoarm: dts: sunxi: update H5 to new EMAC binding
Andre Przywara [Wed, 4 Apr 2018 00:31:19 +0000 (01:31 +0100)]
arm: dts: sunxi: update H5 to new EMAC binding

The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used by the
OrangePi PC2 over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoarm: dts: sunxi: update H3 to new EMAC binding
Andre Przywara [Wed, 4 Apr 2018 00:31:18 +0000 (01:31 +0100)]
arm: dts: sunxi: update H3 to new EMAC binding

The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used by the
various H3 boards over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoarm: dts: sunxi: update A64 to new EMAC binding
Andre Przywara [Wed, 4 Apr 2018 00:31:17 +0000 (01:31 +0100)]
arm: dts: sunxi: update A64 to new EMAC binding

The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used for the
Pine64+ board over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agonet: sun8i-emac: add support for new EMAC DT binding
Andre Przywara [Wed, 4 Apr 2018 00:31:16 +0000 (01:31 +0100)]
net: sun8i-emac: add support for new EMAC DT binding

The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an
upstream Linux driver in v4.15.
This one uses a slightly different binding from the original one used
by the U-Boot driver.
The differences to the old binding are:
- The "syscon" address is held in a separate node, referenced via a
  phandle in the "syscon" property.
- The reference to the PHY is held in a property called "phy-handle",
  not "phy".
- The PHY register is at offset 0x30 in the syscon device, not at 0.
- The internal PHY is activated when the node, which phy-handle points
  to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node.

Teach the U-Boot driver how to find its resources in a "new-style" DT,
so that we can use a Linux kernel compatible DT for U-Boot as well.
This keeps support for the old binding for now, to allow a smooth
transition.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agonet: sun8i-emac: support new pinctrl DT bindings
Andre Przywara [Wed, 4 Apr 2018 00:31:15 +0000 (01:31 +0100)]
net: sun8i-emac: support new pinctrl DT bindings

The Linux kernel driver for the Allwinner pin controller gained support
for generic properties, which are now also used in the DTs.
The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from
the DT, but so far only supported the old binding.
Update the parsing routine to cope with both the old and new bindings,
so that the newer DTs can be used with U-Boot and its Ethernet driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agosunxi: gpio: add missing compatible strings
Andre Przywara [Wed, 4 Apr 2018 00:31:14 +0000 (01:31 +0100)]
sunxi: gpio: add missing compatible strings

The sunxi GPIO driver is missing some compatible strings for recent
SoCs. While most of the sunxi GPIO code seems to not rely on this (and
so works anyway), the sunxi_name_to_gpio() function does and fails at
the moment (for instance when resolving the MMC CD pin name).
Add the compatible strings for the A64 and V3s, which were missing
from the list. This now covers all pinctrl nodes in our own DTs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agosunxi: README.sunxi64: Add hint about non-debug of ARM Trusted Firmware
Andre Przywara [Wed, 4 Apr 2018 00:31:13 +0000 (01:31 +0100)]
sunxi: README.sunxi64: Add hint about non-debug of ARM Trusted Firmware

As we are running into issues where the final U-Boot FIT image file is
exceeding our size limit, add a hint to the README.sunxi64 file
to point out the possibility of building non-debug versions of the ATF
binary. These are about 12KB smaller than the standard debug build, and
so allow successful U-Boot builds for many boards with the Allwinner H5
SoC.
Please note that under normal circumstances the debug build is still
recommended, as it gives valuable clues in case something goes wrong in
the ATF.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoMakefile: Disable stack-usage check for ARC
Alexey Brodkin [Mon, 2 Apr 2018 09:18:02 +0000 (12:18 +0300)]
Makefile: Disable stack-usage check for ARC

With the most recent tools for ARC (arc-2017.09) in case of
"naked" function compiler throws a warning:
---------------------------------->8-----------------------------
board/synopsys/hsdk/hsdk.c: In function 'hsdk_core_init_f':
board/synopsys/hsdk/hsdk.c:345:1: warning: stack usage computation not supported for this target
 }
 ^
---------------------------------->8-----------------------------

That happens because the compiler doesn't handle "naked" functions
as a special case where stack calculation shouldn't be done.

But for now until this is fixed in GCC to get clean buildman output
we're disabling stack-usage check for ARC.

See https://lists.denx.de/pipermail/u-boot/2018-April/324455.html
for more background.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
6 years agoMerge tag 'arc-for-2018.05' of git://git.denx.de/u-boot-arc
Tom Rini [Tue, 3 Apr 2018 12:33:15 +0000 (08:33 -0400)]
Merge tag 'arc-for-2018.05' of git://git.denx.de/u-boot-arc

More ARC changes and fixes for v2018.05

 * Update of ARC tools to the most recent arc-2017.09
 * Fix for compile-time warning for AXS10x
 * Add support of platform-specific commands for HSDK
 * Add support for on-board SPI flash on HSDK
   Note though that for write support another series [1]
   is required. I hope that Jagan will be able to review and
   act on SPI flash improvement series before we get beyond RC1.

   Also note that to get clean build for HSDK we need to disable
   stack-usage check [2] as our current GCC erroneously tries to calculate
   stack-usage on a naked function which leads to warning.

[1] https://patchwork.ozlabs.org/project/uboot/list/?series=35796
[2] https://patchwork.ozlabs.org/patch/894139/

6 years agoconfigs: add NAND support for NES Classic
Miquel Raynal [Wed, 28 Feb 2018 19:52:02 +0000 (20:52 +0100)]
configs: add NAND support for NES Classic

Add NAND parameters to the Nintendo NES Classic configuration file which
features a Macronix NAND flash chip with 128kiB blocks of 2kiB pages
plus 64 OOB bytes.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agosunxi: move the NAND parameters to Kconfig
Miquel Raynal [Wed, 28 Feb 2018 19:52:01 +0000 (20:52 +0100)]
sunxi: move the NAND parameters to Kconfig

Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.

It would have been better to convert this defconfig entry to Kconfig for
all supported machines/architectures but it has been abandoned due to a
fairly high amount of errors reported by the moveconfig.py tool. This is
due to defines quite often being multiplications of values/other defines
not correctly handled.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agosunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig
Miquel Raynal [Wed, 28 Feb 2018 19:52:00 +0000 (20:52 +0100)]
sunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig

Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agosunxi: automatically select SPL_NAND_SUPPORT in Kconfig
Miquel Raynal [Wed, 28 Feb 2018 19:51:59 +0000 (20:51 +0100)]
sunxi: automatically select SPL_NAND_SUPPORT in Kconfig

Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND support.

For now, the only board using it is the CHIP pro.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agosunxi: dts: enable NAND on NES classic
Miquel Raynal [Wed, 28 Feb 2018 19:51:58 +0000 (20:51 +0100)]
sunxi: dts: enable NAND on NES classic

Let the Nintendo NES Classic use the Macronix NAND chip on it.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agosunxi: allow NAND support to be compiled for sun8i platforms
Miquel Raynal [Wed, 28 Feb 2018 19:51:57 +0000 (20:51 +0100)]
sunxi: allow NAND support to be compiled for sun8i platforms

Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agosunxi: spl: remove DMA related settings of the NAND controller
Miquel Raynal [Wed, 28 Feb 2018 19:51:56 +0000 (20:51 +0100)]
sunxi: spl: remove DMA related settings of the NAND controller

Code has been changed to do not use DMA anymore with the NAND
controller, instead PIO is used. Then, DMA-specific initialization may
be dropped.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: use PIO instead of DMA
Miquel Raynal [Wed, 28 Feb 2018 19:51:55 +0000 (20:51 +0100)]
spl: nand: sunxi: use PIO instead of DMA

SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.

Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.

There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.

The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: declare the ecc_bytes array globally
Miquel Raynal [Wed, 28 Feb 2018 19:51:54 +0000 (20:51 +0100)]
spl: nand: sunxi: declare the ecc_bytes array globally

Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agosunxi: spl: deassert the NAND controller reset line
Miquel Raynal [Wed, 28 Feb 2018 19:51:53 +0000 (20:51 +0100)]
sunxi: spl: deassert the NAND controller reset line

Ensure the NAND controller reset line is deasserted before use.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: make the reset column helper more generic
Miquel Raynal [Wed, 28 Feb 2018 19:51:52 +0000 (20:51 +0100)]
spl: nand: sunxi: make the reset column helper more generic

Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: ensure enough time has passed after changing the column
Miquel Raynal [Wed, 28 Feb 2018 19:51:51 +0000 (20:51 +0100)]
spl: nand: sunxi: ensure enough time has passed after changing the column

When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: create an helper to handle command execution
Miquel Raynal [Wed, 28 Feb 2018 19:51:50 +0000 (20:51 +0100)]
spl: nand: sunxi: create an helper to handle command execution

Executing a command is matter of always doing the following sequence:
  * Waiting for the FIFO to be empty so we can fill it with the new
    command.
  * Clearing the status register.
  * Writing the command in the FIFO.
  * Waiting for the command to finish.

Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: add missing status clear
Miquel Raynal [Wed, 28 Feb 2018 19:51:49 +0000 (20:51 +0100)]
spl: nand: sunxi: add missing status clear

It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper
Miquel Raynal [Wed, 28 Feb 2018 19:51:48 +0000 (20:51 +0100)]
spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper

One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.

Add this sanity check before starting any new command.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: introduce the nand_wait_int() helper
Miquel Raynal [Wed, 28 Feb 2018 19:51:47 +0000 (20:51 +0100)]
spl: nand: sunxi: introduce the nand_wait_int() helper

The pattern of polling on a status register until a bit is set or a
timeout occurs is repeated multiple times in the driver. Mutualize the
code by introducing the nand_wait_int() helper that does wait for the
bit to flip or returns an error in case of timeout.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: fix typo on register name
Miquel Raynal [Wed, 28 Feb 2018 19:51:46 +0000 (20:51 +0100)]
spl: nand: sunxi: fix typo on register name

Change NFC_SEND_ADR to NFC_SEND_ADDR.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: nand: sunxi: fix second case of modulo by zero error
Miquel Raynal [Wed, 28 Feb 2018 19:51:45 +0000 (20:51 +0100)]
spl: nand: sunxi: fix second case of modulo by zero error

In the nand_read_buffer() step, the seed is calculated by doing a modulo
by conf->nseeds which is always zero when not using the randomizer (most
of SLC NANDs).

This situation turns out to lead to a run time freeze with certain
toolchains.

Derive this seed only when the randomizer is enabled (and conf->nseeds
logically not zero), exactly like what has been done before with an
identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo
by zero error").

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agomtd: nand: sunxi: fix ECC strength choice
Miquel Raynal [Wed, 28 Feb 2018 19:51:44 +0000 (20:51 +0100)]
mtd: nand: sunxi: fix ECC strength choice

When the requested ECC strength does not exactly match the strengths
supported by the ECC engine, the driver is selecting the closest
strength meeting the 'selected_strength > requested_strength'
constraint. Fix the fact that, in this particular case, ecc->strength
value was not updated to match the 'selected_strength'.

For instance, one can encounter this issue when no ECC requirement is
filled in the device tree while the NAND chip minimum requirement is not
a strength/step_size combo natively supported by the ECC engine.

Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agospl: fix binman_sym output check
Miquel Raynal [Wed, 28 Feb 2018 19:51:43 +0000 (20:51 +0100)]
spl: fix binman_sym output check

A previous commit introduced the use of binman in the SPL.

After the binman_sym call over the 'pos' symbol, the output value is
checked against BINMAN_SYM_MISSING (-1UL). According to the
documentation (tools/binman/README), when it comes to the 'pos'
attribute:

pos:
This sets the position of an entry within the image. The first
byte of the image is normally at position 0. If 'pos' is not
provided, binman sets it to the end of the previous region, or
the start of the image's entry area (normally 0) if there is no
previous region.

So instead of checking if the return value is BINMAN_SYM_MISSING, we
should also check if the value is not null.

The failure happens when using both the SPL file and the U-Boot file
independently instead of the concatenated file (SPL + padding + U-Boot).
This is because the U-Boot binary file alone does not have the U-Boot
header while it is present in the concatenation file. Not having the
header forces the SPL to discover where it should load U-Boot. The
binman_sym call is supposed to do that but fails. Because of the wrong
check, the destination address was set to 0 while it should have been
somewhere in RAM. This, obviously, stalls the board.

Fixes: 8bee2d251afb ("binman: Add binman symbol support to SPL")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
6 years agoPrepare v2018.05-rc1 v2018.05-rc1
Tom Rini [Tue, 3 Apr 2018 00:31:36 +0000 (20:31 -0400)]
Prepare v2018.05-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoARC: HSDK: Enable SPI flash support
Eugeniy Paltsev [Mon, 26 Mar 2018 12:57:38 +0000 (15:57 +0300)]
ARC: HSDK: Enable SPI flash support

HSDK board has sst26wf016 SPI flash IC which we want to support.

Add SPI controller, CS-gpio and SPI flash nodes to hsdk device tree.
Enable corresponding options in hsdk defconfig.

For SPI write functionality to work we need [1] which
adds support of sst26xxx ICs.

[1] https://patchwork.ozlabs.org/project/uboot/list/?series=35796

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoARC: HSDK: Add platform-specific commands
Eugeniy Paltsev [Mon, 26 Mar 2018 12:57:37 +0000 (15:57 +0300)]
ARC: HSDK: Add platform-specific commands

This patch add support of hsdk platform-specific commands:

hsdk_clock set - set clock from axi_freq, cpu_freq and tun_freq
environment variables/command line arguments

hsdk_clock get - save clock frequencies to axi_freq, cpu_freq
and tun_freq environment variables

hsdk_clock print - show CPU, AXI, DDR and TUNNEL current
clock frequencies.

hsdk_clock print_all - show all currently used clock frequencies.

hsdk_init - setup board HW in one of pre-defined configuration
(hsdk_hs34 / hsdk_hs36 / hsdk_hs36_ccm / hsdk_hs38 /
hsdk_hs38_ccm / hsdk_hs38x2 / hsdk_hs38x3 / hsdk_hs38x4)

hsdk_go - run baremetal application on hsdk configured
by hsdk_init command.

This patch changes default behaviour of 'bootm' command:
now we are able to set number of CPUs to be kicked by setting
'core_mask' environment variable before 'bootm' command run.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoARC: Bump ARC tools used in TravisCI to the most recent release arc-2017.09
Alexey Brodkin [Fri, 30 Mar 2018 13:34:55 +0000 (16:34 +0300)]
ARC: Bump ARC tools used in TravisCI to the most recent release arc-2017.09

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoARC: AXS10x: DTS: Remove unused interrupt properties
Eugeniy Paltsev [Tue, 23 Jan 2018 14:03:15 +0000 (17:03 +0300)]
ARC: AXS10x: DTS: Remove unused interrupt properties

Some device tree nodes (like ethernet, ohci, ehci) in axs10x_mb.dtsi
were copied from linux device tree, so they have interrupts properties.
As we don't use interrupts in uboot we don't have interrupt controller
node in AXS10x device tree. In result we get warnings when we compile
such device tree.

So remove unused interrupts properties to get rid of this warnings.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Mon, 2 Apr 2018 00:36:39 +0000 (20:36 -0400)]
Merge git://git.denx.de/u-boot-dm

6 years agoimage.h: add forward declaration of struct fdt_region
Masahiro Yamada [Wed, 21 Mar 2018 09:03:35 +0000 (18:03 +0900)]
image.h: add forward declaration of struct fdt_region

This header needs to know 'fdt_region' is a struct for the
fit_region_make_list() prototype.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agofdt_region: remove unneeded fdt_internal.h inclusion
Masahiro Yamada [Wed, 21 Mar 2018 09:03:34 +0000 (18:03 +0900)]
fdt_region: remove unneeded fdt_internal.h inclusion

fdt_region.c does not depend on anything in libfdt_internal.h

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agolibfdt: move FDT_RAMDISK_OVERHEAD to image-fdt.c
Masahiro Yamada [Wed, 21 Mar 2018 09:03:33 +0000 (18:03 +0900)]
libfdt: move FDT_RAMDISK_OVERHEAD to image-fdt.c

This macro is locally referenced in common/image-fdt.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agocore: ofnode: Fix translation for #size-cells == 0
Mario Six [Mon, 12 Mar 2018 13:53:33 +0000 (14:53 +0100)]
core: ofnode: Fix translation for #size-cells == 0

Commit 286ede6 ("drivers: core: Add translation in live tree case") made
dev_get_addr always use proper bus translations for addresses read from
the device tree. But this leads to problems with certain busses, e.g.
I2C busses, which run into an error during translation, and hence stop
working.

It turns out that of_translate_address() and fdt_translate_address()
stop the address translation with an error when they're asked to
translate addresses for busses where #size-cells == 0 (comment from
drivers/core/of_addr.c):

 * Note: We consider that crossing any level with #size-cells == 0 to mean
 * that translation is impossible (that is we are not dealing with a value
 * that can be mapped to a cpu physical address). This is not really specified
 * that way, but this is traditionally the way IBM at least do things

To fix this case, we check in both the live-tree and non-live tree-case,
whether the bus of the device whose address is about to be translated
has size-cell size zero. If this is the case, we just read the address
as a plain integer and return it, and only apply bus translations if the
size-cell size if greater than zero.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Reported-by: Martin Fuzzey <mfuzzey@parkeon.com>
Fixes: 286ede6 ("drivers: core: Add translation in live tree case")
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agodm: core: make fixed-clock dt scan live dt compatible
Andy Yan [Thu, 1 Mar 2018 06:08:15 +0000 (14:08 +0800)]
dm: core: make fixed-clock dt scan live dt compatible

dm_scan_fdt_node can't work when live dt is active,
we should use dm_scan_fdt_live instead.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agofs: cbfs: fix locating the cbfs header
Andre Heider [Thu, 15 Feb 2018 06:40:11 +0000 (07:40 +0100)]
fs: cbfs: fix locating the cbfs header

The value at the end of the rom is not a pointer, it is an offset
relative to the end of rom.

Signed-off-by: Andre Heider <a.heider@gmail.com>
6 years agocmd: cbfs: fix reading the end_of_rom pointer for 64bit archs
Andre Heider [Thu, 15 Feb 2018 06:40:10 +0000 (07:40 +0100)]
cmd: cbfs: fix reading the end_of_rom pointer for 64bit archs

The cast breaks the pointer on 64bit archs, so lets get rid of it.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
6 years agopinctrl-uclass: convert to use live dt
Kever Yang [Fri, 9 Feb 2018 02:56:24 +0000 (10:56 +0800)]
pinctrl-uclass: convert to use live dt

Use live dt interface for pinctrl_select_state_full()

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agocore: add uclass_get_device_by_phandle_id() api
Kever Yang [Fri, 9 Feb 2018 02:56:23 +0000 (10:56 +0800)]
core: add uclass_get_device_by_phandle_id() api

Add api for who can not get phandle from a device property.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Fri, 30 Mar 2018 22:18:22 +0000 (18:18 -0400)]
Merge git://git.denx.de/u-boot-marvell

6 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Fri, 30 Mar 2018 22:17:23 +0000 (18:17 -0400)]
Merge git://git.denx.de/u-boot-x86

6 years agoMerge git://git.denx.de/u-boot-riscv
Tom Rini [Fri, 30 Mar 2018 22:16:56 +0000 (18:16 -0400)]
Merge git://git.denx.de/u-boot-riscv

6 years agoarm64: a37xx: defconfigs: enable PCI_CMD and E1000 driver
Ken Ma [Mon, 26 Mar 2018 07:57:32 +0000 (15:57 +0800)]
arm64: a37xx: defconfigs: enable PCI_CMD and E1000 driver

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: dts: enable pcie port
Wilson Ding [Mon, 26 Mar 2018 07:57:31 +0000 (15:57 +0800)]
arm64: a37xx: dts: enable pcie port

This patch enabled PCIe port on both devel-board
and espressobin board.

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: defconfigs: enable aardvark pcie driver
Wilson Ding [Mon, 26 Mar 2018 07:57:30 +0000 (15:57 +0800)]
arm64: a37xx: defconfigs: enable aardvark pcie driver

Signed-off-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: pci: add support for aardvark pcie driver
Wilson Ding [Mon, 26 Mar 2018 07:57:29 +0000 (15:57 +0800)]
arm64: a37xx: pci: add support for aardvark pcie driver

This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.

Signed-off-by: Wilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: populate pcie memory region
Wilson Ding [Mon, 26 Mar 2018 07:57:28 +0000 (15:57 +0800)]
arm64: a37xx: populate pcie memory region

This patch added a new region of 32MiB AT 0xe800.0000
to Armada37x0's memory map. This region is supposed to
be mapped in MMU in order to enable the access to the
PCI I/O or MEM resources.

Signed-off-by: Wilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38724
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Victor Gu <xigu@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: remove old pinctrl implementation
Ken Ma [Mon, 26 Mar 2018 07:56:07 +0000 (15:56 +0800)]
arm64: a37xx: remove old pinctrl implementation

Since the new pinctrl/gpio driver is used, so this patch removes
the old board specific pin control settings.

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoRevert "arm64: a37xx: dts: Add pin control nodes to DT"
Ken Ma [Mon, 26 Mar 2018 07:56:06 +0000 (15:56 +0800)]
Revert "arm64: a37xx: dts: Add pin control nodes to DT"

The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has
added new pinctrl nodes.
This reverts commit f7cab0f95b05ec6a66fe4796b9ad44406d0cc864.

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agodoc: a37xx: Introduce pinctrl device tree binding
Ken Ma [Mon, 26 Mar 2018 07:56:05 +0000 (15:56 +0800)]
doc: a37xx: Introduce pinctrl device tree binding

Reviewed-on: http://vgitil04.il.marvell.com:8080/43289
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: dts: Correct mpp definitions
Ken Ma [Mon, 26 Mar 2018 07:56:04 +0000 (15:56 +0800)]
arm64: a37xx: dts: Correct mpp definitions

This patch corrects below mpp definitions for armada 3720 DB board
and ESPRESSOBin board:
- "smi" pins group is added and "smi" function is set for eth0;
- Now pcie pins are used as gpio to implement PCIe function in
  hardware, so "pcie" group function is changed to "gpio".

Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: pinctrl: Correct mpp definitions
Ken Ma [Mon, 26 Mar 2018 07:56:03 +0000 (15:56 +0800)]
arm64: a37xx: pinctrl: Correct mpp definitions

This patch corrects below mpp definitions:
 - The sdio_sb group is composed of 6 pins and not 5;
 - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
 - Pin of group "pmic0" is mpp1[6] but not mpp1[16];
 - Pin of group "pmic1" is mpp1[7] but not mpp1[17];
 - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
   bitmask is bit4;
 - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
   bit5 | bit9 | bit10 but not bit4;
 - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
   bit11 | bit12 | bit13.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: pinctrl: Fix gpio pin offset in register
Ken Ma [Mon, 26 Mar 2018 07:56:02 +0000 (15:56 +0800)]
arm64: a37xx: pinctrl: Fix gpio pin offset in register

For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: pinctrl: Fix the pin 23 on south bridge
Ken Ma [Mon, 26 Mar 2018 07:56:01 +0000 (15:56 +0800)]
arm64: a37xx: pinctrl: Fix the pin 23 on south bridge

Pin 23 on South bridge does not belong to the rgmii group. It belongs to
a separate group which can have 3 functions.

Due to this the fix also have to update the way the functions are
managed. Until now each groups used NB_FUNCS(which was 2) functions. For
the mpp23, 3 functions are available but it is the only group which needs
it, so on the loop involving NB_FUNCS an extra test was added to handle
only the functions added.

The bug was visible when the gpio regulator used the gpio 23, the whole
rgmii group was setup to gpio which broke the Ethernet support on the
Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need
the vqmmc) _and_ the Ethernet work again.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43284
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: dts: Fix the number of GPIO on south bridge
Ken Ma [Mon, 26 Mar 2018 07:56:00 +0000 (15:56 +0800)]
arm64: a37xx: dts: Fix the number of GPIO on south bridge

The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43286
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: pinctrl: Fix number of pin in south bridge
Ken Ma [Mon, 26 Mar 2018 07:55:59 +0000 (15:55 +0800)]
arm64: a37xx: pinctrl: Fix number of pin in south bridge

On the south bridge we have pin from 0 to 29, so it gives 30 pins (and
not 29).

Reviewed-on: http://vgitil04.il.marvell.com:8080/43285
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: dts: Add additional pinctrl definition
Ken Ma [Mon, 26 Mar 2018 07:55:58 +0000 (15:55 +0800)]
arm64: a37xx: dts: Add additional pinctrl definition

Add mmc pins, pcie pins and sdio pins definition and do these pins'
configuration for DB board and espressobin board;
Add uart2 pins configuration for DB board.

Reviewed-on: http://vgitil04.il.marvell.com:8080/40914
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Tested-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: dts: Add pinctrl configuration for ESPRESSOBin board
Ken Ma [Mon, 26 Mar 2018 07:55:57 +0000 (15:55 +0800)]
arm64: a37xx: dts: Add pinctrl configuration for ESPRESSOBin board

Reviewed-on: http://vgitil04.il.marvell.com:8080/40913
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Tested-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: defconfig: Enable PINCTRL and GPIO support for ESPRESSOBin board
Ken Ma [Mon, 26 Mar 2018 07:55:56 +0000 (15:55 +0800)]
arm64: a37xx: defconfig: Enable PINCTRL and GPIO support for ESPRESSOBin board

This patch enable the PINCTRL and GPIO support, including the GPIO
command on the Armada 3720 espressobin board.

Reviewed-on: http://vgitil04.il.marvell.com:8080/40746
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: a37xx: dts: add gpio head file including
Ken Ma [Mon, 26 Mar 2018 07:55:55 +0000 (15:55 +0800)]
arm64: a37xx: dts: add gpio head file including

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: mvebu: a8k: Add distro boot support
Mark Kettenis [Sat, 17 Mar 2018 08:34:27 +0000 (09:34 +0100)]
arm64: mvebu: a8k: Add distro boot support

The various load address values are taken from the a37xx configuration
and match the dowstream 'u-boot-2017.03-armada-17.10' release where
appropriate.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agokwbimage: Fix out of bounds access
Alexander Graf [Thu, 15 Mar 2018 10:14:19 +0000 (11:14 +0100)]
kwbimage: Fix out of bounds access

The kwbimage format is reading beyond its header structure if it
misdetects a Xilinx Zynq image and tries to read it. Fix it by
sanity checking that the header we want to read fits inside our
file size.

Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoconfigs: clearfog: enable random random MAC address
Baruch Siach [Mon, 19 Feb 2018 06:17:22 +0000 (08:17 +0200)]
configs: clearfog: enable random random MAC address

This makes the network devices usable when booting a blank board over
UART, with no pre-configured MAC address stored in the environment area.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agodm: pcie: designware: add correct ATU handling
Igal Liberman [Wed, 14 Feb 2018 17:25:23 +0000 (19:25 +0200)]
dm: pcie: designware: add correct ATU handling

Currently, ATU (address translation unit) implementation doesn't
support translate addresses > 32 bits.

This patch allows to configure ATU correctly for different
memory accesses (memory, configuration and IO).
The same approach is used in Linux Kernel.

Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agox86: zImage: Pass working device tree data to the kernel
Ivan Gorinov [Tue, 27 Mar 2018 01:06:54 +0000 (18:06 -0700)]
x86: zImage: Pass working device tree data to the kernel

On x86 platforms, U-Boot does not pass Device Tree data to the kernel.
This prevents the kernel from using FDT loaded by U-Boot.

Read the working FDT address from the "fdtaddr" environment variable
and add a copy of the FDT data to the kernel setup_data list.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: mmc: Fix mapping of BAR memory
Bernhard Messerklinger [Thu, 15 Feb 2018 08:09:43 +0000 (09:09 +0100)]
x86: mmc: Fix mapping of BAR memory

Use dm_pci_map_bar function for BAR mapping. This has the advantage
of clearing BAR flags and and only accepting mapped memory.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agodm: pci: Avoid setting a PCI region that has 0 size
Bin Meng [Tue, 27 Mar 2018 07:46:06 +0000 (00:46 -0700)]
dm: pci: Avoid setting a PCI region that has 0 size

It makes no sense to set a PCI region that has 0 size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agodm: pci: Check board information pointer in decode_regions()
Bin Meng [Tue, 27 Mar 2018 07:46:05 +0000 (00:46 -0700)]
dm: pci: Check board information pointer in decode_regions()

PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.

With this commit, Intel Galileo board boots again.

Fixes: 664758c ("pci: Fix decode regions for memory banks")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoefi_stub: Fix GDT_NOTSYS check
Alexander Graf [Mon, 4 Dec 2017 15:33:26 +0000 (16:33 +0100)]
efi_stub: Fix GDT_NOTSYS check

The get_codeseg32() wants to know if a passed in descriptor has
flag GDT_NOTSYS set (desc & GDT_NOTSYS), not whether desc and
GDT_NOTSYS are not != 0 (desk && GDT_NOTSYS).

This is an obvious typo. Fix it up.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agoriscv: ae250: Support DT provided by the board at runtime
Rick Chen [Thu, 29 Mar 2018 02:08:33 +0000 (10:08 +0800)]
riscv: ae250: Support DT provided by the board at runtime

Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.

There are two methods to delivery dtb.
 1 Pass from loader:
   When u-boot boot from RAM, gdb or loader can pass dtb
   via a2 to u-boot dynamically. Of course gdb or loader
   shall be in charge of dtb delivery.

 2 Configure CONFIG_SYS_FDT_BASE:
   It can be configured as RAM or ROM base statically,
   no mater u-boot boot from RAM or ROM.
   If it was configured as ROM base, dtb can be burned
   into ROM(spi flash) by spi driver.

Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agoconfigs: Drop CONFIG_MMC_NDS32
Rick Chen [Tue, 20 Mar 2018 03:26:22 +0000 (11:26 +0800)]
configs: Drop CONFIG_MMC_NDS32

Remove CONFIG_MMC_NDS32 from the three config
(adp-ae3xx_defconfig, adp-ag101p_defconfig, nx25-ae250_defconfig).

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agommc: ftsdc010: Merge nds32_mmc to ftsdc010
Rick Chen [Tue, 20 Mar 2018 07:52:58 +0000 (15:52 +0800)]
mmc: ftsdc010: Merge nds32_mmc to ftsdc010

nsd32_mmc was created to support ftsdc010 dm.
It is not necessary to separate both, so merge it
to ftsdc010.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agommc: ftsdc010: Migrate CONFIG_FTSDC010_SDIO to Kconfig
Rick Chen [Tue, 20 Mar 2018 07:10:49 +0000 (15:10 +0800)]
mmc: ftsdc010: Migrate CONFIG_FTSDC010_SDIO to Kconfig

Convert CONFIG_FTSDC010_SDIO to Kconfig.
So CONFIG_FTSDC010_SDIO can also be
removed from config_whitelist.txt.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agoDrop CONFIG_FTSDC010_NUMBER
Rick Chen [Tue, 20 Mar 2018 07:03:40 +0000 (15:03 +0800)]
Drop CONFIG_FTSDC010_NUMBER

CONFIG_FTSDC010_NUMBER was not used anymore,
can be removed now.

So CONFIG_FTSDC010_NUMBER
can also be removed from config_whitelist.txt.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agoDrop CONFIG_FTSDC010_BASE
Rick Chen [Tue, 20 Mar 2018 06:06:38 +0000 (14:06 +0800)]
Drop CONFIG_FTSDC010_BASE

After drop non-dm code of ftsdc010, the sd register
base definition can be droppped now.

So CONFIG_FTSDC010_BASE and CONFIG_FTSDC010_BASE_LIST both
can be removed from config_whitelist.txt

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agoboard: Drop ftsdc010 non-dm code
Rick Chen [Tue, 20 Mar 2018 05:57:13 +0000 (13:57 +0800)]
board: Drop ftsdc010 non-dm code

Remove board_mmc_init() in adp-ag101p, adp-ae3xx
and nx25-ae250 boards.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agommc: ftsdc010: Drop non-dm code
Rick Chen [Tue, 20 Mar 2018 06:30:52 +0000 (14:30 +0800)]
mmc: ftsdc010: Drop non-dm code

Only three defconfig(adp-ag101p_defconfig,
adp-ae3xx_defconfig, nx25-ae250_defconfig)
set CONFIG_FTSDC010=y. And they all also
enable CONFIG_DM_MMC. So the non-dm code
of ftsdc010 can be dropped now.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agonds32: dts: AG101P support sd High-Speed mode
Rick Chen [Thu, 15 Mar 2018 02:47:07 +0000 (10:47 +0800)]
nds32: dts: AG101P support sd High-Speed mode

Enable High-Speed mode with cap-sd-highspeed in dts

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
6 years agoriscv: dts: AE250 support sd High-Speed mode
Rick Chen [Mon, 25 Dec 2017 09:05:39 +0000 (17:05 +0800)]
riscv: dts: AE250 support sd High-Speed mode

Enable High-Speed mode with cap-sd-highspeed in dts.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
6 years agommc: ftsdc010: Support High-Speed mode
Rick Chen [Mon, 25 Dec 2017 08:25:26 +0000 (16:25 +0800)]
mmc: ftsdc010: Support High-Speed mode

ftsdc010 dm driver has been disable High-Speed mode
as default to work around Andes AE3XX platform's problem,
because of it does not support High-Speed mode in
commit id 73cd56b2df213c629191139e5c6705e069b6214f.

But other platforms or SoCs maybe support this function.
So High-Speed mode can be enabled from dts with
cap-mmc-highspeed or cap-sd-highspeed property.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>