oweals/u-boot.git
4 years agofsl-lsch3: Add FlexSPI address space in immap_lsch3
Kuldeep Singh [Thu, 21 Nov 2019 11:45:16 +0000 (17:15 +0530)]
fsl-lsch3: Add FlexSPI address space in immap_lsch3

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
4 years agoarmv8: ls1046afrwy: Fix get_board_version implementation
Pramod Kumar [Thu, 19 Dec 2019 10:28:57 +0000 (10:28 +0000)]
armv8: ls1046afrwy: Fix get_board_version implementation

Current implementation to get board version through GPIO is
broken due to endianness issue hence it is not working for rev B
board.
Fix it to make it work for Rev A as well as Rev B boards

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: Enable SPL_FSL_PBL for some LayerScape platforms
Alison Wang [Wed, 4 Dec 2019 06:21:55 +0000 (06:21 +0000)]
configs: Enable SPL_FSL_PBL for some LayerScape platforms

In commit <db4080d56dec>, SPL_FSL_PBL is removed from the configs of
some LayerScape platforms. Actually, SPL_FSL_PBL is needed for SD/NAND
boot on LS1021A/LS1043A/LS1046A to create boot binary having SPL binary
in PBI format concatenated with u-boot binary. SPL_FRAMEWORK is used on
these platforms too.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agols1028a: Configure stream IDs for integrated PCI and fix up Linux DT
Alex Marginean [Wed, 27 Nov 2019 15:19:32 +0000 (17:19 +0200)]
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT

Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarm64: lx2160a: dts: Fix UART node status
Vabhav Sharma [Tue, 26 Nov 2019 11:30:51 +0000 (11:30 +0000)]
arm64: lx2160a: dts: Fix UART node status

LX2160A PL011 UART driver fetch IP block values using
platform data from board file instead of device tree.

Modified UART nodes in device tree to disable state.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarmv8: Add workaround for USB erratum A-050106
Ran Wang [Tue, 26 Nov 2019 03:40:40 +0000 (11:40 +0800)]
armv8: Add workaround for USB erratum A-050106

USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarmv8: layerscape: fix SPL multi DTB loading
Michael Walle [Sun, 24 Nov 2019 20:13:21 +0000 (21:13 +0100)]
armv8: layerscape: fix SPL multi DTB loading

Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarmv8: fsl-layerscape: Increase mmc read size for secure-boot headers
Udit Agarwal [Wed, 20 Nov 2019 08:49:06 +0000 (08:49 +0000)]
armv8: fsl-layerscape: Increase mmc read size for secure-boot headers

Maximum size of secure boot header to be read from MMC is
12KB which spans across 0x20 blocks.

Hence increase the mmc read size for secure boot
headers from MMC to 0x20 blocks.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodrivers/fsl-mc: Support DPSPARSER object and apply spb command
Florinel Iordache [Tue, 19 Nov 2019 10:28:17 +0000 (10:28 +0000)]
drivers/fsl-mc: Support DPSPARSER object and apply spb command

Add support for DPSPARSER object (create/destroy, open/close, apply spb)
which is required to configure Soft Parser by using MC.
Also add uboot command to apply Soft Parser Blob with command:
fsl_mc apply spb <spb_load_addr>

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next
Tom Rini [Tue, 24 Dec 2019 13:18:19 +0000 (08:18 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next

- Enable DM driver on ppc/km boards
- Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
  T104x, P4080, P2041, P2020, P1020, P3041
- Some updates in mpc85xx-ddr driver, km boards

4 years agoppc/km: enable DM driver support in all defconfigs
Holger Brunck [Mon, 25 Nov 2019 09:04:34 +0000 (10:04 +0100)]
ppc/km: enable DM driver support in all defconfigs

This is the first step to use DM support for the KM powerpc boards.

Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Mario Six <mario.six@gdsys.cc>
CC: Wolfgang Denk <wd@denx.de>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P5040: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:31:09 +0000 (17:31 +0800)]
configs: P5040: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb nodes to P5040 dts
Ran Wang [Thu, 12 Dec 2019 09:31:08 +0000 (17:31 +0800)]
arch: powerpc: add usb nodes to P5040 dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: T4240: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:31:07 +0000 (17:31 +0800)]
configs: T4240: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb nodes to T4240 dts
Ran Wang [Thu, 12 Dec 2019 09:31:06 +0000 (17:31 +0800)]
arch: powerpc: add usb nodes to T4240 dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: T208x: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:31:05 +0000 (17:31 +0800)]
configs: T208x: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: T104x: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:31:04 +0000 (17:31 +0800)]
configs: T104x: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb nodes to T104x dts
Ran Wang [Thu, 12 Dec 2019 09:31:03 +0000 (17:31 +0800)]
arch: powerpc: add usb nodes to T104x dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: T102x: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:31:02 +0000 (17:31 +0800)]
configs: T102x: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agopowerpc: add usb nodes to T102x dts
Ran Wang [Thu, 12 Dec 2019 09:31:01 +0000 (17:31 +0800)]
powerpc: add usb nodes to T102x dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P4080: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:31:00 +0000 (17:31 +0800)]
configs: P4080: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb nodes to P4080 dts
Ran Wang [Thu, 12 Dec 2019 09:30:59 +0000 (17:30 +0800)]
arch: powerpc: add usb nodes to P4080 dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P2041: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:30:58 +0000 (17:30 +0800)]
configs: P2041: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb node to p2041 dts
Ran Wang [Thu, 12 Dec 2019 09:30:57 +0000 (17:30 +0800)]
arch: powerpc: add usb node to p2041 dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P2020: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:30:56 +0000 (17:30 +0800)]
configs: P2020: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb node to p2020 dts
Ran Wang [Thu, 12 Dec 2019 09:30:55 +0000 (17:30 +0800)]
arch: powerpc: add usb node to p2020 dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: p1020: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:30:54 +0000 (17:30 +0800)]
configs: p1020: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb nodes to P1020 dts
Ran Wang [Thu, 12 Dec 2019 09:30:53 +0000 (17:30 +0800)]
arch: powerpc: add usb nodes to P1020 dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: p3041ds: enable CONFIG_DM_USB support
Ran Wang [Thu, 12 Dec 2019 09:30:52 +0000 (17:30 +0800)]
configs: p3041ds: enable CONFIG_DM_USB support

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarch: powerpc: add usb node in p3041 dts
Ran Wang [Thu, 12 Dec 2019 09:30:51 +0000 (17:30 +0800)]
arch: powerpc: add usb node in p3041 dts

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agompc85xx: ddr: Always start DDR RAM in Self Refresh mode
Joakim Tjernlund [Wed, 27 Nov 2019 18:35:10 +0000 (19:35 +0100)]
mpc85xx: ddr: Always start DDR RAM in Self Refresh mode

Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoppc/kmeter1: remove unused define
Holger Brunck [Tue, 26 Nov 2019 18:09:03 +0000 (19:09 +0100)]
ppc/kmeter1: remove unused define

CONFIG_CONS_INDEX is nowhere used for this board, we can drop it.

Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
4 years agoboard/km: remove CONFIG_KM_BOARD_NAME
Holger Brunck [Tue, 26 Nov 2019 18:09:02 +0000 (19:09 +0100)]
board/km: remove CONFIG_KM_BOARD_NAME

We can use the existing CONFIG_SYS_CONFIG_NAME define for that and
remove the option. Also fix the boot string for all km83xx boards.

Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
4 years agoppc/km: convert KM_DEF_NETDEV to Kconfig
Holger Brunck [Tue, 26 Nov 2019 18:09:01 +0000 (19:09 +0100)]
ppc/km: convert KM_DEF_NETDEV to Kconfig

Remove this from the board header files and move it to Kconfig. Also use
the correct default address for kmtegr1.

Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
4 years agoppc/km/tegr1: support second localbus clock signal
Holger Brunck [Tue, 26 Nov 2019 18:09:00 +0000 (19:09 +0100)]
ppc/km/tegr1: support second localbus clock signal

On kmtegr1 we have to specify the second localbus clock signal also
instead of using the default for our ppc 8309 boards.

Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
4 years agoMerge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
Tom Rini [Wed, 18 Dec 2019 12:20:19 +0000 (07:20 -0500)]
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next

- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral

4 years agoMerge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot...
Tom Rini [Tue, 17 Dec 2019 12:53:08 +0000 (07:53 -0500)]
Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next

i2c: for next
- misc: i2c_eeprom:
  Add partition support and add ability to query size
  of eeprom device and partitions
- i2c common:
  add support for offset overflow in to address and add
  sandbox tests for it.

4 years agomisc: i2c_eeprom: add size query
Robert Beckett [Mon, 28 Oct 2019 18:29:06 +0000 (18:29 +0000)]
misc: i2c_eeprom: add size query

Add ability to query size of eeprom device and partitions

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agomisc: i2c_eeprom: add fixed partitions support
Robert Beckett [Mon, 28 Oct 2019 18:29:05 +0000 (18:29 +0000)]
misc: i2c_eeprom: add fixed partitions support

Add ability to partition eeprom via devicetree bindings

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agodm: i2c: EEPROM simulator add tests for addr offset mask
Robert Beckett [Mon, 28 Oct 2019 17:44:59 +0000 (17:44 +0000)]
dm: i2c: EEPROM simulator add tests for addr offset mask

Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agodm: i2c: EEPROM simulator allow tests visibility of addr and offset
Robert Beckett [Mon, 28 Oct 2019 17:44:58 +0000 (17:44 +0000)]
dm: i2c: EEPROM simulator allow tests visibility of addr and offset

Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.

Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: add support for offset overflow in to address
Robert Beckett [Mon, 28 Oct 2019 17:44:57 +0000 (17:44 +0000)]
i2c: add support for offset overflow in to address

Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.

Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agox86: Add chromebook_coral
Simon Glass [Mon, 9 Dec 2019 00:40:20 +0000 (17:40 -0700)]
x86: Add chromebook_coral

Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add FSP support
Simon Glass [Mon, 9 Dec 2019 00:40:19 +0000 (17:40 -0700)]
x86: apl: Add FSP support

The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add FSP structures
Simon Glass [Mon, 9 Dec 2019 00:40:18 +0000 (17:40 -0700)]
x86: apl: Add FSP structures

These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add Kconfig and Makefile
Simon Glass [Mon, 9 Dec 2019 00:40:17 +0000 (17:40 -0700)]
x86: apl: Add Kconfig and Makefile

Add basic plumbing to allow Apollo Lake support to be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add P2SB driver
Simon Glass [Mon, 9 Dec 2019 00:40:16 +0000 (17:40 -0700)]
x86: apl: Add P2SB driver

Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add SPL/TPL init
Simon Glass [Mon, 9 Dec 2019 00:40:15 +0000 (17:40 -0700)]
x86: apl: Add SPL/TPL init

Add code to init the system both in TPL and SPL. Each phase has its own
procedure.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add a CPU driver
Simon Glass [Mon, 9 Dec 2019 00:40:14 +0000 (17:40 -0700)]
x86: apl: Add a CPU driver

Add a bare-bones CPU driver so that CPUs can be probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add SPL loaders
Simon Glass [Mon, 9 Dec 2019 00:40:13 +0000 (17:40 -0700)]
x86: apl: Add SPL loaders

Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospl: Add methods to find the position/size of next phase
Simon Glass [Mon, 9 Dec 2019 00:40:12 +0000 (17:40 -0700)]
spl: Add methods to find the position/size of next phase

Binman supports writing the position and size of U-Boot proper and SPL
into the previous phase of U-Boot. This allows the next phase to be easily
located and loaded.

Add functions to return these useful values, along with symbols to allow
TPL to load SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add PUNIT driver
Simon Glass [Mon, 9 Dec 2019 00:40:11 +0000 (17:40 -0700)]
x86: apl: Add PUNIT driver

Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a
syscon driver since it only needs to be probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add PCH driver
Simon Glass [Mon, 9 Dec 2019 00:40:10 +0000 (17:40 -0700)]
x86: apl: Add PCH driver

Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add LPC driver
Simon Glass [Mon, 9 Dec 2019 00:40:09 +0000 (17:40 -0700)]
x86: apl: Add LPC driver

This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add ITSS driver
Simon Glass [Mon, 9 Dec 2019 00:40:08 +0000 (17:40 -0700)]
x86: apl: Add ITSS driver

This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add hostbridge driver
Simon Glass [Mon, 9 Dec 2019 00:40:07 +0000 (17:40 -0700)]
x86: apl: Add hostbridge driver

This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add systemagent driver
Simon Glass [Mon, 9 Dec 2019 00:32:10 +0000 (17:32 -0700)]
x86: apl: Add systemagent driver

This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoi2c: designware: Add Apollo Lake support
Simon Glass [Wed, 11 Dec 2019 04:28:20 +0000 (21:28 -0700)]
i2c: designware: Add Apollo Lake support

For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add pinctrl driver
Simon Glass [Mon, 9 Dec 2019 00:32:08 +0000 (17:32 -0700)]
x86: apl: Add pinctrl driver

Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add UART driver
Simon Glass [Sat, 7 Dec 2019 04:42:58 +0000 (21:42 -0700)]
x86: apl: Add UART driver

Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add PMC driver
Simon Glass [Sat, 7 Dec 2019 04:42:57 +0000 (21:42 -0700)]
x86: apl: Add PMC driver

Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Add basic IO addresses
Simon Glass [Sat, 7 Dec 2019 04:42:56 +0000 (21:42 -0700)]
x86: apl: Add basic IO addresses

Add some fixed IO and mmap addresses for use in the device tree and with
some early-init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Move qemu CPU fixup function into its own file
Simon Glass [Sat, 7 Dec 2019 04:42:55 +0000 (21:42 -0700)]
x86: Move qemu CPU fixup function into its own file

This function is specific to qemu so it seems best to keep it separate
from the generic code.

Move it out to a new file and update the condition to use if() instead of
 #ifdef

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add a generic Intel GPIO driver
Simon Glass [Sat, 7 Dec 2019 04:42:54 +0000 (21:42 -0700)]
x86: Add a generic Intel GPIO driver

Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add a generic Intel pinctrl driver
Simon Glass [Sat, 7 Dec 2019 04:42:53 +0000 (21:42 -0700)]
x86: Add a generic Intel pinctrl driver

Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.

As well as a pinctrl driver this provides a GPIO driver based on the same
code.

Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add low-power subsystem (lpss) support
Simon Glass [Sat, 7 Dec 2019 04:42:52 +0000 (21:42 -0700)]
x86: Add low-power subsystem (lpss) support

This subsystem is present on various Intel SoCs.

Add very basic support for taking an lpss device out of reset.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Enable pinctrl in SPL and TPL
Simon Glass [Sat, 7 Dec 2019 04:42:51 +0000 (21:42 -0700)]
x86: Enable pinctrl in SPL and TPL

If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agomtd: spi: Export spi_flash_std_probe()
Simon Glass [Sat, 7 Dec 2019 04:42:50 +0000 (21:42 -0700)]
mtd: spi: Export spi_flash_std_probe()

With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.

To avoid duplicating the probing code, export this probe function for use
by these drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Add Apollo Lake support
Simon Glass [Sat, 7 Dec 2019 04:42:49 +0000 (21:42 -0700)]
spi: ich: Add Apollo Lake support

Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Add TPL support
Simon Glass [Sat, 7 Dec 2019 04:42:48 +0000 (21:42 -0700)]
spi: ich: Add TPL support

In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Add support for get_mmap() method
Simon Glass [Sat, 7 Dec 2019 04:42:47 +0000 (21:42 -0700)]
spi: ich: Add support for get_mmap() method

Add this method so that the memory-mapped location of the SPI flash can
be queried.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Support hardware sequencing
Simon Glass [Sat, 7 Dec 2019 04:42:46 +0000 (21:42 -0700)]
spi: ich: Support hardware sequencing

Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Support of-platdata for fast-spi
Simon Glass [Sat, 7 Dec 2019 04:42:45 +0000 (21:42 -0700)]
spi: ich: Support of-platdata for fast-spi

The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Correct max-size bug in ich_spi_adjust_size()
Simon Glass [Sat, 7 Dec 2019 04:42:44 +0000 (21:42 -0700)]
spi: ich: Correct max-size bug in ich_spi_adjust_size()

This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agodm: doc: Add a note about of-platdata and header files
Simon Glass [Sat, 7 Dec 2019 04:42:43 +0000 (21:42 -0700)]
dm: doc: Add a note about of-platdata and header files

We don't want to include dt-structs.h in header files, so add a note about
that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Add mmio_base to struct ich_spi_platdata
Simon Glass [Sat, 7 Dec 2019 04:42:42 +0000 (21:42 -0700)]
spi: ich: Add mmio_base to struct ich_spi_platdata

It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Various small tidy-ups
Simon Glass [Sat, 7 Dec 2019 04:42:41 +0000 (21:42 -0700)]
spi: ich: Various small tidy-ups

Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Fix header order
Simon Glass [Sat, 7 Dec 2019 04:42:40 +0000 (21:42 -0700)]
spi: ich: Fix header order

Move the header files into the right order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Convert to livetree
Simon Glass [Sat, 7 Dec 2019 04:42:39 +0000 (21:42 -0700)]
spi: ich: Convert to livetree

Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Move the protection/lockdown code into a function
Simon Glass [Sat, 7 Dec 2019 04:42:38 +0000 (21:42 -0700)]
spi: ich: Move the protection/lockdown code into a function

Reduce the size of the probe function but putting this code into its own
function.

Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: ich: Move init function just above probe()
Simon Glass [Sat, 7 Dec 2019 04:42:37 +0000 (21:42 -0700)]
spi: ich: Move init function just above probe()

It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: spi: Don't enable SPI_FLASH_BAR by default
Simon Glass [Sat, 7 Dec 2019 04:42:36 +0000 (21:42 -0700)]
x86: spi: Don't enable SPI_FLASH_BAR by default

We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.

Drop the default enabling of this option on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agospi: Correct operations check in dm_spi_xfer()
Simon Glass [Sat, 7 Dec 2019 04:42:35 +0000 (21:42 -0700)]
spi: Correct operations check in dm_spi_xfer()

At present we have to have an xfer() method even if it does nothing. This
is not correct, so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Make MSR_PKG_POWER_SKU common
Simon Glass [Sat, 7 Dec 2019 04:42:34 +0000 (21:42 -0700)]
x86: Make MSR_PKG_POWER_SKU common

This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Separate out U-Boot and device tree in ROM image
Simon Glass [Sat, 7 Dec 2019 04:42:33 +0000 (21:42 -0700)]
x86: Separate out U-Boot and device tree in ROM image

At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.

Do the same for SPL tool.

In both cases, group the two parts into a section so that SPL symbols get
the correct total size.

It may be possible for binman to handle this automatically at some point,
by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and
u-boot.dtb

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Don't repeat microcode in U-Boot if not needed
Simon Glass [Sat, 7 Dec 2019 04:42:32 +0000 (21:42 -0700)]
x86: Don't repeat microcode in U-Boot if not needed

At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add an fdtmap and image-header
Simon Glass [Sat, 7 Dec 2019 04:42:31 +0000 (21:42 -0700)]
x86: Add an fdtmap and image-header

Add these entries to the ROM so that we can list the contents of an image
with 'binman ls'. The image-header is not essential but does speed up
access.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add an option to control the position of SPL
Simon Glass [Sat, 7 Dec 2019 04:42:30 +0000 (21:42 -0700)]
x86: Add an option to control the position of SPL

For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).

Add a Kconfig option for the ROM position.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add an option to control the position of U-Boot
Simon Glass [Sat, 7 Dec 2019 04:42:29 +0000 (21:42 -0700)]
x86: Add an option to control the position of U-Boot

The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.

Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Update .dtsi file for FSP2
Simon Glass [Sat, 7 Dec 2019 04:42:28 +0000 (21:42 -0700)]
x86: Update .dtsi file for FSP2

Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.

Also drop the FSP binary as this relates only to FSP1.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Update the fsp command for FSP2
Simon Glass [Sat, 7 Dec 2019 04:42:27 +0000 (21:42 -0700)]
x86: Update the fsp command for FSP2

The current 'fsp' command only works with FSP1. Update it to handle FSP2
as well. Convert everything to hex which is what U-Boot uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Disable microcode section for FSP2
Simon Glass [Sat, 7 Dec 2019 04:42:26 +0000 (21:42 -0700)]
x86: Disable microcode section for FSP2

At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add support for newer CAR schemes
Simon Glass [Sat, 7 Dec 2019 04:42:25 +0000 (21:42 -0700)]
x86: Add support for newer CAR schemes

Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.

To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add an option to include a FIT
Simon Glass [Sat, 7 Dec 2019 04:42:24 +0000 (21:42 -0700)]
x86: Add an option to include a FIT

Many Intel SoCs require a FIT in order to boot properly. Add an option to
include this and enable it by default.

This term can be confused with FIT (Flat Image Tree) in U-Boot so the
CONFIG option has to include 'X86'.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Don't include the BIOS emulator in TPL
Simon Glass [Sat, 7 Dec 2019 04:42:23 +0000 (21:42 -0700)]
x86: Don't include the BIOS emulator in TPL

We don't generally have enough space to run this, so don't build it into
TPL. This helps reduce the size of TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: fsp: Make the notify API call common
Simon Glass [Sat, 7 Dec 2019 04:42:22 +0000 (21:42 -0700)]
x86: fsp: Make the notify API call common

The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
common API file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: fsp: Allow remembering the location of FSP-S
Simon Glass [Sat, 7 Dec 2019 04:42:21 +0000 (21:42 -0700)]
x86: fsp: Allow remembering the location of FSP-S

FSP-S is used by the notify call after it has been used for silicon init.
To avoid having to load it again, add a field to store the location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: fsp: Add a new arch_fsp_init_r() hook
Simon Glass [Sat, 7 Dec 2019 04:42:20 +0000 (21:42 -0700)]
x86: fsp: Add a new arch_fsp_init_r() hook

With FSP2 we need to run silicon init early after relocation. Add a new
hook for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: fsp: Set up an MTRR for the graphics frame buffer
Simon Glass [Sat, 7 Dec 2019 04:42:19 +0000 (21:42 -0700)]
x86: fsp: Set up an MTRR for the graphics frame buffer

The FSP-S may do this but at least for coral it does not. Set this up so
that graphics is not deathly slow.

It isn't clear whether the FSP is expected to set up MTRR. It is not
mentioned in the APL FSP document.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: fsp: Add FSP2 base support
Simon Glass [Sat, 7 Dec 2019 04:42:18 +0000 (21:42 -0700)]
x86: fsp: Add FSP2 base support

Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.

Support for the FSP_S binary is also included.

Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI
reads.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>