Marek Vasut [Sun, 12 Jul 2015 21:25:21 +0000 (23:25 +0200)]
ddr: altera: Implement universal scc_mgr_set_all_ranks()
Implement universal scc_mgr_set_all_ranks() function and convert
various ad-hoc implementations of similar functionality to use
this single function. Document the function in kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 21:14:33 +0000 (23:14 +0200)]
ddr: altera: Shuffle around scc_mgr_set_*all_ranks()
Shuffle the code around a bit, but without any functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 20 Jul 2015 05:16:42 +0000 (07:16 +0200)]
ddr: altera: Clean up scc_mgr_initialize()
Clean up the comments and add kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 20:28:33 +0000 (22:28 +0200)]
ddr: altera: Implement universal scc manager config function
Implement unified scc_mgr_set() function and convert all those
9 scc_mgr_set_*() ad-hoc functions to call this one function.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 20:11:55 +0000 (22:11 +0200)]
ddr: altera: Reorder scc manager functions
This patch just puts functions which look similar next to each
other, so they can be sorted out. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 20:07:33 +0000 (22:07 +0200)]
ddr: altera: Clean up scc manager function args
Clean up the unused args of the functions used to configure the
SCC manager.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 19:10:24 +0000 (21:10 +0200)]
ddr: altera: Clean up reg_file_set*()
Turn the insides of these functions into trivial clrsetbits_le32()
and fix the data type of their argument to reflect it's actual size.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 19 Jul 2015 04:14:04 +0000 (06:14 +0200)]
ddr: altera: Clean up initialize_hps_phy()
Add brief kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 19 Jul 2015 04:13:37 +0000 (06:13 +0200)]
ddr: altera: Clean up initialize_reg_file()
Add brief kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 19 Jul 2015 04:12:42 +0000 (06:12 +0200)]
ddr: altera: Clean up hc_initialize_rom_data()
Clean the function up, fix data types, add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 19:05:08 +0000 (21:05 +0200)]
ddr: altera: Massage addr into I/O accessors
Get rid of invocations of this sort:
addr = (u32)&base->reg;
writel(val, addr);
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 18:49:39 +0000 (20:49 +0200)]
ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
Use the proper structure which describes these registers,
especially since this is already in place.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 18:05:54 +0000 (20:05 +0200)]
ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS
in the code.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 17:03:33 +0000 (19:03 +0200)]
ddr: altera: Pluck out remaining sdr_get_addr() calls
Remove the remaining invocations of sdr_get_addr() and the function
itself. This makes the code a bit less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 16:54:37 +0000 (18:54 +0200)]
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 16:46:52 +0000 (18:46 +0200)]
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 16:42:34 +0000 (18:42 +0200)]
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 16:31:05 +0000 (18:31 +0200)]
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 15:52:36 +0000 (17:52 +0200)]
ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 23:05:27 +0000 (01:05 +0200)]
ddr: altera: Clean up ugly casts in sdram_calibration_full()
Use the correct formating string in those debug_cond() invocations
and zap those unnecessary ugly casts.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 18 Jul 2015 00:23:29 +0000 (02:23 +0200)]
ddr: altera: Minor indent fix in set_rank_and_odt_mask()
Fix the position of the } else { statement to make it correctly
indented.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 15 Jul 2015 00:53:45 +0000 (02:53 +0200)]
Makefile: Add target for building bootable SPL image for SoCFPGA
Add build target for generating boot partition images recognised by
the SoCFPGA BootROM. The SoCFPGA BootROM expects four copies of the
u-boot-spl-dtb.sfp at the beginning of boot partition. Those are
u-boot-spl-dtb.bin augmented by a header with which the BootROM can
work. The u-boot-dtb.img uImage is appended to this to produce a
full boot partition image, the u-boot-with-spl-dtb.sfp . This is
the name of the final target.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 24 Jul 2015 04:15:14 +0000 (06:15 +0200)]
arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful
Enable the mtdparts command and related options to make support
for SPI NOR MTD useful in any way. With the mtdparts command in
place, it is possible to use partition of the SPI NOR in U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 22 Jul 2015 04:18:19 +0000 (06:18 +0200)]
arm: socfpga: config: Fix LOADADDR
Setting LOADADDR to 0x8000 is a bad idea, it is very likely that
some kind of overlap will happen. Move the LOADADDR 0x01000000
(16MiB from start of RAM) to make sure no overlap happens when
loading kernel for example.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 20 Jul 2015 03:48:37 +0000 (05:48 +0200)]
arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR
This is needed to access broken (read: Micron) SPI flashes which
are larger than 16 MiB and don't correctly support 4-byte addressing.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 21 Jul 2015 14:17:39 +0000 (16:17 +0200)]
arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build
We do not need full MTD support in the SPL build, it only adds size
and is not usable in any way. Exclude it.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 01:41:53 +0000 (03:41 +0200)]
arm: socfpga: config: Zap incorrect config options
There is no need to disable support for partitions in the SPL,
we can support partitions in SPL perfectly well. This is likely
some remnant from old times, so just remove this configuration
option.
Moreover, the CRC32 chunk size doesn't have to be adjusted anymore,
since both the GD and malloc area are in RAM by the time this CRC
check can be used and there's plenty of space. Zap this abomination
as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 13:23:28 +0000 (15:23 +0200)]
arm: socfpga: config: Move SPL GD and malloc to RAM
Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 25 Jul 2015 17:33:56 +0000 (19:33 +0200)]
arm: socfpga: misc: Reset ethernet from OF
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 25 Jul 2015 16:47:02 +0000 (18:47 +0200)]
arm: socfpga: misc: Probe ethernet GMAC from OF
The GMAC can now be probed from OF, so enable DM ethernet and remove the
old ad-hoc designware_initialize() invocation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 22 Jul 2015 03:40:12 +0000 (05:40 +0200)]
arm: socfpga: misc: Export bootmode into environment variable
setenv an environment variable called "bootmode" , which contains the
board boot mode. This can be in turn used in scripts to determine from
where to load kernel and such.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 21 Jul 2015 14:10:13 +0000 (16:10 +0200)]
arm: socfpga: misc: Add support for printing boot mode
Add support for printing from which device the SoCFPGA board booted.
This decodes the BSEL settings and prints it in human readable form.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 13:11:03 +0000 (15:11 +0200)]
arm: socfpga: misc: Fix warm reset
Write necessary magic value into the Warm Boot from ON-Chip RAM
group Enable register to enable Warm reset support. Instead of
doing this in the reset_cpu() function, we do it in arch early
init to avoid breaking old kernel code which expects this magic
value to be already written into this register.
This magic is originally excavated from common/spl/spl.c in the
u-boot port from altera, where this value was written just before
the SPL jumped to actual U-Boot in the RAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 21 Jul 2015 14:11:16 +0000 (16:11 +0200)]
arm: socfpga: spl: Add support for selecting boot device from BSEL
Rework spl_boot_device() such that it reads the BSEL settings from
system manager and decides from where to load U-Boot based on this
information.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 21 Jul 2015 05:50:03 +0000 (07:50 +0200)]
arm: socfpga: spl: Add support for booting from QSPI
Add code and configuration options to support booting from QSPI NOR.
Enable support for booting from QSPI NOR.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 22:04:23 +0000 (00:04 +0200)]
arm: socfpga: spl: Add support for booting from SD/MMC
Add code and configuration options to support booting from RAW
SD/MMC card as well as for ext4/vfat filesystems. Enable support
for booting from SD/MMC card, but don't enable the filesystem
support just yet to retain compatibility with old SoCFPGA card
format.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 21:26:34 +0000 (23:26 +0200)]
arm: socfpga: spl: Remove custom linker script
Remove the custom SPL linker script, use the generic one instead.
The custom script doesn't bring in anything new and is only burden
to maintain.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 03:36:23 +0000 (05:36 +0200)]
arm: socfpga: spl: Merge spl_board_init() into board_init_f()
The code in spl_board_init() should have been in board_init_f()
from the beginning, since it is code which configures system and
then starts DRAM. Thus, it cannot be in spl_board_init(), which
is called from board_init_r() , which already expects a working
DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 03:21:02 +0000 (05:21 +0200)]
arm: socfpga: spl: Add missing reset logic
Make sure that all the peripherals are correctly reset and then
brought out of reset in the SPL. Not going through proper reset
cycle might leave the IP blocks in inconsistent state.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 03:15:40 +0000 (05:15 +0200)]
arm: socfpga: spl: Configure SCU and NIC-301 early
Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register
must be configured, so we can access all peripherals. The NIC-301 must
be configured so that the BootROM is not mapped into the SDRAM address
space.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 02:48:56 +0000 (04:48 +0200)]
arm: socfpga: spl: Toggle warm reset config I/O bit
Synchronise the SPL behavior with the original Altera code and
toggle the Warm Reset Config I/O bit accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 25 Jul 2015 09:09:11 +0000 (11:09 +0200)]
arm: socfpga: system: Clean up pinmux_config.c
Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux
table and it's size from the QTS-generated pinmux_config.c. The target
here is again to get rid of poluting global namespace by including the
pinmux_config.h into it.
Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros,
which are explicitly useless to us in U-Boot. Instead, U-Boot does
use DT to detect exactly these configuration options. This patch
makes sure that while this QTS-generated file can stay in the tree,
these obscure macros do not ooze into the namespace anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 02:40:11 +0000 (04:40 +0200)]
arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()
Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(),
which allows both enabling and disabling the warm reset config I/O
functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 25 Jul 2015 07:53:23 +0000 (09:53 +0200)]
arm: socfpga: scan: Zap iocsr_scan_chain*_table()
Introduce accessor iocsr_get_config_table() for retrieving IOCSR config
tables. This patch is again trimming down the namespace polution.
The IOCSR config tables are used only by scan manager, they are generated
by qts and are board specific. Before this patch, the approach to use
these tables in scan manager was to define an extern variable to silence
the compiler and compile board-specific iocsr_config.c into U-Boot which
defined those extern variables. Furthermore, since these are tables and
the scan manager needs to know the size of those tables, iocsr_config.h
is included build-wide.
This patch wraps all this into a single accessor which takes the scan
chain ID and returns pointer to the table and it's size. All this is
wrapped in wrap_iocsr_config.c board-specific file. The file includes
the iocsr_config.c (!) to access the original tables and transitively
iocsr_config.h . It is thus no longer necessary to include iocsr_config.h
build-wide and the namespace polution is trimmed some more.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 25 Jul 2015 07:36:54 +0000 (09:36 +0200)]
arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg()
It is sufficient to pass in the scan chain ID into the function to determine
the remaining two parameters, so drop those params and determine them locally
in the function. The big-ish switch in the function is temporary and will be
replaced by a proper function call in subsequent patch.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 25 Jul 2015 07:33:28 +0000 (09:33 +0200)]
arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()
This function is never used outside of scan_manager.c , so make it static.
Zap the prototype in scan_manager.h and move the documentation above the
function. Make the documentation kerneldoc compliant.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 25 Jul 2015 06:44:27 +0000 (08:44 +0200)]
arm: socfpga: clock: Clean up pll_config.h
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.
First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.
The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.
The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sat, 25 Jul 2015 06:37:16 +0000 (08:37 +0200)]
arm: socfpga: clock: Get rid of cm_config_t typedef
Get rid of this cryptic typedef and replace it with explicit struct cm_config.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 02:28:13 +0000 (04:28 +0200)]
arm: socfpga: reset: Add SDMMC, QSPI and DMA defines
Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 02:27:28 +0000 (04:27 +0200)]
arm: socfpga: reset: Add function to reset add peripherals
Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 01:52:12 +0000 (03:52 +0200)]
arm: socfpga: reset: Repair bridge reset handling
The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any polling involved, and only if it is
programmed, it de-asserts the reset.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 00:51:56 +0000 (02:51 +0200)]
arm: socfpga: reset: Replace ad-hoc reset functions
Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 00:45:15 +0000 (02:45 +0200)]
arm: socfpga: reset: Implement unified function to toggle reset
Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 00:30:35 +0000 (02:30 +0200)]
arm: socfpga: reset: Start reworking the SoCFPGA reset manager
Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 9 Jul 2015 01:39:06 +0000 (03:39 +0200)]
arm: socfpga: reset: Add missing reset manager regs
Define two missing reset manager registers, which are in the
SoCFPGA CV datasheet.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 26 Jun 2015 16:56:54 +0000 (18:56 +0200)]
ddr: altera: Fix debug message format in sequencer
The debug messages missed proper newlines and/or spaces in them.
Fix the formatting.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Wed, 8 Jul 2015 23:47:56 +0000 (01:47 +0200)]
ddr: altera: Fix typo in mp_threshold1 programming
It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Sun, 26 Jul 2015 08:37:54 +0000 (10:37 +0200)]
ddr: altera: Move struct sdram_prot_rule prototype
Move the structure prototype from sdram.h header file into sdram.c
source file, since it is used only there and for local purpose only.
There is no point in having it global.
While at this move, fix the data types in the structure from uintNN_t
to uNN and fix the coding style a bit.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 12 Jul 2015 13:59:10 +0000 (15:59 +0200)]
arm: socfpga: Move sdram_config.h to board dir
This file is absolutelly positively board specific, so move it
into the correct place.
Signed-off-by: Marek Vasut <marex@denx.de>
Dinh Nguyen [Wed, 3 Jun 2015 03:52:50 +0000 (22:52 -0500)]
arm: socfpga: enable the Altera SDRAM controller driver
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Dinh Nguyen [Wed, 3 Jun 2015 03:52:49 +0000 (22:52 -0500)]
driver/ddr/altera: Add the sdram calibration portion
This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh Nguyen [Wed, 3 Jun 2015 03:52:48 +0000 (22:52 -0500)]
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 25 Jul 2015 16:42:34 +0000 (18:42 +0200)]
net: designware: Rename the driver var name to eth_designware
The driver variable name is eth_sandbox, which is probably a copy-paste
mistake. Fix it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 25 Jul 2015 16:38:44 +0000 (18:38 +0200)]
net: designware: Add SoCFPGA GMAC DT compatible string
Add the OF compatible property to match the SoCFPGA GMAC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 25 Jul 2015 06:22:21 +0000 (08:22 +0200)]
arm: socfpga: Move generated files into qts subdir
Move all the files generated by Quartus into the qts/ subdir of the
board/altera/socfpga dir to make them explicitly separate from the
generic U-Boot code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 25 Jul 2015 08:47:22 +0000 (10:47 +0200)]
arm: dts: socfpga: Add mmc alias
Add alias for the SD/MMC controller, so it can be located by U-Boot OF support.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Tue, 21 Jul 2015 09:25:14 +0000 (11:25 +0200)]
arm: dts: socfpga: Fix SPI aliases
The SPI aliases are completely wrong. First, they point to non-existing
/spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use
ad-hoc string instead of a handle. Furthermore, they are copied multiple
times in each board DTS.
So fix it such that we move these into socfpga.dtsi and make them use
the usual handles.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Mon, 27 Jul 2015 20:34:54 +0000 (22:34 +0200)]
arm: socfpga: Fix FPGA bitstream programming routine
In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Tom Rini [Thu, 6 Aug 2015 23:56:03 +0000 (19:56 -0400)]
Merge git://git.denx.de/u-boot-dm
Stephen Warren [Wed, 5 Aug 2015 17:52:08 +0000 (11:52 -0600)]
ARM: tegra: Add p2371-0000 board
P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
board. The combination contains SoC, DRAM, eMMC, SD card slot,
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 5 Aug 2015 17:52:07 +0000 (11:52 -0600)]
ARM: tegra: Add e2220-1170 board
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
expansion modules.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 5 Aug 2015 17:51:11 +0000 (11:51 -0600)]
ARM: tegra: p2571: remove another unused define
CONFIG_MAX77620_POWER isn't used anywhere. Don't define it in p2571.h.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Alexandre Courbot [Thu, 9 Jul 2015 07:33:01 +0000 (16:33 +0900)]
ARM: tegra: enable GPU DT node when appropriate
T124/210 requires some specific configuration (VPR setup) to
be performed by the bootloader before the GPU can be used.
For this reason, the GPU node in the device tree is disabled
by default. This patch enables the node if U-boot has performed
VPR configuration.
Boards enabled by this patch are T124's Jetson TK1 and Venice2
and T210's P2571.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Alexandre Courbot [Thu, 9 Jul 2015 07:33:00 +0000 (16:33 +0900)]
ARM: tegra: move VPR configuration to a later stage
U-boot is responsible for enabling the GPU DT node after all necessary
configuration (VPR setup for T124) is performed. In order to be able to
check whether this configuration has been performed right before booting
the kernel, make it happen during board_init().
Also move VPR configuration into the more generic gpu.c file, which will
also host other GPU-related functions, and let boards specify
individually whether they need VPR setup or not.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 30 Jul 2015 20:34:09 +0000 (14:34 -0600)]
ARM: tegra: add comment re: autogeneration to pinmux headers
Add a comment block to the top of each generated Tegra pinmux header file
indicating that the file was auto-generated, should not be manually
edited, and with a pointer to the tool and command used to generate it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 29 Jul 2015 19:47:58 +0000 (13:47 -0600)]
ARM: tegra: restrict usable RAM size further
Additionally, ARM64 devices typically run a secure monitor in EL3 and
U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
code and data. These carve-outs are located at the top of 32-bit address
space. Restrict U-Boot's RAM usage to well below the location of those
carve-outs. Ideally, we would the secure monitor would inform U-Boot of
exactly which RAM it could use at run-time. However, I'm not sure how to
do that at present (and even if such a mechanism does exist, it would
likely not be generic across all forms of secure monitor).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Mon, 3 Aug 2015 14:19:19 +0000 (08:19 -0600)]
exynos: dts: Correct LDO and BUCK naming
At present lower case is used for the regulator names in the device tree.
The kernel uses upper case and U-Boot will require this also since it will
move to a case-sensitive name check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 00:07:21 +0000 (18:07 -0600)]
x86: Enable debug UART for Minnowmax
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.
Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.
So this means that the character output cannot be any earlier than
car_init_ret, where memory is available for a stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Simon Glass [Thu, 30 Jul 2015 19:40:40 +0000 (13:40 -0600)]
dm: core: Fix a typo in the uclass_get_device_by_name() comment
This function comment has a typo. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 30 Jul 2015 19:40:39 +0000 (13:40 -0600)]
dm: core: Add a way to set a device name
Some devices are bound entirely by probing and do not have the benefit of
a device tree to give them a name. This is very common with PCI and USB. In
most cases this is fine, but we should add an official way to set a device
name. This should be called in the device's bind() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 28 Jul 2015 17:53:14 +0000 (11:53 -0600)]
sandbox: Enable devres subsystem
This should be used for sandbox. We can convert at least one driver to use
it, but in the meantime, enable the feature so that the code is
build-tested.
Signed-off-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:38 +0000 (21:52 +0900)]
devres: add debug command to dump device resources
This new command can dump all device resources associated to
each device. The fields in every line shows:
- The address of the resource
- The size of the resource
- The name of the release function
- The stage in which the resource has been acquired (BIND/PROBE)
Currently, there is no driver using devres, but if such drivers are
implemented, the output of this command should look like this:
=> dm devres
- root_driver
- soc
- extbus
- serial@
54006800
bfb541e8 (8 byte) devm_kmalloc_release BIND
bfb54440 (4 byte) devm_kmalloc_release PROBE
bfb54460 (4 byte) devm_kmalloc_release PROBE
- serial@
54006900
bfb54270 (8 byte) devm_kmalloc_release BIND
- gpio@
55000000
- i2c@
58780000
bfb5bce8 (12 byte) devm_kmalloc_release PROBE
bfb5bd10 (4 byte) devm_kmalloc_release PROBE
- eeprom
bfb54418 (12 byte) devm_kmalloc_release BIND
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:37 +0000 (21:52 +0900)]
devres: make Devres optional with CONFIG_DEVRES
Currently, Devres requires additional 16 byte for each allocation,
which is not so insignificant in some cases.
Add CONFIG_DEVRES to make this framework optional.
If the option is disabled, devres functions fall back to
non-managed variants. For example, devres_alloc() to kzalloc(),
devm_kmalloc() to kmalloc(), etc.
Because devres_head is also surrounded by an ifdef conditional,
there is no memory overhead when CONFIG_DEVRES is disabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:36 +0000 (21:52 +0900)]
devres: add devm_kmalloc() and friends (managed memory allocators)
devm_kmalloc() is identical to kmalloc() except that the memory
allocated with it is managed and will be automatically released
when the device is removed/unbound.
Likewise for the other variants.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:35 +0000 (21:52 +0900)]
devres: introduce Devres (Managed Device Resource) framework
In U-Boot's driver model, memory is basically allocated and freed
in the core framework. So, low level drivers generally only have
to specify the size of needed memory with .priv_auto_alloc_size,
.platdata_auto_alloc_size, etc. Nevertheless, some drivers still
need to allocate/free memory on their own in case they cannot
statically know the necessary memory size. So, I believe it is
reasonable enough to port Devres into U-boot.
Devres, which originates in Linux, manages device resources for each
device and automatically releases them on driver detach. With devres,
device resources are guaranteed to be freed whether initialization
fails half-way or the device gets detached.
The basic idea is totally the same to that of Linux, but I tweaked
it a bit so that it fits in U-Boot's driver model.
In U-Boot, drivers are activated in two steps: binding and probing.
Binding puts a driver and a device together. It is just data
manipulation on the system memory, so nothing has happened on the
hardware device at this moment. When the device is really used, it
is probed. Probing initializes the real hardware device to make it
really ready for use.
So, the resources acquired during the probing process must be freed
when the device is removed. Likewise, what has been allocated in
binding should be released when the device is unbound. The struct
devres has a member "probe" to remember when the resource was
allocated.
CONFIG_DEBUG_DEVRES is also supported for easier debugging.
If enabled, debug messages are printed each time a resource is
allocated/freed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 25 Jul 2015 12:52:34 +0000 (21:52 +0900)]
dm: add DM_FLAG_BOUND flag
Currently, we only have DM_FLAG_ACTIVATED to indicate the device
status, but we still cannot know in which stage is in progress,
binding or probing.
This commit introduces a new flag, DM_FLAG_BOUND, which is set when
the device is really bound, and cleared when it is unbound.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:44 +0000 (20:53 -0600)]
dm: Support address translation for simple-bus
The 'ranges' property can be used to specify a translation from the system
address to the bus address. Add support for this using the dev_get_addr()
function, which devices should use to find their address.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:42 +0000 (20:53 -0600)]
net: smsc95xx: Add driver-model support
Add support for driver model, so that CONFIG_DM_ETH can be defined and used
with this driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:41 +0000 (20:53 -0600)]
net: smsc95xx: Prepare for conversion to driver model
At present struct eth_device is passed around all over the place. This does
not exist with driver model. Add explicit arguments instead, so that with
driver model we can pass the correct things.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:40 +0000 (20:53 -0600)]
net: smsc95xx: Correct the error numbers
Instead of returning -1 on error, we should use a proper error number. Fix
the code to conform to this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:39 +0000 (20:53 -0600)]
net: smsc95xx: Rename AX_RX_URB_SIZE to RX_URB_SIZE
The AX_ prefix comes from the Asix driver. Since this is not that, we should
avoid this confusing prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:38 +0000 (20:53 -0600)]
net: smsc95xx: Sort the include files
Tidy up the include file order before adding more.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:37 +0000 (20:53 -0600)]
dm: usb: Add driver-model support to dwc2
Add driver model support to this driver so it can be used with the new USB
stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:36 +0000 (20:53 -0600)]
dm: usb: Prepare dwc2 driver for driver-model conversion
Put all global data in a structure and move (what will be) common code into
common functions. This will make the driver-model conversion much easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 8 Jul 2015 02:53:35 +0000 (20:53 -0600)]
dm: usb: Add an errno.h header to usb_ether.c
This is required on some platforms, so add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 17 Jul 2015 15:22:07 +0000 (09:22 -0600)]
dm: Make regmap and syscon optional
Not all boards use garbage collection in their link step, so we should avoid
adding options that rely on this for prevention of code bloat. Add separate
Kconfig options for syscon and regmap uclasses.
Signed-off-by: Simon Glass <sjg@chromium.org>
York Sun [Mon, 3 Aug 2015 19:02:04 +0000 (12:02 -0700)]
lib/fdtdec: Fix fdt_addr_t and fdt_size_t typedef
fdt_addr_t is a physical address. It can be either 64-bit or 32-bit,
depending on the architecture. It should be phys_addr_t instead of
u64 or u32. Similarly, fdt_size_t is changed to phys_size_t.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
York Sun [Mon, 3 Aug 2015 19:02:05 +0000 (12:02 -0700)]
lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t type
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:37 +0000 (08:19 -0600)]
exynos: Add support for spring
Spring is the first ARM-based HP Chromebook 11. It is similar to snow
and it uses the same Samsung Exynos5250 chip. But has some unusual
features. Mainline support for it has lagged snow (both in kernel and
U-Boot). Now that the exynos5 code is common we can support spring just
by adding a device tree and a few lines of configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Aug 2015 14:19:36 +0000 (08:19 -0600)]
exynos: video: Remove non-device-tree code
We always use device tree on exynos, so remove the unused code.
Signed-off-by: Simon Glass <sjg@chromium.org>