From: Piotr Dymacz Date: Sun, 6 Mar 2016 15:02:51 +0000 (+0100) Subject: Include workaround for AR933x PLL init from old code, should fix problem with hang... X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=ff7a030;p=oweals%2Fu-boot_mod.git Include workaround for AR933x PLL init from old code, should fix problem with hang on start/restart --- diff --git a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S index b12e71f..1e409c1 100644 --- a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S +++ b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S @@ -266,11 +266,14 @@ xtal_is_40mhz_recovery: /* * Load target value into CPU_CLOCK_CONTROL register, but for now keep bypass * enabled (by default, after reset, it should be bypassed, do it just in case) + * and AHB_POST_DIV equal to 4 */ cpu_clock_control: li t8, QCA_PLL_CPU_CLK_CTRL_REG move t9, reg_cpu_clk_ctrl or t9, t9, QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK + and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK + or t9, t9, (3 << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) sw t9, 0(t8) /* @@ -306,12 +309,12 @@ cpu_pll_wait: bgtz t9, cpu_pll_wait nop -/* Disable bypassing all clocks */ +/* Disable bypassing all clocks, use target AHB_POST_DIV value */ pll_bypass_disable: - li t8, QCA_PLL_CPU_CLK_CTRL_REG - lw t9, 0(t8) - and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK - sw t9, 0(t8) + li t8, QCA_PLL_CPU_CLK_CTRL_REG + move t9, reg_cpu_clk_ctrl + and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK + sw t9, 0(t8) /* Setup SPI (clock and other settings) */ spi_setup: