From: Masahiro Yamada Date: Fri, 16 Sep 2016 18:33:10 +0000 (+0900) Subject: ARM: uniphier: collect clock/PLL init code into a single directory X-Git-Tag: v2016.11-rc1~129^2~2 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=fcc238baee1495ff9796dfc4e13f8069a152e85f;p=oweals%2Fu-boot.git ARM: uniphier: collect clock/PLL init code into a single directory Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada --- diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 548cfe76fc..ae78548670 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -4,7 +4,7 @@ ifdef CONFIG_SPL_BUILD -obj-y += init/ bcu/ memconf/ pll/ early-clk/ +obj-y += init/ bcu/ memconf/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ else @@ -15,13 +15,12 @@ obj-y += board_init.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o -obj-y += clk/ - endif obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ +obj-y += clk/ obj-y += dram/ obj-y += pinctrl-glue.o diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index b722781443..233e6591ee 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -2,6 +2,20 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD + +obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o dpll-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o dpll-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o dpll-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o + +else + obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o @@ -11,3 +25,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o + +endif diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c new file mode 100644 index 0000000000..a40b30d0e0 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "../init.h" +#include "../sc-regs.h" + +#undef DPLL_SSC_RATE_1PER + +int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) +{ + unsigned int dram_freq = bd->dram_freq; + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + /* Wait 500 usec until dpll gets stable */ + udelay(500); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c new file mode 100644 index 0000000000..3ac48d6365 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "../init.h" +#include "../sc-regs.h" + +#undef DPLL_SSC_RATE_1PER + +int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) +{ + unsigned int dram_freq = bd->dram_freq; + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT ( DPLLCTRL.bit[29:20] ) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~(0x000f0000); + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + + /* + * Set Moduration rate + * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) + */ +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~0x00008000; +#else + tmp |= 0x00008000; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + /* Wait until dpll gets stable */ + udelay(500); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/dpll-sld3.c b/arch/arm/mach-uniphier/clk/dpll-sld3.c new file mode 100644 index 0000000000..0eb310ceb8 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-sld3.c @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../init.h" + +int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd) +{ + /* add pll init code here */ + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c new file mode 100644 index 0000000000..7faa5e85b6 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "../init.h" +#include "../sc-regs.h" + +int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + /* + * Set DPLL SSC parameters for DPLLCTRL3 + * [23] DIVN_TEST 0x1 + * [22:16] DIVN 0x50 + * [10] FREFSEL_TEST 0x1 + * [9:8] FREFSEL 0x2 + * [4] ICPD_TEST 0x1 + * [3:0] ICPD 0xb + */ + tmp = readl(SC_DPLLCTRL3); + tmp &= ~0x00ff0717; + tmp |= 0x00d0061b; + writel(tmp, SC_DPLLCTRL3); + + /* + * Set DPLL SSC parameters for DPLLCTRL + * <-1%> <-2%> + * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) + * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x3ff07fff; +#ifdef DPLL_SSC_RATE_1PER + tmp |= 0x084018bf; +#else + tmp |= 0x084031a6; +#endif + writel(tmp, SC_DPLLCTRL); + + /* + * Set DPLL SSC parameters for DPLLCTRL2 + * [31:29] SSC_STEP 0 + * [27] SSC_REG_REF 1 + * [26:20] SSC_M 79 (0x4f) + * [19:0] SSC_K 964689 (0xeb851) + */ + tmp = readl(SC_DPLLCTRL2); + tmp &= ~0xefffffff; + tmp |= 0x0cfeb851; + writel(tmp, SC_DPLLCTRL2); + + /* Wait 500 usec until dpll gets stable */ + udelay(500); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/early-clk-ld11.c b/arch/arm/mach-uniphier/clk/early-clk-ld11.c new file mode 100644 index 0000000000..c94d83c4ed --- /dev/null +++ b/arch/arm/mach-uniphier/clk/early-clk-ld11.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../init.h" +#include "../sc64-regs.h" + +int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_PERI; + writel(tmp, SC_CLKCTRL4); + + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/early-clk-ld20.c b/arch/arm/mach-uniphier/clk/early-clk-ld20.c new file mode 100644 index 0000000000..5201a55940 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/early-clk-ld20.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../init.h" +#include "../sc64-regs.h" + +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | + SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | + SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_PERI; + writel(tmp, SC_CLKCTRL4); + + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | + SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/early-clk-ld4.c b/arch/arm/mach-uniphier/clk/early-clk-ld4.c new file mode 100644 index 0000000000..b6e8b646f9 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/early-clk-ld4.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "../init.h" +#include "../sc-regs.h" + +int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + + tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; + if (spl_boot_device() != BOOT_DEVICE_NAND) + tmp &= ~SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* provide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/early-clk-pro5.c b/arch/arm/mach-uniphier/clk/early-clk-pro5.c new file mode 100644 index 0000000000..c41a8ead2e --- /dev/null +++ b/arch/arm/mach-uniphier/clk/early-clk-pro5.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../init.h" +#include "../sc-regs.h" + +int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* + * deassert reset + * UMCA2: Ch1 (DDR3) + * UMCA1, UMC31: Ch0 (WIO1) + * UMCA0, UMC30: Ch0 (WIO0) + */ + tmp = readl(SC_RSTCTRL4); + tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | + SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | + SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; + writel(tmp, SC_RSTCTRL4); + readl(SC_RSTCTRL); /* dummy read */ + + /* provide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; + writel(tmp, SC_CLKCTRL); + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 | + SC_CLKCTRL4_CEN_UMC0; + writel(tmp, SC_CLKCTRL4); + readl(SC_CLKCTRL4); /* dummy read */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/early-clk-pxs2.c b/arch/arm/mach-uniphier/clk/early-clk-pxs2.c new file mode 100644 index 0000000000..665ecd510f --- /dev/null +++ b/arch/arm/mach-uniphier/clk/early-clk-pxs2.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "../init.h" +#include "../sc-regs.h" + +int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + if (spl_boot_device() != BOOT_DEVICE_NAND) { + tmp = readl(SC_RSTCTRL); + tmp &= ~SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + }; + + tmp = readl(SC_RSTCTRL4); + tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | + SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | + SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 | + SC_RSTCTRL4_NRST_UMC30; + writel(tmp, SC_RSTCTRL4); + readl(SC_RSTCTRL4); /* dummy read */ + + /* provide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; + writel(tmp, SC_CLKCTRL); + + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 | + SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0; + writel(tmp, SC_CLKCTRL4); + readl(SC_CLKCTRL4); /* dummy read */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile deleted file mode 100644 index 755a3618b5..0000000000 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c deleted file mode 100644 index c94d83c4ed..0000000000 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include "../init.h" -#include "../sc64-regs.h" - -int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL7); - tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30; - writel(tmp, SC_RSTCTRL7); - - /* provide clocks */ - tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_PERI; - writel(tmp, SC_CLKCTRL4); - - tmp = readl(SC_CLKCTRL7); - tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; - writel(tmp, SC_CLKCTRL7); - - return 0; -} diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c deleted file mode 100644 index 5201a55940..0000000000 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2016 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include "../init.h" -#include "../sc64-regs.h" - -int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL7); - tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | - SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | - SC_RSTCTRL7_UMC30; - writel(tmp, SC_RSTCTRL7); - - /* provide clocks */ - tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_PERI; - writel(tmp, SC_CLKCTRL4); - - tmp = readl(SC_CLKCTRL7); - tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | - SC_CLKCTRL7_UMC30; - writel(tmp, SC_CLKCTRL7); - - return 0; -} diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld4.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld4.c deleted file mode 100644 index b6e8b646f9..0000000000 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ld4.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "../init.h" -#include "../sc-regs.h" - -int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); - - tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; - if (spl_boot_device() != BOOT_DEVICE_NAND) - tmp &= ~SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - - /* provide clocks */ - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ - - return 0; -} diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pro5.c b/arch/arm/mach-uniphier/early-clk/early-clk-pro5.c deleted file mode 100644 index c41a8ead2e..0000000000 --- a/arch/arm/mach-uniphier/early-clk/early-clk-pro5.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include "../init.h" -#include "../sc-regs.h" - -int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd) -{ - u32 tmp; - - /* - * deassert reset - * UMCA2: Ch1 (DDR3) - * UMCA1, UMC31: Ch0 (WIO1) - * UMCA0, UMC30: Ch0 (WIO0) - */ - tmp = readl(SC_RSTCTRL4); - tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | - SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | - SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; - writel(tmp, SC_RSTCTRL4); - readl(SC_RSTCTRL); /* dummy read */ - - /* provide clocks */ - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 | - SC_CLKCTRL4_CEN_UMC0; - writel(tmp, SC_CLKCTRL4); - readl(SC_CLKCTRL4); /* dummy read */ - - return 0; -} diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c b/arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c deleted file mode 100644 index 665ecd510f..0000000000 --- a/arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "../init.h" -#include "../sc-regs.h" - -int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd) -{ - u32 tmp; - - /* deassert reset */ - if (spl_boot_device() != BOOT_DEVICE_NAND) { - tmp = readl(SC_RSTCTRL); - tmp &= ~SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); - }; - - tmp = readl(SC_RSTCTRL4); - tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | - SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | - SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 | - SC_RSTCTRL4_NRST_UMC30; - writel(tmp, SC_RSTCTRL4); - readl(SC_RSTCTRL4); /* dummy read */ - - /* provide clocks */ - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - - tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 | - SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0; - writel(tmp, SC_CLKCTRL4); - readl(SC_CLKCTRL4); /* dummy read */ - - return 0; -} diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile deleted file mode 100644 index db22ba4ae1..0000000000 --- a/arch/arm/mach-uniphier/pll/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pll-init-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-init-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pll-init-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-init-sld8.o diff --git a/arch/arm/mach-uniphier/pll/pll-init-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ld4.c deleted file mode 100644 index a40b30d0e0..0000000000 --- a/arch/arm/mach-uniphier/pll/pll-init-ld4.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2013-2014 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "../init.h" -#include "../sc-regs.h" - -#undef DPLL_SSC_RATE_1PER - -int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) -{ - unsigned int dram_freq = bd->dram_freq; - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT (DPLLCTRL.bit[29:20]) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x000f0000; - switch (dram_freq) { - case 1333: - tmp |= 0x000d0000; - break; - case 1600: - tmp |= 0x000c0000; - break; - default: - pr_err("Unsupported frequency"); - return -EINVAL; - } - -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~SC_DPLLCTRL_SSC_RATE; -#else - tmp |= SC_DPLLCTRL_SSC_RATE; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); - - /* Wait 500 usec until dpll gets stable */ - udelay(500); - - return 0; -} diff --git a/arch/arm/mach-uniphier/pll/pll-init-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-pro4.c deleted file mode 100644 index 3ac48d6365..0000000000 --- a/arch/arm/mach-uniphier/pll/pll-init-pro4.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2013-2014 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "../init.h" -#include "../sc-regs.h" - -#undef DPLL_SSC_RATE_1PER - -int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) -{ - unsigned int dram_freq = bd->dram_freq; - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT ( DPLLCTRL.bit[29:20] ) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~(0x000f0000); - switch (dram_freq) { - case 1333: - tmp |= 0x000d0000; - break; - case 1600: - tmp |= 0x000c0000; - break; - default: - pr_err("Unsupported frequency"); - return -EINVAL; - } - - /* - * Set Moduration rate - * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) - */ -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~0x00008000; -#else - tmp |= 0x00008000; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); - - /* Wait until dpll gets stable */ - udelay(500); - - return 0; -} diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-sld3.c deleted file mode 100644 index 0eb310ceb8..0000000000 --- a/arch/arm/mach-uniphier/pll/pll-init-sld3.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" - -int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd) -{ - /* add pll init code here */ - return 0; -} diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-sld8.c deleted file mode 100644 index 7faa5e85b6..0000000000 --- a/arch/arm/mach-uniphier/pll/pll-init-sld8.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2013-2014 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include "../init.h" -#include "../sc-regs.h" - -int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) -{ - u32 tmp; - /* - * Set DPLL SSC parameters for DPLLCTRL3 - * [23] DIVN_TEST 0x1 - * [22:16] DIVN 0x50 - * [10] FREFSEL_TEST 0x1 - * [9:8] FREFSEL 0x2 - * [4] ICPD_TEST 0x1 - * [3:0] ICPD 0xb - */ - tmp = readl(SC_DPLLCTRL3); - tmp &= ~0x00ff0717; - tmp |= 0x00d0061b; - writel(tmp, SC_DPLLCTRL3); - - /* - * Set DPLL SSC parameters for DPLLCTRL - * <-1%> <-2%> - * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) - * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x3ff07fff; -#ifdef DPLL_SSC_RATE_1PER - tmp |= 0x084018bf; -#else - tmp |= 0x084031a6; -#endif - writel(tmp, SC_DPLLCTRL); - - /* - * Set DPLL SSC parameters for DPLLCTRL2 - * [31:29] SSC_STEP 0 - * [27] SSC_REG_REF 1 - * [26:20] SSC_M 79 (0x4f) - * [19:0] SSC_K 964689 (0xeb851) - */ - tmp = readl(SC_DPLLCTRL2); - tmp &= ~0xefffffff; - tmp |= 0x0cfeb851; - writel(tmp, SC_DPLLCTRL2); - - /* Wait 500 usec until dpll gets stable */ - udelay(500); - - return 0; -}