From: Lokesh Vutla Date: Thu, 13 Jun 2019 04:59:49 +0000 (+0530) Subject: board: ti: j721e: Add board support for j721e evm X-Git-Tag: v2019.10-rc1~8^2~27 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=f81850322af1abd367d64a68d34cd07f823a45d2;p=oweals%2Fu-boot.git board: ti: j721e: Add board support for j721e evm Add board specific initialization for j721e evm Signed-off-by: Lokesh Vutla Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Andreas Dannenberg --- diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index bf90d49b47..9652c96a78 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -113,4 +113,5 @@ config SYS_K3_SPL_ATF after SPL from R5. source "board/ti/am65x/Kconfig" +source "board/ti/j721e/Kconfig" endif diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig new file mode 100644 index 0000000000..c2deb6916a --- /dev/null +++ b/board/ti/j721e/Kconfig @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ +# Lokesh Vutla + +choice + prompt "K3 J721E based boards" + optional + +config TARGET_J721E_A72_EVM + bool "TI K3 based J721E EVM running on A72" + select ARM64 + select SOC_K3_J721E + select SYS_DISABLE_DCACHE_OPS + +config TARGET_J721E_R5_EVM + bool "TI K3 based J721E EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select SOC_K3_J721E + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_J721E_A72_EVM + +config SYS_BOARD + default "j721e" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "j721e_evm" + +endif + +if TARGET_J721E_R5_EVM + +config SYS_BOARD + default "j721e" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "j721e_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +endif diff --git a/board/ti/j721e/Makefile b/board/ti/j721e/Makefile new file mode 100644 index 0000000000..97535f5d86 --- /dev/null +++ b/board/ti/j721e/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ +# Lokesh Vutla +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c new file mode 100644 index 0000000000..43d502b6ca --- /dev/null +++ b/board/ti/j721e/evm.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for J721E EVM + * + * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + * + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + + return 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + + return gd->ram_top; +} + +int dram_init_banksize(void) +{ + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR high region */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; +#endif + + return 0; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, "k3-j721e-common-proc-board")) + return 0; + + return -1; +} +#endif diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h new file mode 100644 index 0000000000..5b35e22c85 --- /dev/null +++ b/include/configs/j721e_evm.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 J721E EVM + * + * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#ifndef __CONFIG_J721E_EVM_H +#define __CONFIG_J721E_EVM_H + +#include +#include +#include + +#define CONFIG_ENV_SIZE (128 << 10) + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +/* SPL Loader Configuration */ +#ifdef CONFIG_TARGET_J721E_A72_EVM +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000 +#else +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location filled in by the boot ROM that we want to read out without any + * interference from the C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 +#endif + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_CQSPI_REF_CLK 133333333 + +/* U-Boot general configuration */ +#define EXTRA_ENV_J721E_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv fdtfile ${default_device_tree};" \ + "setenv overlay_files ${name_overlays}\0" \ + "loadaddr=0x80080000\0" \ + "fdtaddr=0x82000000\0" \ + "overlayaddr=0x83000000\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $overlay_files;" \ + "do;" \ + "load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${overlayaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_J721E_BOARD_SETTINGS \ + EXTRA_ENV_J721E_BOARD_SETTINGS_MMC + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_J721E_EVM_H */