From: Zoltan Herpai Date: Fri, 8 Jan 2016 20:37:43 +0000 (+0000) Subject: packages: bump uboot-sunxi to 2016.01-rc3, along with H3 PSCI/SMP patches X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=f15fc140f1e93ea2fbe1769782968a248bb4f5df;p=librecmc%2Flibrecmc.git packages: bump uboot-sunxi to 2016.01-rc3, along with H3 PSCI/SMP patches Signed-off-by: Zoltan HERPAI SVN-Revision: 48154 --- diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index 8471bb3cf4..a0e761c858 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -9,13 +9,13 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=u-boot -PKG_VERSION:=2016.01-rc2 +PKG_VERSION:=2016.01-rc3 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ http://mirror2.openwrt.org/sources \ ftp://ftp.denx.de/pub/u-boot -PKG_MD5SUM:=aca6c7a38534812ab529e90aae976422 +PKG_MD5SUM:=8ec1743d75448bd3d0c73f8722db9213 PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION) diff --git a/package/boot/uboot-sunxi/patches/003-fix-h3-dramclk.patch b/package/boot/uboot-sunxi/patches/003-fix-h3-dramclk.patch new file mode 100644 index 0000000000..46784ef93a --- /dev/null +++ b/package/boot/uboot-sunxi/patches/003-fix-h3-dramclk.patch @@ -0,0 +1,28 @@ +From 0892c1d5371263e2a02c6fd484fa9647439a7ec9 Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Wed, 23 Dec 2015 11:48:40 +0100 +Subject: [PATCH] sunxi: Remove Orangepi PC RAM speed to 624 MHz + +There are some reports of stability issues at 672 MHz, see: +http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit + +So reduce the DRAM speed to 624MHz which seems to be reliable everywhere. + +Signed-off-by: Hans de Goede +--- + configs/orangepi_pc_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig +index 75afca9..358caa5 100644 +--- a/configs/orangepi_pc_defconfig ++++ b/configs/orangepi_pc_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + # CONFIG_VIDEO is not set diff --git a/package/boot/uboot-sunxi/patches/010-sunxi-support-smta.patch b/package/boot/uboot-sunxi/patches/010-sunxi-support-smta.patch new file mode 100644 index 0000000000..87d381555f --- /dev/null +++ b/package/boot/uboot-sunxi/patches/010-sunxi-support-smta.patch @@ -0,0 +1,60 @@ +diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile +index dfb0a3e..7a6a3cc 100644 +--- a/arch/arm/cpu/armv7/sunxi/Makefile ++++ b/arch/arm/cpu/armv7/sunxi/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o + endif + obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o + obj-$(CONFIG_MACH_SUN6I) += tzpc.o ++obj-$(CONFIG_MACH_SUN8I) += tzpc.o + + obj-$(CONFIG_AXP152_POWER) += pmic_bus.o + obj-$(CONFIG_AXP209_POWER) += pmic_bus.o +diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c +index 5c9c69b..6c8a0fd 100644 +--- a/arch/arm/cpu/armv7/sunxi/tzpc.c ++++ b/arch/arm/cpu/armv7/sunxi/tzpc.c +@@ -13,6 +13,15 @@ void tzpc_init(void) + { + struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE; + ++#ifdef CONFIG_MACH_SUN6I + /* Enable non-secure access to the RTC */ +- writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set); ++ writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set); ++#endif ++ ++#ifdef CONFIG_MACH_SUN8I_H3 ++ /* Enable non-secure access to all peripherals */ ++ writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set); ++ writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set); ++ writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set); ++#endif + } +diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h +index ba4d43b..95c55cd 100644 +--- a/arch/arm/include/asm/arch-sunxi/tzpc.h ++++ b/arch/arm/include/asm/arch-sunxi/tzpc.h +@@ -13,10 +13,21 @@ struct sunxi_tzpc { + u32 decport0_status; /* 0x04 Status of decode protection port 0 */ + u32 decport0_set; /* 0x08 Set decode protection port 0 */ + u32 decport0_clear; /* 0x0c Clear decode protection port 0 */ ++ /* For A80 and later SoCs */ ++ u32 decport1_status; /* 0x10 Status of decode protection port 1 */ ++ u32 decport1_set; /* 0x14 Set decode protection port 1 */ ++ u32 decport1_clear; /* 0x18 Clear decode protection port 1 */ ++ u32 decport2_status; /* 0x1c Status of decode protection port 2 */ ++ u32 decport2_set; /* 0x20 Set decode protection port 2 */ ++ u32 decport2_clear; /* 0x24 Clear decode protection port 2 */ + }; + #endif + +-#define SUNXI_TZPC_DECPORT0_RTC (1 << 1) ++#define SUN6I_TZPC_DECPORT0_RTC (1 << 1) ++ ++#define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe ++#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff ++#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f + + void tzpc_init(void); + diff --git a/package/boot/uboot-sunxi/patches/011-sunxi-support-h3-ccu.patch b/package/boot/uboot-sunxi/patches/011-sunxi-support-h3-ccu.patch new file mode 100644 index 0000000000..495b3a94ce --- /dev/null +++ b/package/boot/uboot-sunxi/patches/011-sunxi-support-h3-ccu.patch @@ -0,0 +1,83 @@ +diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c +index 47fb70f..5cc5d25 100644 +--- a/arch/arm/cpu/armv7/sunxi/clock.c ++++ b/arch/arm/cpu/armv7/sunxi/clock.c +@@ -14,12 +14,17 @@ + #include + #include + ++__weak void clock_init_sec(void) ++{ ++} ++ + int clock_init(void) + { + #ifdef CONFIG_SPL_BUILD + clock_init_safe(); + #endif + clock_init_uart(); ++ clock_init_sec(); + + return 0; + } +diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +index 4501884..d0085e8 100644 +--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c ++++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +@@ -45,6 +45,19 @@ void clock_init_safe(void) + } + #endif + ++void clock_init_sec(void) ++{ ++ struct sunxi_ccm_reg * const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ ++#ifdef CONFIG_MACH_SUN8I_H3 ++ setbits_le32(&ccm->ccu_sec_switch, ++ CCM_SEC_SWITCH_MBUS_NONSEC | ++ CCM_SEC_SWITCH_BUS_NONSEC | ++ CCM_SEC_SWITCH_PLL_NONSEC); ++#endif ++} ++ + void clock_init_uart(void) + { + #if CONFIG_CONS_INDEX < 5 +diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h +index 8ca58ae..6c0573f 100644 +--- a/arch/arm/include/asm/arch-sunxi/clock.h ++++ b/arch/arm/include/asm/arch-sunxi/clock.h +@@ -30,6 +30,7 @@ int clock_init(void); + int clock_twi_onoff(int port, int state); + void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); + void clock_init_safe(void); ++void clock_init_sec(void); + void clock_init_uart(void); + #endif + +diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +index 5c76275..554d858 100644 +--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h ++++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +@@ -137,6 +137,8 @@ struct sunxi_ccm_reg { + u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ + u32 reserved24; + u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ ++ u32 reserved25[5]; ++ u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */ + }; + + /* apb2 bit field */ +@@ -375,6 +377,11 @@ struct sunxi_ccm_reg { + #define CCM_DE_CTRL_PLL10 (5 << 24) + #define CCM_DE_CTRL_GATE (1 << 31) + ++/* CCU security switch, H3 only */ ++#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2) ++#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1) ++#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0) ++ + #ifndef __ASSEMBLY__ + void clock_set_pll1(unsigned int hz); + void clock_set_pll3(unsigned int hz); diff --git a/package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch b/package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch new file mode 100644 index 0000000000..78d784f94e --- /dev/null +++ b/package/boot/uboot-sunxi/patches/012-sunxi-support-psci-on-h3.patch @@ -0,0 +1,22 @@ +diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +index 4ff46e4..90b5bfd 100644 +--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S ++++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +@@ -106,7 +106,7 @@ psci_fiq_enter: + str r10, [r8, #0x100] + timer_wait r10, ONE_MS + +-#ifdef CONFIG_MACH_SUN6I ++#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) + @ Activate power clamp + lsl r12, r9, #2 @ x4 + add r12, r12, r8 +@@ -170,7 +170,7 @@ psci_cpu_on: + movw r0, #(SUNXI_PRCM_BASE & 0xffff) + movt r0, #(SUNXI_PRCM_BASE >> 16) + +-#ifdef CONFIG_MACH_SUN6I ++#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) + @ Release power clamp + lsl r5, r1, #2 @ 1 register per CPU + add r5, r5, r0 @ PRCM diff --git a/package/boot/uboot-sunxi/patches/013-sunxi-enable-booting-nonsec_HYP-on-h3.patch b/package/boot/uboot-sunxi/patches/013-sunxi-enable-booting-nonsec_HYP-on-h3.patch new file mode 100644 index 0000000000..dfde4e86c1 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/013-sunxi-enable-booting-nonsec_HYP-on-h3.patch @@ -0,0 +1,16 @@ +diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig +index 9d67847..28e6bb4 100644 +--- a/board/sunxi/Kconfig ++++ b/board/sunxi/Kconfig +@@ -71,8 +71,11 @@ config MACH_SUN8I_A33 + config MACH_SUN8I_H3 + bool "sun8i (Allwinner H3)" + select CPU_V7 ++ select CPU_V7_HAS_NONSEC ++ select CPU_V7_HAS_VIRT + select SUNXI_GEN_SUN6I + select SUPPORT_SPL ++ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + + config MACH_SUN8I_A83T + bool "sun8i (Allwinner A83T)"