From: Wolfgang Denk Date: Mon, 15 Jan 2007 12:41:04 +0000 (+0100) Subject: Merge with /home/hs/SC3/u-boot X-Git-Tag: v1.3.0-rc1~191 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=f11033e739017c5c4eac55f859b8b222ee8d602c;p=oweals%2Fu-boot.git Merge with /home/hs/SC3/u-boot Some code cleanup. --- f11033e739017c5c4eac55f859b8b222ee8d602c diff --cc CHANGELOG index 41040ef70d,e0b9be9d2d..5bc95fac49 --- a/CHANGELOG +++ b/CHANGELOG @@@ -1,211 -1,3 +1,314 @@@ ++commit 5a5c56986a9ccf71642c8b6374eb18487b15fecd ++Author: Stefan Roese ++Date: Mon Jan 15 09:46:29 2007 +0100 ++ ++ [PATCH] Fix 440SPe rev B detection from previous patch ++ ++ Signed-off-by: Stefan Roese ++ ++commit a443d31410c571ee8f970da819a44d698fdd6b1f ++Author: Heiko Schocher ++Date: Sun Jan 14 13:35:31 2007 +0100 ++ ++ [FIX] correct I2C Writes for the LM81 Sensor. ++ ++ Signed-off-by: Heiko Schocher ++ ++commit 0bba5452835f19a61204edcda3a58112fd8e2208 ++Author: Wolfgang Denk ++Date: Sat Jan 13 11:17:10 2007 +0100 ++ ++ Undo commit 3033ebb2: reset command does not take any arguments ++ ++ Haiying Wang's modification to the reset command was broken, undo it. ++ ++ Signed-off-by: Wolfgang Denk ++ ++commit 95981778cff0038fd9941044d6a3eda810e33258 ++Author: Stefan Roese ++Date: Sat Jan 13 08:01:03 2007 +0100 ++ ++ [PATCH] Update 440SP(e) cpu revisions ++ ++ Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's. ++ ++ Signed-off-by: Stefan Roese ++ ++commit 77ddc5b9afb325262fd88752ba430a1dded1f0c7 ++Author: Stefan Roese ++Date: Sat Jan 13 07:59:56 2007 +0100 ++ ++ [PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed ++ ++ Now the board revision and the current PCI bus speed are printed after ++ the board message. ++ ++ Also the EBC initialising is now done via defines in the board config ++ file. ++ ++ Signed-off-by: Stefan Roese ++ ++commit 36adff362c2c0141ff8a810d42a7e478f779130f ++Author: Stefan Roese ++Date: Sat Jan 13 07:59:19 2007 +0100 ++ ++ [PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed ++ ++ Now the board revision and the current PCI bus speed are printed after ++ the board message. ++ ++ Also the EBC initialising is now done via defines in the board config ++ file. ++ ++ Signed-off-by: Stefan Roese ++ ++commit e0b9ea8c8a294de6a5350ae638879d24b5b709d6 ++Author: Stefan Roese ++Date: Sat Jan 13 07:57:51 2007 +0100 ++ ++ [PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speed ++ ++ Now the board revision and the current PCI bus speed are printed after ++ the board message. ++ ++ Signed-off-by: Stefan Roese ++ ++commit 6abaee42621c07e81a2cd189ad4368b5e8c50280 ++Author: Reinhard Thies ++Date: Wed Jan 10 14:41:14 2007 +0100 ++ ++ Adjusted default environment for cam5200 board. ++ ++commit bab5a90d4ccc1a46a8127b867fa59028cc623ad9 ++Author: Wolfgang Denk ++Date: Wed Jan 10 15:35:52 2007 +0100 ++ ++ Update CHANGELOG ++ +commit 787fa15860a57833e50bd30555079a9cd4e519b8 +Author: Wolfgang Denk +Date: Wed Jan 10 01:28:39 2007 +0100 + + Fix auto_update for MCC200 board. + + The invocation of do_auto_update() is moved to the end of the + misc_init_r() function, after the flash mappings have been + initialized. Please find attached a patch that implements that + change. + + Also correct the decoding of the keypad status. With this update, the + key that will trigger the update is Column 2, Row 2. + ++commit d9384de2f571046e71081bae22b49e3d5ca2e3d5 ++Author: Marian Balakowicz ++Date: Wed Jan 10 00:26:15 2007 +0100 ++ ++ CAM5200 flash driver modifications: ++ - use CFI driver (replaces custom flash driver) for main 'cam5200' target ++ - add second build target 'cam5200_niosflash' which still uses custom driver ++ +commit 67fea022fa957f59653b5238c7496f80a6b70432 +Author: Markus Klotzbuecher +Date: Tue Jan 9 16:02:48 2007 +0100 + + SPC1920: cleanup memory contoller setup + +commit 8fc2102faa23593c80381437c09f7745a14deb40 +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:14 2007 +0100 + + Fix the cpu speed setup to work with all boards. + +commit 9295acb77481cf099ef9b40e1fa2d145b3c7490c +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:13 2007 +0100 + + SPC1920: add support for the FM18L08 Ramtron FRAM + +commit 38ccd2fdf3364a53fe80e9b365303ecdafc9e223 +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:13 2007 +0100 + + SPC1920: update the HPI register addresses to work with the second + generation of hardware + +commit 5921e5313fc3eadd42770c2b99badd7fae5ecf1e +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:13 2007 +0100 + + Miscellanious spc1920 related cleanups + +commit e4c2d37adc8bb1bf69dcf600cbc6c75f916a6120 +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:12 2007 +0100 + + SPC1920 GO/NOGO led should be set to color red in U-Boot + +commit 0be62728aac459ba268d6d752ed49ec0e2bc7348 +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:12 2007 +0100 + + Add support for the DS3231 RTC + +commit 8139567b60d678584b05f0718a681f2047c5e14f +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:11 2007 +0100 + + SMC1 uses external CLK4 instead of BRG on spc1920 + +commit d8d9de1a02fbd880b613d607143d1f57342affc7 +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:10 2007 +0100 + + Update the SPC1920 CMB PLD driver + +commit 3f34f869162750e5e999fd140f884f5de952bcfe +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:10 2007 +0100 + + Add / enable I2C support on the spc1920 board + +commit d28707dbce1e9ac2017ad051da4133bf22b4204f +Author: Markus Klotzbuecher +Date: Tue Jan 9 14:57:10 2007 +0100 + + Add support for the tms320671x host port interface (HPI) + +commit f4eb54529bb3664c3a562e488b460fe075f79d67 +Author: Wolfgang Denk +Date: Sun Jan 7 00:13:11 2007 +0100 + + Prepare for release 1.2.0 + +commit f07ae7a9daef27a3d0213a4f3fe39d5342173c02 +Author: Stefan Roese +Date: Sat Jan 6 15:58:09 2007 +0100 + + [PATCH] 44x: Fix problem with DDR controller setup (refresh rate) + + This patch fixes a problem with an incorrect setup for the refresh + timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c + + Signed-off-by: Stefan Roese + +commit f16c1da9577f06c5fc08651a4065537407de4635 +Author: Stefan Roese +Date: Sat Jan 6 15:56:13 2007 +0100 + + [PATCH] Update ALPR board files + + This update brings the ALPR board support to the newest version. + It also fixes a problem with the NAND driver. + + Signed-off-by: Stefan Roese + +commit cd1d937f90250a32988c37b2b4af8364d25de8ed +Author: Stefan Roese +Date: Fri Jan 5 11:46:05 2007 +0100 + + [PATCH] nand: Fix problem with oobsize calculation + + Here the description from Brian Brelsford : + + The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part + returns a 0x15. In the code fragment below bits [1:0] determine the + page size, it is ANDed via "(extid & 0x3)" then shifted out. The + next field is also ANDed with 0x3. However this is a one bit field + as defined in the Hynix and Samsung parts in the 4th ID byte that + determins the oobsize, not a two bit field. It works on Samsung as + bits[3:2] are 01. However for the Hynix there is a 11 in these two + bits, so the oob size gets messed up. + + I checked the correct linux code and the suggested fix from Brian is + also available in the linux nand mtd driver. + + Signed-off-by: Stefan Roese + +commit a78bc443ae5a4a8ba87590587d5e35bf5a787b2e +Author: Stefan Roese +Date: Fri Jan 5 10:40:36 2007 +0100 + + [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx) + + This fix will make the MAL burst disabling patch for the Linux + EMAC driver obsolete. + + Signed-off-by: Stefan Roese + +commit 023889838282b6237b401664f22dd22dfba2c066 +Author: Stefan Roese +Date: Fri Jan 5 10:38:05 2007 +0100 + + [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board + + This code will optimize the DDR2 controller setup on a board specific + basis. + + Note: This code doesn't work right now on the NAND booting image for the + Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. + + Signed-off-by: Stefan Roese + +commit cce4acbb68398634b8d011ed7bb0d12269c84230 +Author: Bartlomiej Sieka +Date: Thu Dec 28 19:08:21 2006 +0100 + + Few V38B changes: + - fix a typo in V38B config file + - move watchdog initialisation earlier in the boot process + - add "wdt=off" to default kernel command line (disables kernel watchdog) + +commit 92eb729bad876725aeea908d2addba0800620840 +Author: Wolfgang Denk +Date: Wed Dec 27 01:26:13 2006 +0100 + + Fix bug in adaption of Stefano Babic's CFI driver patch. + +commit 9c0f42ecfe25f7ffce8ec7a815f03864d723ffe3 +Author: Wolfgang Denk +Date: Sun Dec 24 01:42:57 2006 +0100 + + Minor code cleanup. + +commit d784fdb05900ada3686d5778783e1fb328e9fb66 +Author: Stefano Babic +Date: Tue Dec 12 00:22:42 2006 +0100 + + Fix cfi failure with Spansion Flash (Spansion Flash Devices have a different offset to go into CFI mode) + +commit 1b3c360c235dc684ec06c2d5f183f0a282ce45e2 +Author: Stefan Roese +Date: Fri Dec 22 14:29:40 2006 +0100 + + [PATCH] Fix sequoia flash autodetection (finally correct) + + Now 32MByte and 64MByte FLASH is know to work and other + configurations should work too. + + Signed-off-by: Stefan Roese + +commit 82e5236a8b719543643fd26d5827938ab2b94818 +Author: Wolfgang Denk +Date: Fri Dec 22 10:30:26 2006 +0100 + + Minor code cleanup; update CHANGELOG. + +commit fa23044564091f05d9695beb7b5b9a931e7f41a4 +Author: Heiko Schocher +Date: Thu Dec 21 17:17:02 2006 +0100 + + Added support for the TQM8272 board from TQ + + Signed-off-by: Heiko Schocher + ++commit 6dedf3d49dd14c3bf541c8ecee7ffaac5f0e1d6c ++Author: Heiko Schocher ++Date: Thu Dec 21 16:14:48 2006 +0100 ++ ++ [PATCH] Add support for the UC101 board from MAN. ++ ++ Signed-off-by: Heiko Schocher ++ commit c84bad0ef60e7055ab0bd49b93069509cecc382a Author: Bartlomiej Sieka Date: Wed Dec 20 00:29:43 2006 +0100 diff --cc Makefile index aa6266f3f6,28c6aec4de..01349f128c --- a/Makefile +++ b/Makefile @@@ -1200,6 -1193,9 +1200,9 @@@ sequoia_nand_config: unconfi @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk -SOLIDCARD3_config:unconfig ++solidcard3_config:unconfig + @./mkconfig $(@:_config=) ppc ppc4xx solidcard3 + sycamore_config: unconfig @echo "Configuring for sycamore board as subset of walnut..." @$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc diff --cc board/amcc/sequoia/sdram.h index 48966cfd6f,0000000000..7f847aa2ad mode 100644,000000..100644 --- a/board/amcc/sequoia/sdram.h +++ b/board/amcc/sequoia/sdram.h @@@ -1,508 -1,0 +1,505 @@@ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPD_SDRAM_DENALI_H_ +#define _SPD_SDRAM_DENALI_H_ + +#define ppcMsync sync +#define ppcMbar eieio + +/* General definitions */ +#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */ +#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */ +#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */ +#define SDRAM_NONE 0 /* No DIMM detected in Slot */ +#define MAXRANKS 2 /* 2 ranks maximum */ + +/* Supported PLB Frequencies */ +#define PLB_FREQ_133MHZ 133333333 +#define PLB_FREQ_152MHZ 152000000 +#define PLB_FREQ_160MHZ 160000000 +#define PLB_FREQ_166MHZ 166666666 + +/* Denali Core Registers */ +#define SDRAM_DCR_BASE 0x10 + +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +/*-----------------------------------------------------------------------------+ + | Values for ddrcfga register - indirect addressing of these regs + +-----------------------------------------------------------------------------*/ + +#define DDR0_00 0x00 +#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +/* Status */ +#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ +/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT0 0x00010000 +/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT1 0x00020000 +/* Bit2. Single correctable ECC event detected */ +#define DDR0_00_INT_STATUS_BIT2 0x00040000 +/* Bit3. Multiple correctable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT3 0x00080000 +/* Bit4. Single uncorrectable ECC event detected. */ +#define DDR0_00_INT_STATUS_BIT4 0x00100000 +/* Bit5. Multiple uncorrectable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT5 0x00200000 +/* Bit6. DRAM initialization complete. */ +#define DDR0_00_INT_STATUS_BIT6 0x00400000 +/* Bit7. Logical OR of all lower bits. */ +#define DDR0_00_INT_STATUS_BIT7 0x00800000 + +#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 +#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_00_DLL_START_POINT_MASK 0x0000007F +#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + - +#define DDR0_01 0x01 +#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 +#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 +#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ +#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_02 0x02 +#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ +#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) +#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) +#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ +#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ +#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_02_START_MASK 0x00000001 +#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) +#define DDR0_02_START_OFF 0x00000000 +#define DDR0_02_START_ON 0x00000001 + +#define DDR0_03 0x03 +#define DDR0_03_BSTLEN_MASK 0x07000000 +#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_03_CASLAT_MASK 0x00070000 +#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 +#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_03_INITAREF_MASK 0x0000000F +#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_04 0x04 +#define DDR0_04_TRC_MASK 0x1F000000 +#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_04_TRRD_MASK 0x00070000 +#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_04_TRTP_MASK 0x00000700 +#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) + +#define DDR0_05 0x05 +#define DDR0_05_TMRD_MASK 0x1F000000 +#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_05_TEMRS_MASK 0x00070000 +#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_05_TRP_MASK 0x00000F00 +#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_05_TRAS_MIN_MASK 0x000000FF +#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#define DDR0_06 0x06 +#define DDR0_06_WRITEINTERP_MASK 0x01000000 +#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_06_TWTR_MASK 0x00070000 +#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_06_TDLL_MASK 0x0000FF00 +#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_06_TRFC_MASK 0x0000007F +#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_07 0x07 +#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 +#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_07_TFAW_MASK 0x001F0000 +#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 +#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_07_AREFRESH_MASK 0x00000001 +#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_08 0x08 +#define DDR0_08_WRLAT_MASK 0x07000000 +#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_08_TCPD_MASK 0x00FF0000 +#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_08_DQS_N_EN_MASK 0x00000100 +#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 +#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_09 0x09 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_09_RTT_0_MASK 0x00030000 +#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 +#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F +#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_10 0x0A +#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ +#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_10_CS_MAP_MASK 0x00000300 +#define DDR0_10_CS_MAP_NO_MEM 0x00000000 +#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 +#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 +#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F +#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) + +#define DDR0_11 0x0B +#define DDR0_11_SREFRESH_MASK 0x01000000 +#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_11_TXSNR_MASK 0x00FF0000 +#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_11_TXSR_MASK 0x0000FF00 +#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) + +#define DDR0_12 0x0C +#define DDR0_12_TCKE_MASK 0x0000007 +#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) + +#define DDR0_13 0x0D + +#define DDR0_14 0x0E +#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 +#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_14_REDUC_MASK 0x00010000 +#define DDR0_14_REDUC_64BITS 0x00000000 +#define DDR0_14_REDUC_32BITS 0x00010000 +#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 +#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) + +#define DDR0_15 0x0F + +#define DDR0_16 0x10 + +#define DDR0_17 0x11 +#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 +#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ +#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) + +#define DDR0_18 0x12 +#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 +#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 +#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 +#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F +#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_19 0x13 +#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 +#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 +#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 +#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F +#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_20 0x14 +#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 +#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 +#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 +#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F +#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_21 0x15 +#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 +#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 +#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 +#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F +#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_22 0x16 +/* ECC */ +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ +#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) + +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 +#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F +#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + - - +#define DDR0_23 0x17 +#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 +#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ +#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ +#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ +#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_24 0x18 +#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 +#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 +#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 +#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 +#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) +#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) + +#define DDR0_25 0x19 +#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ +#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ +#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_26 0x1A +#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 +#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_26_TREF_MASK 0x00003FFF +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_27 0x1B +#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 +#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_27_TINIT_MASK 0x0000FFFF +#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_28 0x1C +#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 +#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF +#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_29 0x1D + +#define DDR0_30 0x1E + +#define DDR0_31 0x1F +#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF +#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_32 0x20 +#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_33 0x21 +#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_34 0x22 +#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_35 0x23 +#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_36 0x24 +#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_37 0x25 +#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_38 0x26 +#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_39 0x27 +#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_40 0x28 +#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_41 0x29 +#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_42 0x2A +#define DDR0_42_ADDR_PINS_MASK 0x07000000 +#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F +#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_43 0x2B +#define DDR0_43_TWR_MASK 0x07000000 +#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_43_APREBIT_MASK 0x000F0000 +#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 +#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 +#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_44 0x2C +#define DDR0_44_TRCD_MASK 0x000000FF +#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#endif /* _SPD_SDRAM_DENALI_H_ */ diff --cc board/mcc200/mcc200.c index 554c51d93f,67969a6010..af047e2a07 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@@ -92,8 -92,8 +92,8 @@@ static void sdram_start (int hi_addr /* * ATTENTION: Although partially referenced initdram does NOT make real use -- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE -- * is something else than 0x00000000. ++ * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE ++ * is something else than 0x00000000. */ long int initdram (int board_type) @@@ -290,9 -294,6 +290,9 @@@ int misc_init_r (void flash_info[0].sector_count = snum; } +#ifdef CONFIG_AUTO_UPDATE - do_auto_update(); ++ do_auto_update(); +#endif return (0); } diff --cc board/solidcard3/init.S index 0000000000,36039e8f8d..e7b3c83949 mode 000000,100644..100644 --- a/board/solidcard3/init.S +++ b/board/solidcard3/init.S @@@ -1,0 -1,383 +1,382 @@@ + /*------------------------------------------------------------------------------+ + * - * This souce code has been made available to you by EuroDesign - * (www.eurodsn.de). It's based on the original IBM source code, so - * this follows: ++ * This souce code has been made available to you by EuroDesign ++ * (www.eurodsn.de). It's based on the original IBM source code, so ++ * this follows: + * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. ++ * This source code has been made available to you by IBM on an AS-IS ++ * basis. Anyone receiving this source is licensed under IBM ++ * copyrights to use it in any way he or she deems fit, including ++ * copying it, modifying it, compiling it, and redistributing it either ++ * with or without modifications. No license under IBM patents or ++ * patent applications is to be implied by the copyright license. + * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. ++ * Any user of this software should understand that IBM cannot provide ++ * technical support for this software and will not be responsible for ++ * any consequences resulting from the use of this software. + * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. ++ * Any person who transfers this source code or any derivative work ++ * must include the IBM copyright notice, this paragraph, and the ++ * preceding two paragraphs in the transferred software. + * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++ * COPYRIGHT I B M CORPORATION 1995 ++ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *------------------------------------------------------------------------------- */ + + #include + #include + + #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + + #include + #include + + #include + #include + + /** + * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals + * + * IMPORTANT: For pass1 this code must run from cache since you can not + * reliably change a peripheral banks timing register (pbxap) while running + * code from that bank. For ex., since we are running from ROM on bank 0, we + * can NOT execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * + * Bank 0 - Boot-Flash + * Bank 1 - NAND-Flash + * Bank 2 - ISA bus + * Bank 3 - Second Flash + * Bank 4 - USB controller + */ + .globl ext_bus_cntlr_init + ext_bus_cntlr_init: + /* + * We need the current boot up configuration to set correct + * timings into internal flash and external flash + */ + mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx - 0 0 -> 8 bit external ROM - 0 1 -> 16 bit internal ROM */ ++ 0 0 -> 8 bit external ROM ++ 0 1 -> 16 bit internal ROM */ + addi r4,0,2 + srw r24,r24,r4 /* shift right r24 two positions */ + andi. r24,r24,0x06000 -/* ++/* + * All calculations are based on 33MHz EBC clock. + * + * First, create a "very slow" timing (~250ns) with burst mode enabled + * This is need for the external flash access + */ + lis r25,0x0800 + ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 + /* + * Second, create a fast timing: + * 90ns first cycle - 3 clock access + * and 90ns burst cycle, plus 1 clock after the last access + * This is used for the internal access + */ + lis r26,0x8900 + ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx + /* + * We can't change settings on CS# if we currently use them. + * -> load a few instructions into cache and run this code from cache + */ + mflr r4 /* save link register */ + bl ..getAddr + ..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function + in cache (gives us 8x10=80 instructions) */ + ..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ + /* + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. 200usec should be enough. + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + */ + lis r3,0x0 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 + ..spinlp: + bdnz ..spinlp /* spin loop */ + + /*----------------------------------------------------------------------- + * Memory Bank 0 (BOOT-ROM) initialization + * 0xFFEF00000....0xFFFFFFF + * We only have to change the timing. Mapping is ok by boot-strapping + *----------------------------------------------------------------------- */ + + li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */ + mtdcr ebccfga,r4 + + mr r4,r26 /* assume internal fast flash is boot flash */ + cmpwi r24,0x2000 /* assumption true? ... */ + beq 1f /* ...yes! */ + mr r4,r25 /* ...no, use the slow variant */ + mr r25,r26 /* use this for the other flash */ + 1: + mtdcr ebccfgd,r4 /* change timing now */ + + li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */ + mtdcr ebccfga,r4 + mfdcr r4,ebccfgd + lis r3,0x0001 + ori r3,r3,0x8000 /* allow reads and writes */ + or r4,r4,r3 + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- - * Memory Bank 3 (Second-Flash) initialization ++ * Memory Bank 3 (Second-Flash) initialization + * 0xF0000000...0xF01FFFFF -> 2MB + *----------------------------------------------------------------------- */ + + li r4,pb3ap /* Peripheral Bank 1 Access Parameter */ + mtdcr ebccfga,r4 + mtdcr ebccfgd,r2 /* change timing */ + + li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */ + mtdcr ebccfga,r4 + + lis r4,0xF003 + ori r4,r4,0x8000 + /* + * Consider boot configuration + */ + xori r24,r24,0x2000 /* invert current bus width */ + or r4,r4,r24 + mtdcr ebccfgd,r4 - ++ + /*----------------------------------------------------------------------- + * Memory Bank 1 (NAND-Flash) initialization + * 0x77D00000...0x77DFFFFF -> 1MB + * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns + * - the setup time is 0ns + * - the hold time is 15ns + * -> + * - TWT = 0 + * - CSN = 0 + * - OEN = 0 + * - WBN = 0 + * - WBF = 0 + * - TH = 1 + * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold) + *----------------------------------------------------------------------- */ + + li r4,pb1ap /* Peripheral Bank 1 Access Parameter */ + mtdcr ebccfga,r4 + + lis r4,0x0000 + ori r4,r4,0x0200 + mtdcr ebccfgd,r4 + + li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */ + mtdcr ebccfga,r4 + + lis r4,0x77D1 + ori r4,r4,0x8000 + mtdcr ebccfgd,r4 + + + /* USB init (without acceleration) */ + #ifndef CONFIG_ISP1161_PRESENT + li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ + mtdcr ebccfga,r4 + lis r4,0x0180 - ori r4,r4,0x5940 ++ ori r4,r4,0x5940 + mtdcr ebccfgd,r4 + #endif + + /*----------------------------------------------------------------------- + * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7) + * 0x78000000...0x7BFFFFFF -> 64 MB + * Wir arbeiten bei 33 MHz -> 30ns + *----------------------------------------------------------------------- + + A7 (ppc notation) or A24 (standard notation) decides about + the type of access: + A7/A24=0 -> memory cycle - A7//A24=1 -> I/O cycle ++ A7/ /A24=1 -> I/O cycle + */ + li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */ + mtdcr ebccfga,r4 + /* + We emulate an ISA access + + 1. Address active + 2. wait 0 EBC clocks -> CSN=0 + 3. set CS# + 4. wait 0 EBC clock -> OEN/WBN=0 + 5. set OE#/WE# + 6. wait 4 clocks (ca. 90ns) and for Ready signal + 7. hold for 4 clocks -> TH=4 + */ + + #if 1 + /* faster access to isa-bus */ + lis r4,0x0180 + ori r4,r4,0x5940 + #else + lis r4,0x0100 + ori r4,r4,0x0340 + #endif + mtdcr ebccfgd,r4 + + #ifdef IDE_USES_ISA_EMULATION + li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */ + mtdcr ebccfga,r25 + mtdcr ebccfgd,r4 + #endif + + li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */ + mtdcr ebccfga,r25 + mtdcr ebccfgd,r4 + li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */ + mtdcr ebccfga,r25 + mtdcr ebccfgd,r4 + + li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */ + mtdcr ebccfga,r25 + + lis r4,0x780B + ori r4,r4,0xA000 + mtdcr ebccfgd,r4 + /* + * the other areas are only 1MiB in size + */ + lis r4,0x7401 + ori r4,r4,0xA000 + + li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */ + mtdcr ebccfga,r25 + lis r4,0x7401 - ori r4,r4,0xA000 ++ ori r4,r4,0xA000 + mtdcr ebccfgd,r4 + + li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */ + mtdcr ebccfga,r25 + lis r4,0x7411 + ori r4,r4,0xA000 + mtdcr ebccfgd,r4 + + #ifndef CONFIG_ISP1161_PRESENT + li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */ + mtdcr ebccfga,r25 + lis r4,0x7421 + ori r4,r4,0xA000 + mtdcr ebccfgd,r4 + #endif + #ifdef IDE_USES_ISA_EMULATION + li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */ + mtdcr ebccfga,r25 + lis r4,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + #endif + + /*----------------------------------------------------------------------- + * Memory bank 4: USB controller Philips ISP6111 + * 0x77C00000 ... 0x77CFFFFF + * + * The chip is connected to: + * - CPU CS#4 + * - CPU IRQ#2 + * - CPU DMA 3 + * + * Timing: + * - command to first data: 300ns. Software must ensure this timing! + * - Write pulse: 26ns + * - Read pulse: 33ns + * - read cycle time: 150ns + * - write cycle time: 140ns + * + * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns + * - * |- 300ns --| - * |---- 420ns ---|---- 420ns ---| cycle ++ * |- 300ns --| ++ * |---- 420ns ---|---- 420ns ---| cycle + * CS ############:###____#######:###____####### + * OE ############:####___#######:####___####### + * WE ############:####__########:####__######## + * + * ----> 2 clocks RD/WR pulses: 60ns + * ----> CSN: 3 clock, 90ns + * ----> OEN: 1 clocks (read cycle) + * ----> WBN: 1 clocks (write cycle) + * ----> WBE: 2 clocks + * ----> TH: 7 clock, 210ns + * ----> TWT: 7 clocks + *----------------------------------------------------------------------- */ + + #ifdef CONFIG_ISP1161_PRESENT + + li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ + mtdcr ebccfga,r4 + + lis r4,0x030D + ori r4,r4,0x5E80 + mtdcr ebccfgd,r4 + + li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */ + mtdcr ebccfga,r4 + + lis r4,0x77C1 + ori r4,r4,0xA000 + mtdcr ebccfgd,r4 + + #endif + + #ifndef IDE_USES_ISA_EMULATION + + /*----------------------------------------------------------------------- + * Memory Bank 5 used for IDE access + * + * Timings for IDE Interface + * + * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time + * 70 165 30 PIO-Mode 0, [ns] + * 3 6 1 [Cycles] ----> AP=0x040C0200 + * 50 125 20 PIO-Mode 1, [ns] + * 2 5 1 [Cycles] ----> AP=0x03080200 + * 30 100 15 PIO-Mode 2, [ns] + * 1 4 1 [Cycles] ----> AP=0x02040200 + * 30 80 10 PIO-Mode 3, [ns] + * 1 3 1 [Cycles] ----> AP=0x01840200 + * 25 70 10 PIO-Mode 4, [ns] + * 1 3 1 [Cycles] ----> AP=0x01840200 + * + *----------------------------------------------------------------------- */ + + li r4,pb5ap + mtdcr ebccfga,r4 + lis r4,0x040C + ori r4,r4,0x0200 + mtdcr ebccfgd,r4 + + li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */ + mtdcr ebccfga,r4 + + lis r4,0x7A01 + ori r4,r4,0xA000 + mtdcr ebccfgd,r4 + #endif + /* + * External Peripheral Control Register + */ + li r4,epcr + mtdcr ebccfga,r4 + + lis r4,0xB84E + ori r4,r4,0xF000 + mtdcr ebccfgd,r4 + /* + * drive POST code + */ + lis r4,0x7900 + ori r4,r4,0x0080 + li r3,0x0001 + stb r3,0(r4) /* 01 -> external bus controller is initialized */ + nop /* pass2 DCR errata #8 */ + blr - diff --cc board/solidcard3/sc3nand.c index 0000000000,0000000000..7daa877cdd new file mode 100644 --- /dev/null +++ b/board/solidcard3/sc3nand.c @@@ -1,0 -1,0 +1,94 @@@ ++/* ++ * (C) Copyright 2007 ++ * Heiko Schocher, DENX Software Engineering, hs@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++#if (CONFIG_COMMANDS & CFG_CMD_NAND) ++ ++#include ++#include ++ ++#define readb(addr) *(volatile u_char *)(addr) ++#define readl(addr) *(volatile u_long *)(addr) ++#define writeb(d,addr) *(volatile u_char *)(addr) = (d) ++ ++#define SC3_NAND_ALE 29 /* GPIO PIN 3 */ ++#define SC3_NAND_CLE 30 /* GPIO PIN 2 */ ++#define SC3_NAND_CE 27 /* GPIO PIN 5 */ ++ ++static void *sc3_io_base; ++static void *sc3_control_base = (void *)0xEF600700; ++ ++static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd) ++{ ++ switch (cmd) { ++ case NAND_CTL_SETCLE: ++ set_bit (SC3_NAND_CLE, sc3_control_base); ++ break; ++ case NAND_CTL_CLRCLE: ++ clear_bit (SC3_NAND_CLE, sc3_control_base); ++ break; ++ ++ case NAND_CTL_SETALE: ++ set_bit (SC3_NAND_ALE, sc3_control_base); ++ break; ++ case NAND_CTL_CLRALE: ++ clear_bit (SC3_NAND_ALE, sc3_control_base); ++ break; ++ ++ case NAND_CTL_SETNCE: ++ set_bit (SC3_NAND_CE, sc3_control_base); ++ break; ++ case NAND_CTL_CLRNCE: ++ clear_bit (SC3_NAND_CE, sc3_control_base); ++ break; ++ } ++} ++ ++static int sc3_nand_dev_ready(struct mtd_info *mtd) ++{ ++ if (!(readl(sc3_control_base + 0x1C) & 0x4000)) ++ return 0; ++ return 1; ++} ++ ++static void sc3_select_chip(struct mtd_info *mtd, int chip) ++{ ++ clear_bit (SC3_NAND_CE, sc3_control_base); ++} ++ ++int board_nand_init(struct nand_chip *nand) ++{ ++ nand->eccmode = NAND_ECC_SOFT; ++ ++ sc3_io_base = (void *) CFG_NAND_BASE; ++ /* Set address of NAND IO lines (Using Linear Data Access Region) */ ++ nand->IO_ADDR_R = (void __iomem *) sc3_io_base; ++ nand->IO_ADDR_W = (void __iomem *) sc3_io_base; ++ /* Reference hardware control function */ ++ nand->hwcontrol = sc3_nand_hwcontrol; ++ nand->dev_ready = sc3_nand_dev_ready; ++ nand->select_chip = sc3_select_chip; ++ return 0; ++} ++#endif diff --cc board/solidcard3/solidcard3.c index 0000000000,804471178d..21cc031ef9 mode 000000,100644..100644 --- a/board/solidcard3/solidcard3.c +++ b/board/solidcard3/solidcard3.c @@@ -1,0 -1,779 +1,779 @@@ -/* ++/* + * (C) Copyright 2007 + * Heiko Schocher, DENX Software Engineering, . + * + * (C) Copyright 2003 + * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de + * Derived from walnut.c + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * $Log:$ + */ + + #include + #include + #include + #include "solidcard3.h" + #include + #include + #include + + #undef writel + #undef writeb + #define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) + #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) + + /* write only register to configure things in our CPLD */ + #define CPLD_CONTROL_1 0x79000102 + #define CPLD_VERSION 0x79000103 + + #define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0) + + static struct pci_controller hose={0,}; + + /************************************************************ + * Standard definition + ************************************************************/ + + /* CPC0_CR0 Function ISA bus + - GPIO0 + - GPIO1 -> Output: NAND-Command Latch Enable + - GPIO2 -> Output: NAND Address Latch Enable + - GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD) + - GPIO4 -> Output: NAND-Chip Enable + - GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD) + - GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD) + - GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD) + - GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD) + - GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD) + - GPIO10/CS1# -> CS1# NAND ISA-CS#0 + - GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1 + - GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7 + - GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3 + - GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4 + - GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5 + - GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6 + - GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3 + - GPIO18/IRQ1 -> IRQ input ISA-IRQ#14 + - GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4 + - GPIO20/IRQ3 -> IRQ input PCI-IRQ#D + - GPIO21/IRQ4 -> IRQ input PCI-IRQ#C + - GPIO22/IRQ5 -> IRQ input PCI-IRQ#B + - GPIO23/IRQ6 -> IRQ input PCI-IRQ#A + - GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv + */ + /* + | CPLD register: io-space at offset 0x102 (write only) + | 0 + | 1 + | 2 0=CS#4 USB CS#, 1=ISA or GP bus + | 3 + | 4 + | 5 + | 6 1=enable faster IDE access + | 7 + */ + #define USB_CHIP_ENABLE 0x04 + #define IDE_BOOSTING 0x40 + + /* --------------- USB stuff ------------------------------------- */ + #ifdef CONFIG_ISP1161_PRESENT + /** + * initUsbHost- Initialize the Philips isp1161 HC part if present + * @cpldConfig: Pointer to value in write only CPLD register + * + * Initialize the USB host controller if present and fills the + * scratch register to inform the driver about used resources + */ + + static void initUsbHost (unsigned char *cpldConfig) + { + int i; + unsigned long usbBase; + /* + * Read back where init.S has located the USB chip + */ + mtdcr (0x012, 0x04); + usbBase = mfdcr (0x013); + if (!(usbBase & 0x18000)) /* enabled? */ + return; + usbBase &= 0xFFF00000; + + /* + * to test for the USB controller enable using of CS#4 and DMA 3 for USB access + */ + writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1); + + /* + * first check: is the controller assembled? + */ + hcWriteWord (usbBase, 0x5555, HcScratch); + if (hcReadWord (usbBase, HcScratch) == 0x5555) { + hcWriteWord (usbBase, 0xAAAA, HcScratch); + if (hcReadWord (usbBase, HcScratch) == 0xAAAA) { + if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100) + return; /* this is not our controller */ + /* + * try a software reset. This needs up to 10 seconds (see datasheet) + */ + hcWriteDWord (usbBase, 0x00000001, HcCommandStatus); + for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */ + udelay (10); + if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01)) + break; + } + + if (!i) + return; /* the controller doesn't responding. Broken? */ + /* + * OK. USB controller is ready. Initialize it in such way the later driver + * can us it (without any knowing about specific implementation) + */ + hcWriteDWord (usbBase, 0x00000000, HcControl); + /* + * disable all interrupt sources. Because we + * don't know where we come from (hard reset, cold start, soft reset...) + */ + hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable); + /* + * our current setup hardware configuration + * - every port power supply can switched indepently + * - every port can signal overcurrent + * - every port is "outside" and the devices are removeable + */ + hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA); + hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB); + /* + * don't forget to switch off power supply of each port + * The later running driver can reenable them to find and use + * the (maybe) connected devices. + * + */ + hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1); + hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2); + hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration); + hcWriteWord (usbBase, 0x0040, HcDMAConfiguration); + hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable); + hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch); + /* + * controller is present and usable + */ + *cpldConfig |= USB_CHIP_ENABLE; + } + } + } + #endif + + #if defined(CONFIG_START_IDE) + int board_start_ide(void) + { + if (IS_CAMERON) { + puts ("no IDE on cameron board.\n"); + return 0; + } + return 1; + } + #endif + + static int sc3_cameron_init (void) + { + /* Set up the Memory Controller for the CAMERON version */ + mtebc (pb4ap, 0x01805940); + mtebc (pb4cr, 0x7401a000); + mtebc (pb5ap, 0x01805940); + mtebc (pb5cr, 0x7401a000); + mtebc (pb6ap, 0x0); + mtebc (pb6cr, 0x0); + mtebc (pb7ap, 0x0); + mtebc (pb7cr, 0x0); + return 0; + } + + void sc3_read_eeprom (void) + { + uchar i2c_buffer[18]; + + i2c_read (0x50, 0x03, 1, i2c_buffer, 9); + i2c_buffer[9] = 0; + setenv ("serial#", (char *)i2c_buffer); + + /* read mac-address from eeprom */ + i2c_read (0x50, 0x11, 1, i2c_buffer, 15); + i2c_buffer[17] = 0; + i2c_buffer[16] = i2c_buffer[14]; + i2c_buffer[15] = i2c_buffer[13]; + i2c_buffer[14] = ':'; + i2c_buffer[13] = i2c_buffer[12]; + i2c_buffer[12] = i2c_buffer[11]; + i2c_buffer[11] = ':'; + i2c_buffer[8] = ':'; + i2c_buffer[5] = ':'; + i2c_buffer[2] = ':'; + setenv ("ethaddr", (char *)i2c_buffer); + } + + int board_early_init_f (void) + { + /* write only register to configure things in our CPLD */ + unsigned char cpldConfig_1=0x00; + + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board). + | + | Note: IRQ 0 UART 0, active high; level sensitive + | IRQ 1 UART 1, active high; level sensitive + | IRQ 2 IIC, active high; level sensitive + | IRQ 3 Ext. master, rising edge, edge sensitive + | IRQ 4 PCI, active high; level sensitive + | IRQ 5 DMA Channel 0, active high; level sensitive + | IRQ 6 DMA Channel 1, active high; level sensitive + | IRQ 7 DMA Channel 2, active high; level sensitive + | IRQ 8 DMA Channel 3, active high; level sensitive + | IRQ 9 Ethernet Wakeup, active high; level sensitive + | IRQ 10 MAL System Error (SERR), active high; level sensitive + | IRQ 11 MAL Tx End of Buffer, active high; level sensitive + | IRQ 12 MAL Rx End of Buffer, active high; level sensitive + | IRQ 13 MAL Tx Descriptor Error, active high; level sensitive + | IRQ 14 MAL Rx Descriptor Error, active high; level sensitive + | IRQ 15 Ethernet, active high; level sensitive + | IRQ 16 External PCI SERR, active high; level sensitive + | IRQ 17 ECC Correctable Error, active high; level sensitive + | IRQ 18 PCI Power Management, active high; level sensitive + | + | IRQ 19 (EXT IRQ7 405GPr only) + | IRQ 20 (EXT IRQ8 405GPr only) + | IRQ 21 (EXT IRQ9 405GPr only) + | IRQ 22 (EXT IRQ10 405GPr only) + | IRQ 23 (EXT IRQ11 405GPr only) + | IRQ 24 (EXT IRQ12 405GPr only) + | + | IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready) + | IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive) + | IRQ 27 (EXT IRQ 2) USB controller + | IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive + | IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive + | IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive + | IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive + | + | Direct Memory Access Controller Signal Polarities + | DRQ0 active high (like ISA) + | ACK0 active low (like ISA) + | EOT0 active high (like ISA) + | DRQ1 active high (like ISA) + | ACK1 active low (like ISA) + | EOT1 active high (like ISA) + | DRQ2 active high (like ISA) + | ACK2 active low (like ISA) + | EOT2 active high (like ISA) + | DRQ3 active high (like ISA) + | ACK3 active low (like ISA) + | EOT3 active high (like ISA) + | + +-------------------------------------------------------------------------*/ + + writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */ + + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + + if (IS_CAMERON) { + sc3_cameron_init(); + mtdcr (0x0B6, 0x18000000); + mtdcr (uicpr, 0xFFFFFFF0); + mtdcr (uictr, 0x10001030); + } else { + mtdcr (0x0B6, 0x0000000); + mtdcr (uicpr, 0xFFFFFFE0); + mtdcr (uictr, 0x10000020); + } + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* setup other implementation specific details */ + mtdcr (ecr, 0x60606000); + + mtdcr (cntrl1, 0x000042C0); + + if (IS_CAMERON) { + mtdcr (cntrl0, 0x01380000); + /* Setup the GPIOs */ + writel (0x08008000, 0xEF600700); /* Output states */ + writel (0x00000000, 0xEF600718); /* Open Drain control */ + writel (0x68098000, 0xEF600704); /* Output control */ + } else { + mtdcr (cntrl0,0x00080000); + /* Setup the GPIOs */ + writel (0x08000000, 0xEF600700); /* Output states */ + writel (0x14000000, 0xEF600718); /* Open Drain control */ + writel (0x7C000000, 0xEF600704); /* Output control */ + } + + /* Code decompression disabled */ + mtdcr (kiar, kconf); + mtdcr (kidr, 0x2B); + + /* CPC0_ER: enable sleep mode of (currently) unused components */ + /* CPC0_FR: force unused components into sleep mode */ + mtdcr (cpmer, 0x3F800000); + mtdcr (cpmfr, 0x14000000); + + /* set PLB priority */ + mtdcr (0x87, 0x08000000); + + /* --------------- DMA stuff ------------------------------------- */ + mtdcr (0x126, 0x49200000); + + #ifndef IDE_USES_ISA_EMULATION + cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */ + /* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */ + writeb (cpldConfig_1, CPLD_CONTROL_1); + #endif + + #ifdef CONFIG_ISP1161_PRESENT + initUsbHost (&cpldConfig_1); + writeb (cpldConfig_1, CPLD_CONTROL_1); + #endif + return(0); + } + + int misc_init_r (void) + { + char *s1; + int i, xilinx_val; + volatile char *xilinx_adr; + xilinx_adr = (char *)0x79000102; + + *xilinx_adr = 0x00; + + /* customer settings ***************************************** */ + /* + s1 = getenv ("function"); + if (s1) { + if (!strcmp (s1, "Rosho")) { + printf ("function 'Rosho' activated\n"); + *xilinx_adr = 0x40; + } + else { + printf (">>>>>>>>>> function %s not recognized\n",s1); + } + } + */ + + /* individual settings ***************************************** */ + if ((s1 = getenv ("xilinx"))) { + i=0; + xilinx_val = 0; + while (i < 3 && s1[i]) { + if (s1[i] >= '0' && s1[i] <= '9') + xilinx_val = (xilinx_val << 4) + s1[i] - '0'; + else + if (s1[i] >= 'A' && s1[i] <= 'F') + xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10; + else + if (s1[i] >= 'a' && s1[i] <= 'f') + xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10; + else { + xilinx_val = -1; + break; + } + i++; + } + if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) { + printf ("Xilinx: set to %s\n", s1); + *xilinx_adr = (unsigned char) xilinx_val; + } else + printf ("Xilinx: rejected value %s\n", s1); + } + return 0; + } + + /* ------------------------------------------------------------------------- + * printCSConfig + * + * Print some informations about chips select configurations + * Only used while debugging. + * + * Params: + * - No. of CS pin + * - AP of this CS + * - CR of this CS + * + * Returns + * nothing + ------------------------------------------------------------------------- */ + + #ifdef SC3_DEBUGOUT + static void printCSConfig(int reg,unsigned long ap,unsigned long cr) + { + const char *bsize[4] = {"8","16","32","?"}; + const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128}; + const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"}; + + #define CYCLE 30 /* time of one clock (based on 33MHz) */ + + printf("\nCS#%d",reg); + if (!(cr & 0x00018000)) + puts(" unused"); + else { + if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20))) + puts(" Address is not multiple of bank size!"); + + printf("\n -%s bit device", + bsize[(cr & 0x00006000) >> 13]); + printf(" at 0x%08lX", cr & 0xFFF00000U); + printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]); + printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]); + if (ap & 0x80000000) { + printf("\n -Burst device (%luns/%luns)", + (((ap & 0x7C000000) >> 26) + 1) * CYCLE, + (((ap & 0x03800000) >> 23) + 1) * CYCLE); + } else { + printf("\n -Non burst device, active cycle %luns", + (((ap & 0x7F800000) >> 23) + 1) * CYCLE); + printf("\n -Address setup %luns", + ((ap & 0xC0000) >> 18) * CYCLE); + printf("\n -CS active to RD %luns/WR %luns", - ((ap & 0x30000) >> 16) * CYCLE, ++ ((ap & 0x30000) >> 16) * CYCLE, + ((ap & 0xC000) >> 14) * CYCLE); + printf("\n -WR to CS inactive %luns", + ((ap & 0x3000) >> 12) * CYCLE); + printf("\n -Hold after access %luns", + ((ap & 0xE00) >> 9) * CYCLE); + printf("\n -Ready is %sabled", + ap & 0x100 ? "en" : "dis"); + } + } + } + #endif + + #ifdef SC3_DEBUGOUT + + static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap, + pb5ap, pb6ap, pb7ap}; + static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr, + pb5cr, pb6cr, pb7cr}; + + static int show_reg (int nr) + { + unsigned long ul1, ul2; + + mtdcr (ebccfga, ap[nr]); + ul1 = mfdcr (ebccfgd); + mtdcr (ebccfga, cr[nr]); + ul2 = mfdcr(ebccfgd); + printCSConfig(nr, ul1, ul2); + return 0; + } + #endif + + int checkboard (void) + { + #ifdef SC3_DEBUGOUT + unsigned long ul1; + int i; + + for (i = 0; i < 8; i++) { + show_reg (i); + } - ++ + mtdcr (ebccfga, epcr); + ul1 = mfdcr (ebccfgd); + + puts ("\nGeneral configuration:\n"); + + if (ul1 & 0x80000000) + printf(" -External Bus is always driven\n"); + + if (ul1 & 0x400000) + printf(" -CS signals are always driven\n"); + + if (ul1 & 0x20000) + printf(" -PowerDown after %lu clocks\n", + (ul1 & 0x1F000) >> 7); + + switch (ul1 & 0xC0000) + { + case 0xC0000: + printf(" -No external master present\n"); + break; + case 0x00000: + printf(" -8 bit external master present\n"); + break; + case 0x40000: + printf(" -16 bit external master present\n"); + break; + case 0x80000: + printf(" -32 bit external master present\n"); + break; + } + + switch (ul1 & 0x300000) + { + case 0x300000: + printf(" -Prefetch: Illegal setting!\n"); + break; + case 0x000000: + printf(" -1 doubleword prefetch\n"); + break; + case 0x100000: + printf(" -2 doublewords prefetch\n"); + break; + case 0x200000: + printf(" -4 doublewords prefetch\n"); + break; + } + putc ('\n'); + #endif + printf("Board: SolidCard III %s %s version.\n", + (IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION); + return 0; + } + + static int printSDRAMConfig(char reg, unsigned long cr) + { + const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0}; + #ifdef SC3_DEBUGOUT + const char *basize[8]= + {"4", "8", "16", "32", "64", "128", "256", "Reserved"}; + + printf("SDRAM bank %d",reg); + + if (!(cr & 0x01)) + puts(" disabled\n"); + else { + printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]); + printf(" mode %lu\n",((cr & 0xE000)>>13)+1); + } + #endif + + if (cr & 0x01) + return(bisize[(cr & 0xE0000) >> 17]); + + return 0; + } + + #ifdef SC3_DEBUGOUT + static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf}; + #endif + + long int initdram (int board_type) + { + unsigned int mems=0; + unsigned long ul1; + + #ifdef SC3_DEBUGOUT + unsigned long ul2; + int i; + + puts("\nSDRAM configuration:\n"); + + mtdcr (memcfga, mem_mcopt1); + ul1 = mfdcr(memcfgd); + + if (!(ul1 & 0x80000000)) { + puts(" Controller disabled\n"); + return 0; + } + for (i = 0; i < 4; i++) { + mtdcr (memcfga, mbcf[i]); + ul1 = mfdcr (memcfgd); + mems += printSDRAMConfig (i, ul1); + } + + mtdcr (memcfga, mem_sdtr1); + ul1 = mfdcr(memcfgd); + + printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); + printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1); + printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1); + printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1); + printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); + printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); + puts ("Misc:\n"); + mtdcr (memcfga, mem_rtr); + ul1 = mfdcr(memcfgd); + printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); + + mtdcr(memcfga,mem_pmit); + ul2=mfdcr(memcfgd); + + mtdcr(memcfga,mem_mcopt1); + ul1=mfdcr(memcfgd); + + if (ul1 & 0x20000000) + printf(" -Power Down after: %luns\n", + ((ul2 & 0xFFC00000) >> 22) * 7); + else + puts(" -Power Down disabled\n"); + + if (ul1 & 0x40000000) + printf(" -Self refresh feature active\n"); + else + puts(" -Self refresh disabled\n"); + + if (ul1 & 0x10000000) + puts(" -ECC enabled\n"); + else + puts(" -ECC disabled\n"); + + if (ul1 & 0x8000000) + puts(" -Using registered SDRAM\n"); + + if (!(ul1 & 0x6000000)) + puts(" -Using 32 bit data width\n"); + else + puts(" -Illegal data width!\n"); + + if (ul1 & 0x400000) + puts(" -ECC drivers inactive\n"); + else + puts(" -ECC drivers active\n"); + + if (ul1 & 0x200000) + puts(" -Memory lines always active outputs\n"); + else + puts(" -Memory lines only at write cycles active outputs\n"); + + mtdcr (memcfga, mem_status); + ul1 = mfdcr (memcfgd); + if (ul1 & 0x80000000) + puts(" -SDRAM Controller ready\n"); + else + puts(" -SDRAM Controller not ready\n"); + + if (ul1 & 0x4000000) + puts(" -SDRAM in self refresh mode!\n"); + + return (mems * 1024 * 1024); + #else + mtdcr (memcfga, mem_mb0cf); + ul1 = mfdcr (memcfgd); + mems = printSDRAMConfig (0, ul1); + + mtdcr (memcfga, mem_mb1cf); + ul1 = mfdcr (memcfgd); + mems += printSDRAMConfig (1, ul1); + + mtdcr (memcfga, mem_mb2cf); + ul1 = mfdcr(memcfgd); + mems += printSDRAMConfig (2, ul1); + + mtdcr (memcfga, mem_mb3cf); + ul1 = mfdcr(memcfgd); + mems += printSDRAMConfig (3, ul1); + + return (mems * 1024 * 1024); + #endif + } + + static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev) + { + /*-------------------------------------------------------------------------+ + | ,-. ,-. ,-. ,-. ,-. + | INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G| + | |R| |C| \ / |C| \ / |E| \ / |r| + | INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a| + | |D| |0| \/ |0| \/ |h| \/ |f| + | INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i| + | |E| |+| /\ |+| /\ |r| /\ |k| + | INTA# ----| |-----| |- `----| |- `----| |- `----| | + | `-' `-' `-' `-' `-' + | Slot 0 10 11 12 13 + | REQ# 0 1 2 * + | GNT# 0 1 2 * + +-------------------------------------------------------------------------*/ + unsigned char int_line = 0xff; + + switch (PCI_DEV(dev)) { + case 10: - int_line = 31; /* INT A */ ++ int_line = 31; /* INT A */ + POST_OUT(0x42); + break; + + case 11: + int_line = 30; /* INT B */ + POST_OUT(0x43); + break; + + case 12: + int_line = 29; /* INT C */ + POST_OUT(0x44); + break; + + case 13: + int_line = 28; /* INT D */ + POST_OUT(0x45); + break; + } + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); + } + + extern void pci_405gp_init(struct pci_controller *hose); + extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev); + extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry); + /* + * The following table is used when there is a special need to setup a PCI device. + * For every PCI device found in this table is called the given init function with given + * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same + * parameters! + * + */ + static struct pci_config_table pci_solidcard3_config_table[] = + { + /* Host to PCI Bridge device (405GP) */ + { + vendor: 0x1014, + device: 0x0156, + class: PCI_CLASS_BRIDGE_HOST, + bus: 0, + dev: 0, + func: 0, + config_device: pci_405gp_setup_bridge + }, + { } + }; + + /*-------------------------------------------------------------------------+ + | pci_init_board (Called from pci_init() in drivers/pci.c) + | + | Init the PCI part of the SolidCard III + | + | Params: + * - Pointer to current PCI hose + * - Current Device + * + * Returns + * nothing + +-------------------------------------------------------------------------*/ + + void pci_init_board(void) + { + POST_OUT(0x41); + /* + * we want the ptrs to RAM not flash (ie don't use init list) + */ + hose.fixup_irq = pci_solidcard3_fixup_irq; + hose.config_table = pci_solidcard3_config_table; + pci_405gp_init(&hose); + } diff --cc board/uc101/uc101.c index 90624e5cef,0000000000..b803585845 mode 100644,000000..100644 --- a/board/uc101/uc101.c +++ b/board/uc101/uc101.c @@@ -1,374 -1,0 +1,371 @@@ +/* + * (C) Copyright 2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* some SIMPLE GPIO Pins */ +#define GPIO_USB_8 (31-12) +#define GPIO_USB_7 (31-13) +#define GPIO_USB_6 (31-14) +#define GPIO_USB_0 (31-15) +#define GPIO_PSC3_7 (31-18) +#define GPIO_PSC3_6 (31-19) +#define GPIO_PSC3_1 (31-22) +#define GPIO_PSC3_0 (31-23) + +/* some simple Interrupt GPIO Pins */ +#define GPIO_PSC3_8 2 +#define GPIO_USB1_9 3 + +#define GPT_OUT_0 0x00000027 +#define GPT_OUT_1 0x00000037 +#define GPT_DISABLE 0x00000000 /* GPT pin disabled */ + +#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \ + pgpio->simple_ddr |= (1 << n); \ + pgpio->simple_gpioe |= (1 << n); \ + } + +#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \ + pgpio->simple_gpioe |= (1 << n); \ + } + +#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \ + (pgpio->simple_dvo | (1 << n)) : \ + (pgpio->simple_dvo & ~(1 << n)) ) - ++ +#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1) +#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1) + - - +#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \ + (pgpio->sint_dvo | (1 << n)) : \ + (pgpio->sint_dvo & ~(1 << n)) ) + +#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \ + pgpio->sint_ddr |= (1 << n); \ + GP_SINT_SET_O(n, v); \ + pgpio->sint_gpioe |= (1 << n); \ + } + +#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \ + pgpio->sint_gpioe |= (1 << n); \ + } + +#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1) +#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1) + +#define GP_TIMER_ENABLE_O(n, v) ( \ + ((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \ + GPT_OUT_1 : \ + GPT_OUT_0 ) + +#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v) + +#define GP_TIMER_GET_O(n, v) ( \ + (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4) + +#define GP_TIMER_GET_I(n, v) ( \ + (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8) + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + +/* return dramsize + dramsize2; */ + return dramsize; +} + +int checkboard (void) +{ + puts ("Board: MAN UC101\n"); + return 0; +} + +static void init_ports (void) +{ - volatile struct mpc5xxx_gpio *pgpio = ++ volatile struct mpc5xxx_gpio *pgpio = + (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */ + GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */ + GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */ + GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */ + GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */ + GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */ + GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */ + GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */ + GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */ + GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */ + GP_TIMER_ENABLE_O(4, 0); /* LED H4 */ + GP_TIMER_ENABLE_O(5, 0); /* LED H5 */ + GP_TIMER_ENABLE_O(3, 0); /* LED HB */ + GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */ +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +struct kbd_data_t { + char s1; +}; + +struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) +{ + volatile struct mpc5xxx_gpio *pgpio = + (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + + kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \ + GP_SIMP_GET_I(GPIO_USB_7) << 2 | \ + GP_SIMP_GET_I(GPIO_USB_6) << 1 | \ + GP_SIMP_GET_I(GPIO_USB_0) << 0; + return kbd_data; +} + +static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str) +{ + char s1 = str[0]; + + if (s1 >= '0' && s1 <= '9') + s1 -= '0'; + else if (s1 >= 'a' && s1 <= 'f') + s1 = s1 - 'a' + 10; + else if (s1 >= 'A' && s1 <= 'F') + s1 = s1 - 'A' + 10; + else + return -1; + + if (s1 != kbd_data->s1) return -1; + return 0; +} + +static uchar *key_match (const struct kbd_data_t *kbd_data) +{ + uchar magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + uchar *kbd_magic_keys; + + /* + * The following string defines the characters that can be appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix = kbd_magic_keys; *suffix || + suffix == kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + + if (compare_magic(kbd_data, getenv(magic)) == 0) { + uchar cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv (cmd_name); + + return (cmd); + } + } + + return (NULL); +} + +#endif /* CONFIG_PREBOOT */ + +int misc_init_r (void) +{ + /* Init the I/O ports */ + init_ports (); + +#ifdef CONFIG_PREBOOT + struct kbd_data_t kbd_data; + /* Decode keys */ + uchar *str = strdup (key_match (get_keys (&kbd_data))); + /* Set or delete definition */ + setenv ("preboot", str); + free (str); +#endif /* CONFIG_PREBOOT */ + return 0; +} + +int board_early_init_r (void) +{ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + *(vu_long *)MPC5XXX_BOOTCS_START = + *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); + *(vu_long *)MPC5XXX_BOOTCS_STOP = + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); + /* Interbus enable it here ?? */ + *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1; + return 0; +} +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + /* Trigger HW Watchdog with TIMER_0 */ + *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1; + *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0; +} +#endif - diff --cc cpu/mpc8xx/serial.c index c8caa793d2,8ae584f2e1..9d0fc6b4fa --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@@ -227,17 -227,8 +227,17 @@@ static int smc_init (void sp->smc_smcm = 0; sp->smc_smce = 0xff; -#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */ - *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff; +#ifdef CFG_SPC1920_SMC1_CLK4 + /* clock source is PLD */ - ++ + /* set freq to 19200 Baud */ + *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3; + /* configure clk4 as input */ + im->im_ioport.iop_pdpar |= 0x800; + im->im_ioport.iop_pddir &= ~0x800; - ++ + cp->cp_simode = 0x0000; - cp->cp_simode |= 0x7000; ++ cp->cp_simode |= 0x7000; #else /* Set up the baud rate generator */ smc_setbrg (); diff --cc cpu/ppc4xx/cpu_init.c index db0559b04d,9e24b33f5a..e2aa867c94 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@@ -219,6 -221,6 +219,10 @@@ void set_chip_gpio_configuration(gpio_p void cpu_init_f (void) { ++#if defined(CONFIG_WATCHDOG) ++ unsigned long val; ++#endif ++ #if defined(CONFIG_405EP) /* * GPIO0 setup (select GPIO or alternate function) @@@ -309,9 -311,13 +313,12 @@@ mtebc(pb7cr, CFG_EBC_PB7CR); #endif - #if defined(CONFIG_WATCHDOG) - unsigned long val; + #if defined (CONFIG_SOLIDCARD3) -mtebc(epcr, 0xb84ef000); -*(unsigned long *)0x79000080 = 0x0001; ++ mtebc(epcr, 0xb84ef000); ++ *(unsigned long *)0x79000080 = 0x0001; + #endif -#if defined(CONFIG_WATCHDOG) - unsigned long val; ++#if defined(CONFIG_WATCHDOG) val = mfspr(tcr); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ diff --cc dtt/lm81.c index c83a3cdf63,0000000000..03bc53d58c mode 100644,000000..100644 --- a/dtt/lm81.c +++ b/dtt/lm81.c @@@ -1,148 -1,0 +1,148 @@@ +/* + * (C) Copyright 2006 + * Heiko Schocher, DENX Software Enginnering + * + * based on dtt/lm75.c which is ... + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * On Semiconductor's LM81 Temperature Sensor + */ + +#include + +#ifdef CONFIG_DTT_LM81 +#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ + (CFG_EEPROM_PAGE_WRITE_BITS < 1) +# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM81" +#endif + +#include +#include + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */ + +int dtt_read(int sensor, int reg) +{ + int dlen = 1; + uchar data[2]; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */ + + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return -1; + + return (int)data[0]; +} /* dtt_read() */ + + +int dtt_write(int sensor, int reg, int val) +{ + uchar data; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */ + + data = (char)(val & 0xff); + + /* + * Write value to register. + */ + if (i2c_write(sensor, reg, 1, &data, 1) != 0) + return 1; + + return 0; +} /* dtt_write() */ + +#define DTT_MANU 0x3e +#define DTT_REV 0x3f +#define DTT_CONFIG 0x40 +#define DTT_ADR 0x48 + +static int _dtt_init(int sensor) +{ + int man; + int adr; + int rev; + + if (dtt_write (sensor, DTT_CONFIG, 0x01) < 0) + return 1; + /* The LM81 needs 400ms to get the correct values ... */ + udelay (400000); + man = dtt_read (sensor, DTT_MANU); + if (man != 0x01) + return 1; + adr = dtt_read (sensor, DTT_ADR); + if (adr < 0) + return 1; + rev = dtt_read (sensor, DTT_REV); + if (adr < 0) + return 1; + + printf ("DTT: Found LM81@%x Rev: %d\n", adr, rev); + return 0; +} /* _dtt_init() */ + + +int dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("%s%d FAILED INIT\n", header, i+1); + else + printf("%s%d is %i C\n", header, i+1, + dtt_get_temp(sensors[i])); + } + + return (0); +} /* dtt_init() */ + +#define TEMP_FROM_REG(temp) \ - ((temp)<256?((((temp)&0x1fe) >> 1) * 10) + ((temp) & 1) * 5: \ - ((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5) \ ++ ((temp)<256?((((temp)&0x1fe) >> 1) * 10) + ((temp) & 1) * 5: \ ++ ((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5) \ + +int dtt_get_temp(int sensor) +{ + int val = dtt_read (sensor, DTT_READ_TEMP); + int tmpcnf = dtt_read (sensor, DTT_CONFIG_TEMP); + + return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10; +} /* dtt_get_temp() */ + +#endif /* CONFIG_DTT_LM81 */ diff --cc include/configs/solidcard3.h index 0000000000,0000000000..867cba5a35 new file mode 100644 --- /dev/null +++ b/include/configs/solidcard3.h @@@ -1,0 -1,0 +1,537 @@@ ++/* ++ * (C) Copyright 2007 ++ * Heiko Schocher, DENX Software Engineering, . ++ * ++ * From: ++ * (C) Copyright 2003 ++ * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#undef USE_VGA_GRAPHICS ++ ++/* Memory Map ++0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB) ++0x74000000 .... 0x740FFFFF -> CS#6 ++0x74100000 .... 0x741FFFFF -> CS#7 ++0x74200000 .... 0x742FFFFF -> CS4# if no internal USB ++0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE ++0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB) ++0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB) ++0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB) ++0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB) ++0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored) ++0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB) ++ ++0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1) ++0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF) ++0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF) ++0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF) ++0xEED00000 .... 0xEED00003 -> PCI-Bus ++0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers ++0xEF40003F .... 0xEF5FFFFF -> reserved ++0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB) ++0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB) ++0xF0200000 .... 0xF7FFFFFF -> free for flash devices ++0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB) ++0xF8001000 .... 0xFFDFFFFF -> free for flash devices ++0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB) ++*/ ++ ++#define CONFIG_SOLIDCARD3 1 ++#define CONFIG_4xx 1 ++#define CONFIG_405GP 1 ++ ++#define CONFIG_BOARD_EARLY_INIT_F 1 ++ ++/* ++ * define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range ++ * If undefed, IDE access uses a seperat emulation with higher access speed ++ * Consider to inform your Linux IDE driver about the different addresses! ++ * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes the CFG_CMD_IDE macro! ++ */ ++#define IDE_USES_ISA_EMULATION ++ ++/*----------------------------------------------------------------------- ++ * Serial Port ++ *----------------------------------------------------------------------*/ ++#define CONFIG_SERIAL_MULTI ++#undef CONFIG_SERIAL_SOFTWARE_FIFO ++/* ++ * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input ++ * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature ++ */ ++#if CONFIG_SERIAL_SOFTWARE_FIFO ++ #define CONFIG_POWER_DOWN ++#endif ++ ++/* ++ * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz ++ */ ++#define CONFIG_SYS_CLK_FREQ 33333333 ++ ++/* ++ * define CONFIG_BAUDRATE to the baudrate value you want to use as default ++ */ ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ ++ ++#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ ++#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ ++ ++#if 1 /* feel free to disable for development */ ++#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ ++#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n" ++#define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */ ++#endif ++ ++/* ++ * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after ++ * the CONFIG_BOOTDELAY delay to boot your machine ++ */ ++#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm" ++ ++/* ++ * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't ++ * set different values at the u-boot prompt ++ */ ++#ifdef USE_VGA_GRAPHICS ++ #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re" ++#else ++ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp" ++#endif ++/* ++ * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT ++ * This reserves memory bank #4 for this purpose ++ */ ++#undef CONFIG_ISP1161_PRESENT ++ ++#undef CONFIG_LOADS_ECHO /* no echo on for serial download */ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++#define CONFIG_NET_MULTI ++/* #define CONFIG_EEPRO100_SROM_WRITE */ ++/* #define CONFIG_SHOW_MAC */ ++#define CONFIG_EEPRO100 ++#define CONFIG_MII 1 /* add 405GP MII PHY management */ ++#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ ++ ++#define CONFIG_COMMANDS \ ++ (CONFIG_CMD_DFL | \ ++ CFG_CMD_PCI | \ ++ CFG_CMD_IRQ | \ ++ CFG_CMD_NET | \ ++ CFG_CMD_MII | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_IDE | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_ELF ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP 1 /* undef to save memory */ ++#define CFG_PROMPT "SC3> " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ ++ ++/* ++ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. ++ * If CFG_405_UART_ERRATA_59, then UART divisor is 31. ++ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. ++ * The Linux BASE_BAUD define should match this configuration. ++ * baseBaud = cpuClock/(uartDivisor*16) ++ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, ++ * set Linux BASE_BAUD to 403200. ++ * ++ * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to ++ * (see 405GP datasheet for descritpion) ++ */ ++#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ ++#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ ++#define CFG_BASE_BAUD 921600 /* internal clock */ ++ ++/* The following table includes the supported baudrates */ ++#define CFG_BAUDRATE_TABLE \ ++ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} ++ ++#define CFG_LOAD_ADDR 0x1000000 /* default load address */ ++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ ++ ++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ ++ ++/*----------------------------------------------------------------------- ++ * IIC stuff ++ *----------------------------------------------------------------------- ++ */ ++#define CONFIG_HARD_I2C /* I2C with hardware support */ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++ ++#define I2C_INIT ++#define I2C_ACTIVE 0 ++#define I2C_TRISTATE 0 ++ ++#define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */ ++#define CFG_I2C_SLAVE 0x7F /* mask valid bits */ ++ ++#define CONFIG_RTC_DS1337 ++#define CFG_I2C_RTC_ADDR 0x68 ++ ++/*----------------------------------------------------------------------- ++ * PCI stuff ++ *----------------------------------------------------------------------- ++ */ ++#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ ++#define PCI_HOST_FORCE 1 /* configure as pci host */ ++#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ ++ ++#define CONFIG_PCI /* include pci support */ ++#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++ /* resource configuration */ ++ ++/* If you want to see, whats connected to your PCI bus */ ++/* #define CONFIG_PCI_SCAN_SHOW */ ++ ++#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ ++#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ ++#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ ++#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ ++#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ ++#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ ++#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ ++#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ ++ ++/*----------------------------------------------------------------------- ++ * External peripheral base address ++ *----------------------------------------------------------------------- ++ */ ++#if !(CONFIG_COMMANDS & CFG_CMD_IDE) ++ ++#undef CONFIG_IDE_LED /* no led for ide supported */ ++#undef CONFIG_IDE_RESET /* no reset for ide supported */ ++ ++/*----------------------------------------------------------------------- ++ * IDE/ATA stuff ++ *----------------------------------------------------------------------- ++ */ ++#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */ ++#define CONFIG_START_IDE 1 /* check, if use IDE */ ++ ++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ ++#undef CONFIG_IDE_LED /* no led for ide supported */ ++#undef CONFIG_IDE_RESET /* no reset for ide supported */ ++ ++#define CONFIG_ATAPI ++#define CONFIG_DOS_PARTITION ++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ ++ ++#ifndef IDE_USES_ISA_EMULATION ++ ++/* New and faster access */ ++#define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */ ++ ++/* How many IDE busses are available */ ++#define CFG_IDE_MAXBUS 1 ++ ++/* What IDE ports are available */ ++#define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */ ++#undef CFG_ATA_IDE1_OFFSET /* second not available */ ++ ++/* access to the data port is calculated: ++ CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */ ++#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ ++ ++/* access to the registers is calculated: ++ CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */ ++#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ ++ ++/* access to the alternate register is calculated: ++ CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */ ++#define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */ ++ ++#else /* IDE_USES_ISA_EMULATION */ ++ ++#define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */ ++ ++/* How many IDE busses are available */ ++#define CFG_IDE_MAXBUS 1 ++ ++/* What IDE ports are available */ ++#define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */ ++#undef CFG_ATA_IDE1_OFFSET /* second not available */ ++ ++/* access to the data port is calculated: ++ CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */ ++#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ ++ ++/* access to the registers is calculated: ++ CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */ ++#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ ++ ++/* access to the alternate register is calculated: ++ CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */ ++#define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */ ++ ++#endif /* IDE_USES_ISA_EMULATION */ ++ ++#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */ ++ ++/* ++#define CFG_KEY_REG_BASE_ADDR 0xF0100000 ++#define CFG_IR_REG_BASE_ADDR 0xF0200000 ++#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 ++*/ ++ ++/*----------------------------------------------------------------------- ++ * Start addresses for the final memory configuration ++ * (Set up by the startup code) ++ * Please note that CFG_SDRAM_BASE _must_ start at 0 ++ * ++ * CFG_FLASH_BASE -> start address of internal flash ++ * CFG_MONITOR_BASE -> start of u-boot ++ */ ++#ifndef __ASSEMBLER__ ++extern unsigned long offsetOfBigFlash; ++extern unsigned long offsetOfEnvironment; ++#endif ++ ++#define CFG_SDRAM_BASE 0x00000000 ++#define CFG_FLASH_BASE 0xFFE00000 ++#define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */ ++#define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */ ++#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MiB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++/*----------------------------------------------------------------------- ++ * FLASH organization ## FIXME: lookup in datasheet ++ */ ++#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ ++ ++#define CFG_FLASH_CFI /* flash is CFI compat. */ ++#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ ++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ ++#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ ++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ ++#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ ++ ++#define CFG_ENV_IS_IN_FLASH 1 ++#if CFG_ENV_IS_IN_FLASH ++ #define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */ ++ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ ++ #define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ ++#endif ++/* let us changing anything in our environment */ ++#define CONFIG_ENV_OVERWRITE ++ ++/* ++ * NAND-FLASH stuff ++ */ ++#define CFG_MAX_NAND_DEVICE 1 ++#define NAND_MAX_CHIPS 1 ++#define CFG_NAND_BASE 0x77D00000 ++ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ * ++ * CFG_DCACHE_SIZE -> size of data cache: ++ * - 405GP 8k ++ * - 405GPr 16k ++ * How to handle the difference in chache size? ++ * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes ++ * (used in cpu/ppc4xx/start.S) ++*/ ++#define CFG_DCACHE_SIZE 16384 ++ ++#define CFG_CACHELINE_SIZE 32 ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++/* ++ * Init Memory Controller: ++ * ++ */ ++ ++#define FLASH_BASE0_PRELIM CFG_FLASH_BASE ++#define FLASH_BASE1_PRELIM 0 ++ ++/*----------------------------------------------------------------------- ++ * Some informations about the internal SRAM (OCM=On Chip Memory) ++ * ++ * CFG_OCM_DATA_ADDR -> location ++ * CFG_OCM_DATA_SIZE -> size ++*/ ++ ++#define CFG_TEMP_STACK_OCM 1 ++#define CFG_OCM_DATA_ADDR 0xF8000000 ++#define CFG_OCM_DATA_SIZE 0x1000 ++ ++/*----------------------------------------------------------------------- ++ * Definitions for initial stack pointer and data area (in DPRAM): ++ * - we are using the internal 4k SRAM, so we don't need data cache mapping ++ * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR ++ * - Stackpointer will be located to ++ * (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF) ++ * in cpu/ppc4xx/start.S ++ */ ++ ++#undef CFG_INIT_DCACHE_CS ++/* Where the internal SRAM starts */ ++#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR ++/* Where the internal SRAM ends (only offset) */ ++#define CFG_INIT_RAM_END 0x0F00 ++ ++/* ++ ++ CFG_INIT_RAM_ADDR ------> ------------ lower address ++ | | ++ | ^ | ++ | | | ++ | | Stack | ++ CFG_GBL_DATA_OFFSET ----> ------------ ++ | | ++ | 64 Bytes | ++ | | ++ CFG_INIT_RAM_END ------> ------------ higher address ++ (offset only) ++ ++*/ ++/* size in bytes reserved for initial data */ ++#define CFG_GBL_DATA_SIZE 64 ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++/* Initial value of the stack pointern in internal SRAM */ ++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++/* ################################################################################### */ ++/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */ ++/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ ++ ++/* This chip select accesses the boot device */ ++/* It depends on boot select switch if this device is 16 or 8 bit */ ++ ++#undef CFG_EBC_PB0AP ++#undef CFG_EBC_PB0CR ++ ++#undef CFG_EBC_PB1AP ++#undef CFG_EBC_PB1CR ++ ++#undef CFG_EBC_PB2AP ++#undef CFG_EBC_PB2CR ++ ++#undef CFG_EBC_PB3AP ++#undef CFG_EBC_PB3CR ++ ++#undef CFG_EBC_PB4AP ++#undef CFG_EBC_PB4CR ++ ++#undef CFG_EBC_PB5AP ++#undef CFG_EBC_PB5CR ++ ++#undef CFG_EBC_PB6AP ++#undef CFG_EBC_PB6CR ++ ++#undef CFG_EBC_PB7AP ++#undef CFG_EBC_PB7CR ++ ++#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */ ++#undef CONFIG_SPD_EEPROM ++ ++/* ++ * Define this to get more information about system configuration ++ */ ++/* #define SC3_DEBUGOUT */ ++#undef SC3_DEBUGOUT ++ ++/*********************************************************************** ++ * External peripheral base address ++ ***********************************************************************/ ++ ++#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000 ++/* ++ Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu. ++ Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die ++ das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen ++ auf ISA- und PCI-Zyklen) ++ */ ++#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 ++/*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */ ++ ++/************************************************************ ++ * Video support ++ ************************************************************/ ++ ++#ifdef USE_VGA_GRAPHICS ++#define CONFIG_VIDEO /* To enable video controller support */ ++#define CONFIG_VIDEO_CT69000 ++#define CONFIG_CFB_CONSOLE ++/* #define CONFIG_VIDEO_LOGO */ ++#define CONFIG_VGA_AS_SINGLE_DEVICE ++#define CONFIG_VIDEO_SW_CURSOR ++/* #define CONFIG_VIDEO_HW_CURSOR */ ++#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ ++ ++#define VIDEO_HW_RECTFILL ++#define VIDEO_HW_BITBLT ++ ++#endif ++ ++/************************************************************ ++ * Ident ++ ************************************************************/ ++#define CONFIG_SC3_VERSION "r1.4" ++ ++#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x) ++ ++#endif /* __CONFIG_H */