From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 19:02:11 +0000 (-0600)
Subject: ARM: tegra: p2371-2180: A03 board PMIC config update
X-Git-Tag: v2016.09-rc1~71^2~2
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=efbb3d491e87935421242396958fdddd87e0fde1;hp=49626ea801e8bb33c9ee4cbcb69e2fea6b13c330;p=oweals%2Fu-boot.git

ARM: tegra: p2371-2180: A03 board PMIC config update

Rev A03 of P2180 requires some PMIC programming adjustments, yet the
PMIC's own OTP has not been updated. Consequently, U-Boot must make
these changes itself.

NVIDIA's syseng team has confirmed that these changes can be enabled on
all board revisions without issue.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---

diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c
index 0f587eaaa7..dbdc1b65e6 100644
--- a/board/nvidia/p2371-2180/p2371-2180.c
+++ b/board/nvidia/p2371-2180/p2371-2180.c
@@ -30,6 +30,28 @@ void pin_mux_mmc(void)
 	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
 	if (ret)
 		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+	/* Disable LDO4 discharge */
+	ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+	if (ret) {
+		printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+	} else {
+		val &= ~BIT(1); /* ADE */
+		ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+	}
+
+	/* Set MBLPD */
+	ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+	if (ret) {
+		printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	} else {
+		val |= BIT(6); /* MBLPD */
+		ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	}
 }
 
 /*
diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h
index 92c3719112..39e550149a 100644
--- a/board/nvidia/p2571/max77620_init.h
+++ b/board/nvidia/p2571/max77620_init.h
@@ -13,6 +13,8 @@
 #define MAX77620_I2C_ADDR		0x78
 #define MAX77620_I2C_ADDR_7BIT		0x3C
 
+#define MAX77620_CNFGGLBL1_REG		0x00
+
 #define MAX77620_SD0_REG		0x16
 #define MAX77620_SD1_REG		0x17
 #define MAX77620_SD2_REG		0x18